CN115987460B - Data transmission method, device, equipment and medium based on check code - Google Patents
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Abstract
The invention relates to the technical field of data processing, and provides a data transmission method, a device, equipment and a medium based on check codes, which can copy an initial data packet in each period to obtain a data packet to be processed and divide the data packet into two paths of processing, wherein one path calculates a target ICRC check code based on the data packet to be processed and a lookup table prestored in a register, and the other path adopts a D trigger to delay the initial data packet, further adds the target ICRC check code to the tail part of the initial data packet after delay processing to obtain the data packet to be transmitted, and issues the check code of the data packet to be transmitted, so that the check code of any byte of the data packet is generated rapidly, and the data packet is assisted to carry out safe and rapid transmission.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a method, an apparatus, a device, and a medium for data transmission based on check codes.
Background
In data transmission, in order to ensure the security and effectiveness of data, a check code is usually required to be generated.
For example: when a system including an FPGA (Field Programmable Gate Array ) requires RDMA (Remote Direct Memory Access, remote direct data access) transmission for low latency, the FPGA needs to construct RDMA packets by itself, and one of the most important loops is to calculate the cyclic check code ICRC (Invariant Cyclic Redundancy Check, unchanged cyclic redundancy check). On the one hand, in a system pursuing low time delay and extremely high data throughput, it is important whether the ICRC of each data can be iterated out rapidly, otherwise, the risk of cache overflow caused by untimely data processing needs to be borne; on the other hand, the data part is filled by a user, the specific value of the length of the data within a certain range is unpredictable, the network transmission generally adopts a data bus with the width of 4 bytes and 32 bits, 4 bytes are aligned during normal transmission, and one cycle needs to iterate ICRC of 4 bytes of data. However, in the last cycle of transmission, there is a possibility that non-4 bytes of data may be present, and in this case, non-four byte aligned data needs to be processed in that cycle.
In view of the foregoing, there is a need for an ICRC packet generation scheme that is fast and supports arbitrary byte iterations to facilitate data transmission.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, apparatus, device and medium for transmitting data based on check codes, which can quickly generate check codes of data packets with arbitrary bytes to assist in transmitting the data packets.
A data transmission method based on a check code, the data transmission method based on the check code comprising:
in each period, acquiring an initial data packet;
copying the initial data packet to obtain a data packet to be processed;
calculating a target ICRC check code based on the data packet to be processed and a lookup table pre-stored in a register;
adopting a D trigger to delay the initial data packet;
adding the target ICRC check code to the tail of the initial data packet after delay processing to obtain a data packet to be transmitted;
and transmitting the data packet to be transmitted.
According to a preferred embodiment of the present invention, the calculating the target ICRC check code based on the pending data packet and a lookup table pre-stored in a register includes:
generating calculation data according to the data packet to be processed;
Determining the byte number of the data packet to be processed;
selecting a target lookup table from the register based on the byte count using a request arbiter;
processing the calculated data by utilizing a circuit corresponding to the target lookup table to obtain first data;
obtaining output data corresponding to other lookup tables in the register, and obtaining an ICRC check code obtained by calculation of the previous period;
performing exclusive-or operation on the first data, the output data corresponding to the other lookup tables and the ICRC check code obtained by the previous period calculation to obtain second data;
and performing bit inversion operation on the second data to obtain the target ICRC check code.
According to a preferred embodiment of the present invention, the generating calculation data according to the data packet to be processed includes:
deleting eth header in the RDMA data packet when the data packet to be processed is the RDMA data packet;
filling an LRH field of infiniband in the RDMA data packet into 0 xffffffffff_ffffffff;
replacing a type of service field and a time to live field of an IP header in the RDMA data packet with 0xff, and replacing a header checksum field of the IP header in the RDMA data packet with 0 xff;
And replacing the reserve field of the infiniband header with 0xff to obtain the calculation data.
According to a preferred embodiment of the present invention, the calculating the target ICRC check code based on the pending data packet and a look-up table stored in a register in advance further includes:
in an initial period, after the first data is obtained, obtaining output data corresponding to other lookup tables in the register, and obtaining a pre-configured initial ICRC check code;
and performing exclusive OR operation on the first data, the output data corresponding to the other lookup tables and the initial ICRC check code to obtain the second data.
According to a preferred embodiment of the present invention, before the calculating the target ICRC check code based on the data packet to be processed and the lookup table stored in the register in advance, the method further includes:
configuring a corresponding lookup table for each byte number and a circuit corresponding to each lookup table;
storing the lookup table into the register.
According to a preferred embodiment of the present invention, the adding the target ICRC check code to the tail of the initial data packet after the delay processing, to obtain the data packet to be transmitted includes:
and when the preset mark in the initial data packet after the delay processing is detected, adding the target ICRC check code to the tail part of the initial data packet after the delay processing to obtain the data packet to be transmitted.
A data transmission apparatus based on a check code, the data transmission apparatus based on a check code comprising:
an acquisition unit, configured to acquire an initial data packet in each period;
the copying unit is used for copying the initial data packet to obtain a data packet to be processed;
the calculating unit is used for calculating a target ICRC check code based on the data packet to be processed and a lookup table pre-stored in a register;
the delay unit is used for carrying out delay processing on the initial data packet by adopting a D trigger;
an adding unit, configured to add the target ICRC check code to the tail of the initial data packet after delay processing, to obtain a data packet to be transmitted;
and the issuing unit is used for issuing the data packet to be transmitted.
A computer device, the computer device comprising:
a memory storing at least one instruction; and
And the processor executes the instructions stored in the memory to realize the data transmission method based on the check code.
A computer-readable storage medium having stored therein at least one instruction that is executed by a processor in a computer device to implement the check code based data transmission method.
According to the technical scheme, the method and the device can copy the initial data packet in each period to obtain the data packet to be processed, and divide the data packet into two paths of processing, wherein one path calculates the target ICRC check code based on the data packet to be processed and the lookup table stored in the register in advance, and the other path adopts the D trigger to delay the initial data packet, further adds the target ICRC check code to the tail part of the initial data packet after delay processing to obtain the data packet to be transmitted, and issues the data packet to be transmitted, and further rapidly generates the check code of the data packet with any byte so as to assist the data packet to carry out safe and rapid transmission.
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Fig. 1 is a flow chart of a data transmission method based on check codes according to a preferred embodiment of the present invention.
Fig. 2 is a functional block diagram of a data transmission device based on check codes according to a preferred embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a computer device according to a preferred embodiment of the present invention for implementing a data transmission method based on check codes.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a flowchart of a data transmission method based on check codes according to a preferred embodiment of the present invention. The order of the steps in the flowchart may be changed and some steps may be omitted according to various needs.
The data transmission method based on the check code is applied to one or more computer devices, wherein the computer device is a device capable of automatically performing numerical calculation and/or information processing according to preset or stored instructions, and the hardware of the computer device comprises, but is not limited to, a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a programmable gate array (Field-Programmable Gate Array, FPGA), a digital processor (Digital Signal Processor, DSP), an embedded device and the like.
The computer device may be any electronic product that can interact with a user in a human-computer manner, such as a personal computer, tablet computer, smart phone, personal digital assistant (Personal Digital Assistant, PDA), game console, interactive internet protocol television (Internet Protocol Television, IPTV), smart wearable device, etc.
The computer device may also include a network device and/or a user device. Wherein the network device includes, but is not limited to, a single network server, a server group composed of a plurality of network servers, or a Cloud based Cloud Computing (Cloud Computing) composed of a large number of hosts or network servers.
The server may be an independent server, or may be a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (Content Delivery Network, CDN), and basic cloud computing services such as big data and artificial intelligence platforms.
Among these, artificial intelligence (Artificial Intelligence, AI) is the theory, method, technique and application system that uses a digital computer or a digital computer-controlled machine to simulate, extend and extend human intelligence, sense the environment, acquire knowledge and use knowledge to obtain optimal results.
Artificial intelligence infrastructure technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technologies, operation/interaction systems, mechatronics, and the like. The artificial intelligence software technology mainly comprises a computer vision technology, a robot technology, a biological recognition technology, a voice processing technology, a natural language processing technology, machine learning/deep learning and other directions.
The network in which the computer device is located includes, but is not limited to, the internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (Virtual Private Network, VPN), and the like.
S10, acquiring an initial data packet in each period.
In the present embodiment, the period may be determined according to the characteristics of the mounted system. For example: for FPGA systems, the period may be determined from the clock edge.
In this embodiment, the initial packet may be an RDMA (Remote Direct Memory Access, remote direct data access) packet. For example: the initial data packet may be a data packet based on a RocEv2 protocol, where RocEv2 is one of hardware implementation manners of RDMA technology, has advantages of low latency, low overhead of CPU (Central Processing Unit ) and high bandwidth, and is a common transmission protocol for low-latency systems.
S11, copying the initial data packet to obtain a data packet to be processed.
In this embodiment, the data packet to be processed obtained by replication is the same as the initial data packet.
After replication, the copy can be divided into two paths for processing.
S12, calculating a target ICRC (Invariant Cyclic Redundancy Check, constant cyclic redundancy check) check code based on the data packet to be processed and a lookup table pre-stored in a register.
In this embodiment, before the calculating the target ICRC check code based on the data packet to be processed and the lookup table stored in the register in advance, the method further includes:
Configuring a corresponding lookup table for each byte number and a circuit corresponding to each lookup table;
storing the lookup table into the register.
For example: the number of bytes can be 1 byte, 2 bytes, 3 bytes and 4 bytes, and in this embodiment, the lookup tables are configured for each byte number respectively, and corresponding circuits are configured for each lookup table. Further, the lookup table is stored in the register, and the register can perform quick reading and writing, so that the generation speed of the ICRC check code is improved, and the ICRC check code of data carried by the data bus can be iterated out quickly in one period.
It will be appreciated that a data bus of 32 bits width of 4 bytes is typically used for network transmission on devices such as FPGAs, but that specific values of the data length within a certain range are unpredictable because the data portion is user-filled, 4 bytes are aligned during normal transmission, one cycle requires iteration of the ICRC of 4 bytes of data, and non-4 bytes of data may occur during the last cycle of transmission, which requires processing of this non-four byte aligned data during this cycle.
However, currently, in a system, only one byte of data can be used, and a scenario that a 32-bit data bus is not aligned with 4 bytes for transmission cannot be simultaneously supported, and in this case, a lookup table is configured according to the embodiment, and multiple byte alignments are supported based on the lookup table.
Specifically, the calculating the target ICRC check code based on the data packet to be processed and a lookup table stored in a register in advance includes:
generating calculation data according to the data packet to be processed;
determining the byte number of the data packet to be processed;
selecting a target lookup table from the register based on the byte count using a request arbiter;
processing the calculated data by utilizing a circuit corresponding to the target lookup table to obtain first data;
obtaining output data corresponding to other lookup tables in the register, and obtaining an ICRC check code obtained by calculation of the previous period;
performing exclusive-or operation on the first data, the output data corresponding to the other lookup tables and the ICRC check code obtained by the previous period calculation to obtain second data;
and performing bit inversion operation on the second data to obtain the target ICRC check code.
The calculation data are used for calculating the target ICRC check code subsequently.
Wherein the generating calculation data according to the data packet to be processed includes:
deleting eth header in the RDMA data packet when the data packet to be processed is the RDMA data packet;
filling an LRH field of infiniband in the RDMA data packet into 0 xffffffffff_ffffffff;
Replacing a type of service field and a time to live field of an IP header in the RDMA data packet with 0xff, and replacing a header checksum field of the IP header in the RDMA data packet with 0 xff;
and replacing the reserve field of the infiniband header with 0xff to obtain the calculation data.
Through the above-described embodiments, it is possible to prepare the relevant data for calculating the target ICRC check code.
In this embodiment, the calculating the target ICRC check code based on the data packet to be processed and the lookup table stored in the register in advance further includes:
in an initial period, after the first data is obtained, obtaining output data corresponding to other lookup tables in the register, and obtaining a pre-configured initial ICRC check code;
and performing exclusive OR operation on the first data, the output data corresponding to the other lookup tables and the initial ICRC check code to obtain the second data.
S13, adopting a D trigger to delay the initial data packet.
And (3) delaying the initial data packet to make one path of data be one beat slower than the other path of data, so that after the target ICRC check code is calculated, the target ICRC check code and the initial data packet can be just fused.
S14, adding the target ICRC check code to the tail of the initial data packet after delay processing to obtain a data packet to be transmitted.
In this embodiment, the adding the target ICRC check code to the tail of the initial data packet after the delay processing, to obtain the data packet to be transmitted includes:
and when the preset mark in the initial data packet after the delay processing is detected, adding the target ICRC check code to the tail part of the initial data packet after the delay processing to obtain the data packet to be transmitted.
The preset flag may be last, which is used to mark the last data in the data packet.
For example: the ICRC check code is calculated streamed for the RDMA packets transmitted in the preceding stage and the RDMA packets are sent in real time to the succeeding stage. The ICRC is also calculated and completed at the same time when the last byte of the RDMA data packet is transmitted, and the ICRC is appended at the tail of the RDMA data packet, so that a complete RDMA packet is constructed.
S15, the data packet to be transmitted is issued.
Through the above embodiment, the complete data packet with the check code can be issued to the downstream.
The embodiment can be used for various scenes requiring calculation of the crc32, such as a scene which is designed to run in an FPGA and has a RocEv2 transmission requirement, or a scene which has a need for calculation of a RocEv2 check code.
It should be noted that, in this embodiment, an FPGA may be mounted and a modular design is adopted, so that, for an FPGA design that already supports a UDP (User Datagram Protocol ) protocol, RDMA transmission may be well supported through simple modification. For example: the above-mentioned process of generating calculation data can be constructed as a module (such as an infiniband protocol processing module), and the process of generating the ICRC check code can be constructed as a module (ICRC check code generating module), so that for the FPGA application which already supports the UDP protocol, only the infiniband protocol processing module needs to be inserted between the application and the UDP packaging processing module, and then the ICRC check code generating module is inserted immediately before the network packet output network, so that the conversion from the UDP to the RDMA protocol can be completed.
According to the technical scheme, the method and the device can copy the initial data packet in each period to obtain the data packet to be processed, and divide the data packet into two paths of processing, wherein one path calculates the target ICRC check code based on the data packet to be processed and the lookup table stored in the register in advance, and the other path adopts the D trigger to delay the initial data packet, further adds the target ICRC check code to the tail part of the initial data packet after delay processing to obtain the data packet to be transmitted, and issues the data packet to be transmitted, and further rapidly generates the check code of the data packet with any byte so as to assist the data packet to carry out safe and rapid transmission.
Fig. 2 is a functional block diagram of a data transmission device based on check codes according to a preferred embodiment of the present invention. The data transmission device 11 based on the check code includes an acquisition unit 110, a replication unit 111, a calculation unit 112, a delay unit 113, an addition unit 114, and a transmission unit 115. The module/unit referred to in the present invention refers to a series of computer program segments, which are stored in a memory, capable of being executed by a processor and of performing a fixed function. In the present embodiment, the functions of the respective modules/units will be described in detail in the following embodiments.
The acquiring unit 110 is configured to acquire an initial data packet in each period.
In the present embodiment, the period may be determined according to the characteristics of the mounted system. For example: for FPGA systems, the period may be determined from the clock edge.
In this embodiment, the initial packet may be an RDMA (Remote Direct Memory Access, remote direct data access) packet. For example: the initial data packet may be a data packet based on a RocEv2 protocol, where RocEv2 is one of hardware implementation manners of RDMA technology, has advantages of low latency, low overhead of CPU (Central Processing Unit ) and high bandwidth, and is a common transmission protocol for low-latency systems.
The copying unit 111 is configured to copy the initial data packet to obtain a data packet to be processed.
In this embodiment, the data packet to be processed obtained by replication is the same as the initial data packet.
After replication, the copy can be divided into two paths for processing.
The calculating unit 112 is configured to calculate a target ICRC (Invariant Cyclic Redundancy Check, unchanged cyclic redundancy check) check code based on the data packet to be processed and a lookup table stored in a register in advance.
In this embodiment, before calculating the target ICRC check code based on the data packet to be processed and the lookup table stored in the register in advance, a corresponding lookup table and a circuit corresponding to each lookup table are configured for each byte number;
storing the lookup table into the register.
For example: the number of bytes can be 1 byte, 2 bytes, 3 bytes and 4 bytes, and in this embodiment, the lookup tables are configured for each byte number respectively, and corresponding circuits are configured for each lookup table. Further, the lookup table is stored in the register, and the register can perform quick reading and writing, so that the generation speed of the ICRC check code is improved, and the ICRC check code of data carried by the data bus can be iterated out quickly in one period.
It will be appreciated that a data bus of 32 bits width of 4 bytes is typically used for network transmission on devices such as FPGAs, but that specific values of the data length within a certain range are unpredictable because the data portion is user-filled, 4 bytes are aligned during normal transmission, one cycle requires iteration of the ICRC of 4 bytes of data, and non-4 bytes of data may occur during the last cycle of transmission, which requires processing of this non-four byte aligned data during this cycle.
However, currently, in a system, only one byte of data can be used, and a scenario that a 32-bit data bus is not aligned with 4 bytes for transmission cannot be simultaneously supported, and in this case, a lookup table is configured according to the embodiment, and multiple byte alignments are supported based on the lookup table.
Specifically, the calculating unit 112 calculates a target ICRC check code based on the data packet to be processed and a lookup table stored in a register in advance, including:
generating calculation data according to the data packet to be processed;
determining the byte number of the data packet to be processed;
selecting a target lookup table from the register based on the byte count using a request arbiter;
processing the calculated data by utilizing a circuit corresponding to the target lookup table to obtain first data;
Obtaining output data corresponding to other lookup tables in the register, and obtaining an ICRC check code obtained by calculation of the previous period;
performing exclusive-or operation on the first data, the output data corresponding to the other lookup tables and the ICRC check code obtained by the previous period calculation to obtain second data;
and performing bit inversion operation on the second data to obtain the target ICRC check code.
The calculation data are used for calculating the target ICRC check code subsequently.
Wherein the generating calculation data according to the data packet to be processed includes:
deleting eth header in the RDMA data packet when the data packet to be processed is the RDMA data packet;
filling an LRH field of infiniband in the RDMA data packet into 0 xffffffffff_ffffffff;
replacing a type of service field and a time to live field of an IP header in the RDMA data packet with 0xff, and replacing a header checksum field of the IP header in the RDMA data packet with 0 xff;
and replacing the reserve field of the infiniband header with 0xff to obtain the calculation data.
Through the above-described embodiments, it is possible to prepare the relevant data for calculating the target ICRC check code.
In this embodiment, the calculating unit 112 calculates the target ICRC check code based on the data packet to be processed and a lookup table stored in a register in advance further includes:
In an initial period, after the first data is obtained, obtaining output data corresponding to other lookup tables in the register, and obtaining a pre-configured initial ICRC check code;
and performing exclusive OR operation on the first data, the output data corresponding to the other lookup tables and the initial ICRC check code to obtain the second data.
The delay unit 113 is configured to delay the initial data packet by using a D flip-flop.
And (3) delaying the initial data packet to make one path of data be one beat slower than the other path of data, so that after the target ICRC check code is calculated, the target ICRC check code and the initial data packet can be just fused.
The adding unit 114 is configured to add the target ICRC check code to the tail of the initial data packet after delay processing, to obtain a data packet to be transmitted.
In this embodiment, the adding unit 114 adds the target ICRC check code to the tail of the initial data packet after the delay processing, where obtaining the data packet to be transmitted includes:
and when the preset mark in the initial data packet after the delay processing is detected, adding the target ICRC check code to the tail part of the initial data packet after the delay processing to obtain the data packet to be transmitted.
The preset flag may be last, which is used to mark the last data in the data packet.
For example: the ICRC check code is calculated streamed for the RDMA packets transmitted in the preceding stage and the RDMA packets are sent in real time to the succeeding stage. The ICRC is also calculated and completed at the same time when the last byte of the RDMA data packet is transmitted, and the ICRC is appended at the tail of the RDMA data packet, so that a complete RDMA packet is constructed.
The issuing unit 115 is configured to issue the data packet to be transmitted.
Through the above embodiment, the complete data packet with the check code can be issued to the downstream.
The embodiment can be used for various scenes requiring calculation of the crc32, such as a scene which is designed to run in an FPGA and has a RocEv2 transmission requirement, or a scene which has a need for calculation of a RocEv2 check code.
It should be noted that, in this embodiment, an FPGA may be mounted and a modular design is adopted, so that, for an FPGA design that already supports a UDP (User Datagram Protocol ) protocol, RDMA transmission may be well supported through simple modification. For example: the above-mentioned process of generating calculation data can be constructed as a module (such as an infiniband protocol processing module), and the process of generating the ICRC check code can be constructed as a module (ICRC check code generating module), so that for the FPGA application which already supports the UDP protocol, only the infiniband protocol processing module needs to be inserted between the application and the UDP packaging processing module, and then the ICRC check code generating module is inserted immediately before the network packet output network, so that the conversion from the UDP to the RDMA protocol can be completed.
According to the technical scheme, the method and the device can copy the initial data packet in each period to obtain the data packet to be processed, and divide the data packet into two paths of processing, wherein one path calculates the target ICRC check code based on the data packet to be processed and the lookup table stored in the register in advance, and the other path adopts the D trigger to delay the initial data packet, further adds the target ICRC check code to the tail part of the initial data packet after delay processing to obtain the data packet to be transmitted, and issues the data packet to be transmitted, and further rapidly generates the check code of the data packet with any byte so as to assist the data packet to carry out safe and rapid transmission.
Fig. 3 is a schematic structural diagram of a computer device according to a preferred embodiment of the present invention for implementing a data transmission method based on check codes.
The computer device 1 may comprise a memory 12, a processor 13 and a bus, and may further comprise a computer program stored in the memory 12 and executable on the processor 13, for example a data transmission program based on a check code.
It will be appreciated by those skilled in the art that the schematic diagram is merely an example of the computer device 1 and does not constitute a limitation of the computer device 1, the computer device 1 may be a bus type structure, a star type structure, the computer device 1 may further comprise more or less other hardware or software than illustrated, or a different arrangement of components, for example, the computer device 1 may further comprise an input-output device, a network access device, etc.
It should be noted that the computer device 1 is only used as an example, and other electronic products that may be present in the present invention or may be present in the future are also included in the scope of the present invention by way of reference.
The memory 12 includes at least one type of readable storage medium including flash memory, a removable hard disk, a multimedia card, a card memory (e.g., SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, etc. The memory 12 may in some embodiments be an internal storage unit of the computer device 1, such as a removable hard disk of the computer device 1. The memory 12 may in other embodiments also be an external storage device of the computer device 1, such as a plug-in mobile hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the computer device 1. Further, the memory 12 may also include both an internal storage unit and an external storage device of the computer device 1. The memory 12 may be used not only for storing application software installed in the computer apparatus 1 and various types of data, such as codes of a data transmission program based on check codes, etc., but also for temporarily storing data that has been output or is to be output.
The processor 13 may be comprised of integrated circuits in some embodiments, for example, a single packaged integrated circuit, or may be comprised of multiple integrated circuits packaged with the same or different functions, including one or more central processing units (Central Processing unit, CPU), microprocessors, digital processing chips, graphics processors, a combination of various control chips, and the like. The processor 13 is a Control Unit (Control Unit) of the computer device 1, connects the respective components of the entire computer device 1 using various interfaces and lines, executes various functions of the computer device 1 and processes data by running or executing programs or modules stored in the memory 12 (for example, executing a data transmission program based on a check code, etc.), and calls data stored in the memory 12.
The processor 13 executes the operating system of the computer device 1 and various types of applications installed. The processor 13 executes the application program to implement the steps of the various embodiments of the check code based data transmission method described above, such as the steps shown in fig. 1.
Illustratively, the computer program may be partitioned into one or more modules/units that are stored in the memory 12 and executed by the processor 13 to complete the present invention. The one or more modules/units may be a series of computer readable instruction segments capable of performing the specified functions, which instruction segments describe the execution of the computer program in the computer device 1. For example, the computer program may be divided into an acquisition unit 110, a replication unit 111, a calculation unit 112, a delay unit 113, an addition unit 114, a issuing unit 115.
The integrated units implemented in the form of software functional modules described above may be stored in a computer readable storage medium. The software functional module is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a computer device, or a network device, etc.) or a processor (processor) to execute portions of the data transmission method based on the check code according to the embodiments of the present invention.
The modules/units integrated in the computer device 1 may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as separate products. Based on this understanding, the present invention may also be implemented by a computer program for instructing a relevant hardware device to implement all or part of the procedures of the above-mentioned embodiment method, where the computer program may be stored in a computer readable storage medium and the computer program may be executed by a processor to implement the steps of each of the above-mentioned method embodiments.
Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory, or the like.
Further, the computer-readable storage medium may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created from the use of blockchain nodes, and the like.
The blockchain is a novel application mode of computer technologies such as distributed data storage, point-to-point transmission, consensus mechanism, encryption algorithm and the like. The Blockchain (Blockchain), which is essentially a decentralised database, is a string of data blocks that are generated by cryptographic means in association, each data block containing a batch of information of network transactions for verifying the validity of the information (anti-counterfeiting) and generating the next block. The blockchain may include a blockchain underlying platform, a platform product services layer, an application services layer, and the like.
The bus may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one straight line is shown in fig. 3, but not only one bus or one type of bus. The bus is arranged to enable a connection communication between the memory 12 and at least one processor 13 or the like.
Although not shown, the computer device 1 may further comprise a power source (such as a battery) for powering the various components, preferably the power source may be logically connected to the at least one processor 13 via a power management means, whereby the functions of charge management, discharge management, and power consumption management are achieved by the power management means. The power supply may also include one or more of any of a direct current or alternating current power supply, recharging device, power failure detection circuit, power converter or inverter, power status indicator, etc. The computer device 1 may further include various sensors, bluetooth modules, wi-Fi modules, etc., which will not be described in detail herein.
Further, the computer device 1 may also comprise a network interface, optionally comprising a wired interface and/or a wireless interface (e.g. WI-FI interface, bluetooth interface, etc.), typically used for establishing a communication connection between the computer device 1 and other computer devices.
The computer device 1 may optionally further comprise a user interface, which may be a Display, an input unit, such as a Keyboard (Keyboard), or a standard wired interface, a wireless interface. Alternatively, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch, or the like. The display may also be referred to as a display screen or display unit, as appropriate, for displaying information processed in the computer device 1 and for displaying a visual user interface.
It should be understood that the embodiments described are for illustrative purposes only and are not limited to this configuration in the scope of the patent application.
Fig. 3 shows only a computer device 1 with components 12-13, it being understood by those skilled in the art that the structure shown in fig. 3 is not limiting of the computer device 1 and may include fewer or more components than shown, or may combine certain components, or a different arrangement of components.
In connection with fig. 1, the memory 12 in the computer device 1 stores a plurality of instructions to implement a data transmission method based on a check code, the processor 13 being executable to implement:
in each period, acquiring an initial data packet;
copying the initial data packet to obtain a data packet to be processed;
calculating a target ICRC check code based on the data packet to be processed and a lookup table pre-stored in a register;
adopting a D trigger to delay the initial data packet;
adding the target ICRC check code to the tail of the initial data packet after delay processing to obtain a data packet to be transmitted;
and transmitting the data packet to be transmitted.
Specifically, the specific implementation method of the above instructions by the processor 13 may refer to the description of the relevant steps in the corresponding embodiment of fig. 1, which is not repeated herein.
The data in this case were obtained legally.
In the several embodiments provided in the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be other manners of division when actually implemented.
The invention is operational with numerous general purpose or special purpose computer system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like. The invention may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units can be realized in a form of hardware or a form of hardware and a form of software functional modules.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference signs in the claims shall not be construed as limiting the claim concerned.
Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the singular does not exclude a plurality. The units or means stated in the invention may also be implemented by one unit or means, either by software or hardware. The terms first, second, etc. are used to denote a name, but not any particular order.
Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (9)
1. The data transmission method based on the check code is characterized by comprising the following steps of:
in each period, acquiring an initial data packet;
copying the initial data packet to obtain a data packet to be processed;
calculating a target ICRC check code based on the data packet to be processed and a lookup table pre-stored in a register;
adopting a D trigger to delay the initial data packet;
adding the target ICRC check code to the tail of the initial data packet after delay processing to obtain a data packet to be transmitted;
Issuing the data packet to be transmitted;
before the target ICRC check code is calculated based on the data packet to be processed and the lookup table stored in the register in advance, the method further includes:
configuring a corresponding lookup table for each byte number and a circuit corresponding to each lookup table;
storing the look-up table into the register;
wherein, the initial data packet is an RDMA data packet; the data packet to be processed is the same as the initial data packet.
2. The check code based data transmission method according to claim 1, wherein the calculating a target ICRC check code based on the data packet to be processed and a lookup table stored in a register in advance includes:
generating calculation data according to the data packet to be processed;
determining the byte number of the data packet to be processed;
selecting a target lookup table from the register based on the byte count using a request arbiter;
processing the calculated data by utilizing a circuit corresponding to the target lookup table to obtain first data;
obtaining output data corresponding to other lookup tables in the register, and obtaining an ICRC check code obtained by calculation of the previous period;
performing exclusive-or operation on the first data, the output data corresponding to the other lookup tables and the ICRC check code obtained by the previous period calculation to obtain second data;
And performing bit inversion operation on the second data to obtain the target ICRC check code.
3. The method for transmitting data based on check codes according to claim 2, wherein said generating calculation data from said data packet to be processed comprises:
deleting eth header in the RDMA data packet when the data packet to be processed is the RDMA data packet;
filling an LRH field of infiniband in the RDMA data packet into 0 xffffffffff_ffffffff;
replacing a type of service field and a time to live field of an IP header in the RDMA data packet with 0xff, and replacing a header checksum field of the IP header in the RDMA data packet with 0 xff;
and replacing the reserve field of the infiniband header with 0xff to obtain the calculation data.
4. The check code based data transmission method according to claim 2, wherein the calculating the target ICRC check code based on the pending data packet and a lookup table stored in a register in advance further comprises:
in an initial period, after the first data is obtained, obtaining output data corresponding to other lookup tables in the register, and obtaining a pre-configured initial ICRC check code;
And performing exclusive OR operation on the first data, the output data corresponding to the other lookup tables and the initial ICRC check code to obtain the second data.
5. The method for transmitting data based on check codes according to claim 1, wherein adding the target ICRC check code to the tail of the initial data packet after the delay processing, to obtain the data packet to be transmitted, comprises:
and when the preset mark in the initial data packet after the delay processing is detected, adding the target ICRC check code to the tail part of the initial data packet after the delay processing to obtain the data packet to be transmitted.
6. A data transmission device based on a check code, wherein the data transmission device based on the check code comprises:
an acquisition unit, configured to acquire an initial data packet in each period;
the copying unit is used for copying the initial data packet to obtain a data packet to be processed;
the calculating unit is used for calculating a target ICRC check code based on the data packet to be processed and a lookup table pre-stored in a register;
the delay unit is used for carrying out delay processing on the initial data packet by adopting a D trigger;
An adding unit, configured to add the target ICRC check code to the tail of the initial data packet after delay processing, to obtain a data packet to be transmitted;
the issuing unit is used for issuing the data packet to be transmitted;
before the target ICRC check code is calculated based on the data packet to be processed and a lookup table stored in a register in advance, the apparatus further includes:
configuring a corresponding lookup table for each byte number and a circuit corresponding to each lookup table;
storing the look-up table into the register;
wherein, the initial data packet is an RDMA data packet; the data packet to be processed is the same as the initial data packet.
7. The data transmission device based on check codes as claimed in claim 6, wherein said calculation unit is specifically configured to:
generating calculation data according to the data packet to be processed;
determining the byte number of the data packet to be processed;
selecting a target lookup table from the register based on the byte count using a request arbiter;
processing the calculated data by utilizing a circuit corresponding to the target lookup table to obtain first data;
obtaining output data corresponding to other lookup tables in the register, and obtaining an ICRC check code obtained by calculation of the previous period;
Performing exclusive-or operation on the first data, the output data corresponding to the other lookup tables and the ICRC check code obtained by the previous period calculation to obtain second data;
and performing bit inversion operation on the second data to obtain the target ICRC check code.
8. A computer device, the computer device comprising:
a memory storing at least one instruction; and
A processor executing instructions stored in the memory to implement the check code based data transmission method of any one of claims 1 to 5.
9. A computer-readable storage medium, characterized by: the computer readable storage medium has stored therein at least one instruction for execution by a processor in a computer device to implement the check code based data transmission method of any of claims 1 to 5.
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