CN104702293B - A kind of double mode BCH decoder circuits towards body area network - Google Patents
A kind of double mode BCH decoder circuits towards body area network Download PDFInfo
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Abstract
The invention belongs to error correction controlled coding technical field, specially a kind of double mode BCH decoder circuits towards body area network.The present invention is directed in body area network agreement IEEE 802.15.6 towards the arrowband physical layer standard of low-power consumption application, the high energy efficiency BCH code decoder for supporting double mode is devised, low-power consumption, the communication of energy-efficient can be carried out under different communication scenes, channel situation to realize.The present invention is realized to the double support based on the soft decoding algorithms of II types Chase and traditional decoding algorithm, and pass through the shared circuit area for reducing decoder of hardware between two kinds of algorithms by designing the decoder control unit using finite state machine as control core.
Description
Technical field
The invention belongs to error correction controlled coding technical field, and in particular to a kind of double mode BCH towards body area network is decoded
Device circuit.Application scenarios are wearable device, other related applications or any low power loss communication system for supporting BCH code.
Background technology
Error correction controlled coding is widely used in various types of communication system, in addition to it can increase the reliability of communication, is drawn
The power consumption of communication system, the energy efficiency of lifting system can also be reduced by entering Error Correction of Coding.By coding, transmitting terminal can be more
Small transmission power is issued to corresponding reliability index.When transmitting terminal because the power consumption for introducing error correction controlled coding and saving is big
When the power consumption of encoding and decoding, it is possible to obtain the reduction of system power dissipation and the lifting of energy efficiency.
Also there are the application to error correction controlled coding, the body area network standard IEEE of issue in 2012 in wearable device
802.15.6 it is for the standard between implanted or wearable device designed by group-net communication.The standard specifies physical layer and Jie
The agreement of matter access control sublayer, physical layer include three arrowband, ultra wide band and human body channel agreements.Narrow band protocol is used for low work(
Information transfer is consumed, has used BCH（63,51）Error correction controlled coding.
The coding gain of BCH code is related to decoding algorithm, and soft decoding can reach more preferable coding gain, i.e., more hairs
Power save is penetrated, but more decoding power consumptions can be introduced.Because with the deterioration of communication channel, transmission signal is in transmitting procedure
The raising for the decay undergone, introducing the transmission power saving as caused by the error correction controlled coding of stronger error correcting capability can further
Significantly, so being lifted in this case using soft decoding to system energy efficiency more favourable.Opposite, it is good in communication channel
In the case of, coding gain is small but simpler, encoding and decoding cost is smaller decoding algorithm more saves power consumption, and energy efficiency is more
It is high.
For body area network, different communication scenes lower channel models is different, therefore enables the system to the decoding of amount efficiency highest
Algorithm is also not quite similar.In order to realize low-power consumption, the communication of energy-efficient, it is necessary to which decoder can under different communication scene
Different decoding algorithms are supported, and can be switched between algorithm.
The content of the invention
It is soft to support it is an object of the invention to provide a kind of double mode BCH decoder circuit structures towards body area network
Decoding and hard decoder both of which, pattern switching can be carried out according to application scenarios and channel situation, realize low-power consumption, high-energy
Efficiency is wirelessly transferred.
Double mode BCH decoder circuit structures provided by the invention towards body area network, under soft-decision pattern, using II
The soft decoding algorithms of type Chase decode to input code word.Hard decoder module and hard decoder in the soft decoding algorithms of wherein Chase
The hard decoder module used in pattern is same module, so reduces hardware spending.Structure of the present invention includes：Hard decoder mould
Block, decoding control unit and clock generating module.Hard decoder module is responsible for entering the word to be decoded of input under hard decoder pattern
Row decoding, and cycle tests caused by each iteration is decoded under soft decoding schema；Include inside decoding control unit
Limit state machine, cycle tests generation module, candidate codewords caching, decoding output module.Decoding circuit mode of operation switching and
Decoding algorithm is controlled by the finite state machine in decoding control unit.Finite state machine receives external control signal,
And the status signal and data of hard decoder module output, the transfer that does well accordingly, control cycle tests generation module, candidate
Code word caching, hard decoder module and clock generating module.Clock generating module is controlled by state machine, and generation meets throughput requirement
The clock of frequency, i.e., meet the clock of corresponding modes throughput requirement frequency using frequency divider generation, be operated in hard decoder pattern
Under clock by soft decoding schema clock eight frequency dividing obtain.
In addition to clock and reset terminal, input signal includes the present invention：（1）Model selection：One, represent configuration decoding circuit
Arrangement works are under hard decoder pattern or under soft decoding schema；（2）Hard decision inputs：One, thus word to be decoded holds string
Row is inputted to decoding circuit structure；（3）Undefined position 1：Six, represent the position that confidence level is minimum in input code word；（4）No
Determine position 2：Six, represent the position that confidence level time is minimum in input code word；（5）Commencing signal：One, in input first
Become effective before word to be decoded, open decoding circuit.Output signal includes：（1）Decode accurate indication：One, represent input
Code word whether successfully decoded；（2）Output data effective marker：It is one, effective in Serial output decoded result；（3）Data
Output：One, Serial output decoded result；（4）Ready signals：One, represent that decoding circuit is not being decoded when invalid
Work, can start new decoding effort.
In the present invention, hard decoder module generates corresponding syndrome according to the code word of input first, and is sentenced according to syndrome
It whether there is mistake in disconnected input code word, set error flag signal accordingly；Following error location polynomial computing module root
According to syndrome generation error position multinomial；Money search module solves to error location polynomial, obtain errors present to
Amount, and judge whether the mistake for inputting code word can correct, whether setting successfully decoded mark is effective accordingly, solves obtained mistake
Position vector Serial output, by/the vectorial beginning and end exported of end mark sign errors present.
In the present invention, soft decoding schema is decoded using the soft decoding algorithms of II types Chase, is generated according to undefined position
Four cycle tests, it is separately input to be decoded in hard decoder module, by the code word generated after successfully decoded with not entering
The original series of row hard decision are compared, and the code word for taking Euclidean distance minimum exports as final coding result.Particularly,
When decoder circuit is operated under soft decoded state, the cycle tests generation module inside decoder control unit is in limited shape
Under the control of state machine, four cycle tests are generated according to the undefined position 1 of input and undefined position 2, it is inputted respectively
Decoded into hard decoder module, by the code word generated after successfully decoded deposit candidate codewords caching；Four cycle tests are complete
Code word during decoding output module caches candidate codewords after the completion of portion's decoding carries out Euclidean distance comparison with word to be decoded respectively,
The minimum code word of Euclidean distance is chosen to export as final coding result.
The present invention proposes that decoding circuit structure is completed to decode in decoder control unit under the control of finite state machine
Journey simultaneously realizes that double mode decodes.Finite state machine is according to the corresponding pattern of the value of the mode selection input of decoding circuit, control
Make other circuit modules and carry out hard decoder or soft decoding process.Qualified decoded result is stored in decoder control unit
Candidate codewords caching in, by decoder control unit output module control output.
Above-mentioned support hard decoder proposed by the present invention and soft decoding double mode BCH decoder circuit structures, available for body
BCH used by arrowband physical layer in the net standard IEEE 802.15.6 of domain（63,51）The decoding of code；Can be in different applications
More excellent decoding schema is switched under scene.Soft decoding algorithm is used under the larger channel of bad channel, decay, and in channel
Decoding algorithm is used in the case of good, so as to which the different scenes reached in body area network can lift the purpose of energy efficiency.
Brief description of the drawings
FigureIt is a kind of double mode BCH decoder circuit structures towards body area network.
Fig. 2 is the soft decoding algorithm schematic diagrames of II types Chase.
Fig. 3 is hard decoder modular structure.
Fig. 4 is decoder control unit structure.
Fig. 5 is decoder control unit state machine state transfer figure.
Embodiment
The purpose of the present invention, technical scheme and advantage are illustrated to be more clearly understood, below in conjunction with drawings and Examples,
The present invention is further explained.
Referring to Fig. 1, the invention provides a kind of BCH decoding circuit structures for supporting double mode, the decoding circuit removes clock
Outside reset terminal, in addition to five input signals and four output signals.Input signal includes：（1）Model selection：One, table
Show configuration decoding circuit arrangement works under hard decoder pattern or under soft decoding schema；（2）Hard decision inputs：One, treat
Thus decoded word holds serial input to decoding circuit structure；（3）Undefined position 1：Six, represent that confidence level is most in input code word
Low position；（4）Undefined position 2：Six, represent the position that confidence level time is minimum in input code word；（5）Commencing signal：One
Position, becomes effective before first word to be decoded is inputted, and opens decoding circuit.Output signal includes：（1）The correct mark of decoding
Will：One, represent input code word whether successfully decoded；（2）Output data effective marker：One, decode and tie in Serial output
It is effective during fruit；（3）Data output：One, Serial output decoded result；（4）Ready signals：One, decoding electricity is represented when invalid
Road is not carrying out decoding effort, can start new decoding effort.Decoding circuit structure includes：（1）Hard decoder module：It is used for
To the code word of input under hard decoder pattern, or cycle tests to be decoded in each iteration is carried out under soft decoding schema
BCH hard decoders operate；（2）Decoder control unit：Realized in the design with finite state machine, the control unit receives input
To the original code word and control signal in decoding circuit structure, clock generating module is controlled, is interacted with hard decoder module, and generate
The final output of decoding circuit structure；（3）Clock generating module：The pattern to be worked according to decoding circuit, is controlled by decoder
Unit control is divided accordingly to input clock, and generation meets the clock of corresponding modes throughput requirement.
In the present invention, hard decoder pattern uses the decoding algorithm based on BERLEKAMP-MASSEY algorithms, calculates treat first
The syndrome of decoded word, calculates error location polynomial using BERLEKAMP-MASSEY accordingly, and searching algorithm of then spending money is asked
Solve error location polynomial, judge whether character error to be decoded can solve, and obtain characterizing the mistake of character error position to be decoded to
Amount, decoding output is obtained with word XOR to be decoded.
In the present invention, soft decoding schema is decoded using the soft decoding algorithms of II types Chase, as shown in Fig. 2 decoding algorithm
200, step 201 receives the code word of input and two positions that confidence level is minimum, i.e. undefined position 1 in Fig. 1 and uncertain
Position 2.Step 202 accordingly generates cycle tests, and cycle tests is characterized in value of the other positions for input code word, and confidence level is most
Small position all permutation and combination that initial value or initial value negate respectively, often perform a step 202 and generate a new test sequence
Row, genesis sequence is gray encoding order.The cycle tests of generation is carried out hard decoder, decoding algorithm and hard solution by step 203
Decoding algorithm is identical used by pattern, and step 204 judges whether decoded result generates effective code word after the completion of decoding,
If so, then code word is deposited into candidate codewords caching, step 205 is carried out, otherwise directly carries out step 205.Step 205 judges
Whether there is cycle tests not decoded, if so, then return to step 202, otherwise into step 206, compare institute in caching
There is the Euclidean distance of candidate codewords and original code word, choose reckling and exported for decoding.
Hard decoder module is by syndrome computing module 31, error location polynomial computing module 32,33 groups of money search module
Into.As shown in Figure 3.Whether syndrome computing module 31 calculates the syndrome of word to be decoded, and judge wrong in code word；Mistake
Position polynomial computation module 32 calculates the error location polynomial of word to be decoded accordingly；Money search module 33 is more to errors present
Item formula is solved, and tries to achieve vicious position in word to be decoded, generation error vector, and judge that the mistake in word to be decoded is
It is no to solve.The commencing signal of syndrome computing module 31 provides with data input by control unit, commencing signal effectively it
After start working, word to be decoded is by data input pin serial input to syndrome computing module, data after 63 clock cycle
Input is completed, and calculates the syndrome of word to be decoded accordingly, and after calculating, the calculating completion signal of output is effective, calculates simultaneously
Obtained syndrome Serial output；Meanwhile syndrome computing module 31 is by judging whether syndrome is in 0 judgement word to be decoded
It is whether wrong, accordingly generate mistake and mark be present.Signal is completed in the calculating of syndrome computing module 31 and errors present is multinomial
The ready signals phase of formula computing module 32 and the commencing signal of generation input module 32, it is therefore an objective to prevent from calculating in module 32
Burr caused by the calculating completion signal accident of module 31 has an impact to calculating in journey.After the commencing signal of input is effective, mould
The ready signals of block 32 drag down, the syndrome that module 32 calculates according to syndrome computing module 31, using BERLEKAMP-
MASSEY algorithms calculate the error location polynomial of word to be decoded.After calculating, the ready signals of module 32 are drawn high, and are calculated
Completion signal is effective, and result of calculation is by error location polynomial Serial output.Signal and money search mould are completed in the calculating of module 32
The ready signals phase of block 33 and the commencing signal of formation module 33.After input commencing signal is effective, module 33 is counted to module 32
The error location polynomial for calculating gained is solved, and obtains error vector.The value of error vector is in the error-free position of code word to be decoded
0 is set to, error-free position is 1.The Serial output error vector of module 33, mistake output commencing signal is effective after the completion of calculating, under
One clock cycle starts a data of output error vector, when being output to last a data, mistake end of output mark
Will is effective.Module 33 judges whether the mistake in word to be decoded can solve always according to the number of error location polynomial, if to be decoded
Mistake in word can solve, then successfully decoded mark is effective, otherwise invalid.The effectively rear module of the calculating commencing signal of input
Ready signals are dragged down, and ready signals are drawn high after output.
Decoder control unit structure proposed by the invention as shown in figure 4, decoder control unit mainly by test sequence
Column-generation module 41, finite state machine 42, candidate codewords caching 43, and decoding output module 44.Wherein, cycle tests generation mould
Block 41 includes：3 multiplexers 410,411,412, codeword register group, counter, comparator, etc..Candidate codewords caching 43
The unidirectional shift register being mainly made up of several 1 bit registers, number are the digit of information bit in word to be decoded, are used
In caching candidate codewords.To be decoded word, undefined position 1 of the cycle tests generation module 41 according to input decoder control unit
Corresponding cycle tests is generated with undefined position 2, and hard decoder module is sent into iterative process is decoded, and in output last solution
To decoding output module output hard decision input during code result.63 bit codewords register groups are used for caching word to be decoded,
And when being operated under soft-decision pattern, the cycle tests that iteration is generated is decoded every time.Internal counter is by finite state
Machine controls, for calculating the data position of present clock period codeword register group output, and with undefined position 1 or not
Determine that position 2 is compared, when equal, otherwise it 1 is 0 that the data with codeword register group output institute XOR, which are,.In such a way,
The test vector that XOR gate can just exported meets：Other positions are the value of input code word, and the minimum position of confidence level is distinguished
All permutation and combination that initial value or initial value negate.Under soft solution pattern, XOR gate output is former word to be decoded during first time iteration；
Second of iteration multiplexer 411 selects undefined position 1 compared with counter, comparator selection 1 and codeword register when equal
Group output XOR, so as to obtain undefined position 1 except the data cycle tests opposite with former word to be decoded；During third time iteration,
Compared with multiplexer 411 selects the output of undefined position 2 and counter, so, XOR gate output be undefined position 1 and 2 with
The opposite cycle tests of word to be decoded；Last time iteration, select undefined position 1, obtain only undefined position 2 with it is to be decoded
The opposite cycle tests of word.As can be seen that the order of cycle tests generation is the order of Gray code.Finite state machine 42 is according to defeated
Enter the mode select signal of whole decoding circuit, and all outputs of hard decoder module carry out state transfer, output decoding is just
Really mark, ready signals, and the control signal to other modules of decoder control unit, its state transition diagram such as Fig. 5 institutes
Show.The state ID LE of code word input is waited, ready signals are effective under this state, and expression can do decoding effort.Start in input
Signal effectively enters effective code word input state DATA_COLLECTED afterwards, in this condition state machine control codeword register group
Caching inputs word or cycle tests to be decoded, generates and exports corresponding data to hard decoder module.If hard decoder output error
Mark is effective, then enters and wait errors present vector pattern ERR_WAIT.Under ERR_WATI patterns, when hard decoder module is completed
After error location polynomial generation, solution, errors present vector output commencing signal is effective, and state machine enters errors present vector
Input pattern ERR_COLLECTED.State machine is controlled the cycle tests of decoding and error bit under ERR_COLLECTED states
Put after vector carries out XOR and be stored in candidate codewords caching 43, hard decoder unit terminates letter after errors present vector output
Number effectively, state machine judges NextState according to mode of operation：If hard decoder pattern, then enter coding output mode DATA_
OUT；If soft decoding schema, then need to judge whether still there is the cycle tests not decoded, if so, then returning to DATA_COLLECTED
State, if nothing, into DATA_OUT states.The data that state machine is exported under DATA_OUT states in candidate codewords caching arrive
Judge and export in decoding output module, if candidate codewords are sky, control candidate codewords module output complete zero, input code word
Accurate indication invalid representation code word intangibility.In addition to IDLE state, when state machine be in other institute it is stateful when, ready signals
It is invalid, represent that decoding circuit is just busy.Decoding output module 44 mainly includes：Subtracter, power unit, adder, comparator,
3 multiplexers, 2 bit registers, and FIFO1, FIFO2, a control logic.It is relatively more all to decode output module 44
Euclidean distance between candidate codewords and word to be decoded, it is defeated as final decoding to choose the minimum candidate codewords of Euclidean distance
Go out.Word to be decoded and the Euclidean distance of candidate codewords are calculated by the way of serially adding up, the two subtracts each other per bit data, power
The difference square of all bits cumulative and be added again and before, finally give between this candidate codewords and word to be decoded it is European away from
From square, because chi square function in positive number field is increasing function, so not increasing extra extracting operation unit does not influence finally
As a result.For the candidate codewords that output Euclidean distance is minimum, module 44 stores intermediate result using Ping-pong FIFO.Input first
First candidate codewords is stored in FIFO1, and tries to achieve its Euclidean distance input control logic with word to be decoded.Second Candidate key
Word is stored in FIFO2, tries to achieve after Euclidean distance compared with the Euclidean distance of previous code word, if being less than, under control logic control
One code word is stored in FIFO1, is otherwise stored in FIFO2.Such iteration, until the judgement completion of all candidate codewords, if last
The Euclidean distance of all candidate codewords before the Euclidean distance of candidate codewords is less than, then control logic control export last time
Code selection word exports as decoding data, and otherwise, the data exported in another FIFO export as decoding data, output decoding
During data, effective marker is arranged to effective, is arranged to invalid after output.
Clock generating module in decoding circuit structure proposed by the present invention is entered according to mode select signal to input clock
Row frequency dividing, there is provided to hard decoder module and decoder control unit.The soft decoding algorithms of ChaseII used for the present invention, its
Decoding iteration number is 4 times, and need at most carry out 4 Euclidean distances when exporting decoded result compares.Therefore, to meet decoding circuit
Throughput requirement, when circuit is operated in soft decoding schema, clock frequency should be the octuple of hard decoder pattern.In the present invention,
The clock frequency of input decoding circuit meets the working frequency required for soft decoding schema, when decoding circuit is operated in hard decoder mould
When under formula, clock generating module divides input clock eight, inputs to hard decision module and decoder control unit as work
Clock.This method meets the clock demand under different mode, has reached the purpose of working in double modes.
Claims (5)
- A kind of 1. double mode BCH decoder circuits towards body area network, it is characterised in that：Support hard-decision decoding and soft-decision solution Code both of which, under soft-decision pattern, input code word is decoded using II types Chase soft decoding algorithms；Wherein Chase The hard decoder module used in hard decoder module and hard decoder pattern in soft decoding algorithm is same module；Its structure bag Include：Hard decoder module, decoding control unit and clock generating module；Wherein：The hard decoder module is responsible for decoding the word to be decoded of input under hard decoder pattern, and in soft decoding schema Under cycle tests caused by each iteration is decoded；Include finite state machine, cycle tests generation module, candidate codewords caching, decoding output inside the decoding control unit Module；The mode of operation switching of decoding circuit and decoding algorithm pass through the finite states machine control in decoding control unit；It is limited State machine receives external control signal, and the status signal and data of the output of hard decoder module, the transfer that does well accordingly, control Cycle tests generation module, candidate codewords caching, hard decoder module and clock generating module processed；The clock generating module meets corresponding modes throughput requirement frequency by finite states machine control using frequency divider generation Clock, the clock being operated under hard decoder pattern by soft decoding schema clock eight frequency dividing obtain.
- 2. decoder circuit according to claim 1, it is characterised in that input signal includes：（1）Model selection：One, represent configuration decoding circuit arrangement works under hard decoder pattern or under soft decoding schema；（2）Hard decision inputs：One, thus word to be decoded holds serial input to decoding circuit structure；（3）Undefined position 1：Six, represent the position that confidence level is minimum in input code word；（4）Undefined position 2：Six, represent the position that confidence level time is minimum in input code word；（5）Commencing signal：One, become effective before first word to be decoded is inputted, open decoding circuit；Output signal includes：（1）Decode accurate indication：One, represent input code word whether successfully decoded；（2）Output data effective marker：It is one, effective in Serial output decoded result；（3）Data output：One, Serial output decoded result；（4）Ready signals：One, represent that decoding circuit is not carrying out decoding effort when invalid, new decoding work can be started Make.
- 3. decoder circuit according to claim 1, it is characterised in that：Hard decoder module is given birth to according to the code word of input first Into corresponding syndrome, and judge to input in code word according to syndrome and whether there is mistake, set error flag signal accordingly；Connect Error location polynomial computing module get off according to syndrome generation error position multinomial；Money search module is more to errors present Item formula is solved, and obtains errors present vector, and judges whether the mistake for inputting code word can correct, and sets successfully decoded accordingly Whether mark effective, solves obtained errors present vector Serial output, by/end mark characterize errors present vector it is defeated The beginning and end gone out.
- 4. decoder circuit according to claim 2, it is characterised in that：Soft decoding schema uses the soft decodings of II types Chase Algorithm is decoded；When decoder circuit is operated under soft decoded state, the cycle tests life inside decoder control unit Into module under the control of finite state machine, four test sequences are generated according to the undefined position 1 of input and undefined position 2 Row, are separately input to be decoded in hard decoder module, by the code word generated after successfully decoded deposit candidate codewords caching； Code word during decoding output module caches candidate codewords after the completion of four cycle tests all decode is entered with word to be decoded respectively Row Euclidean distance compares, and chooses the minimum code word of Euclidean distance and is exported as final coding result.
- 5. according to the decoder circuit described in one of claim 1-3, it is characterised in that：The limited shape in decoder control unit Decoding process is completed under the control of state machine and realizes that double mode decodes；Finite state machine inputs according to the model selection of decoding circuit The corresponding pattern of the value at end, controls other circuit modules to carry out hard decoder or soft decoding process.
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