CN104702293A - Dual-mode BCH decoder circuit for body area network - Google Patents
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Abstract
The invention belongs to the technical field of error-correcting control coding, and in particular relates to a dual-mode BCH decoder circuit for a body area network. A high energy efficiency dual-mode BCH decoder is designed aiming at a narrow-band physical layer standard for low power consumption application of the body area network protocol IEEE802.15.6, so that the communication with low power consumption and high energy efficiency can be achieved in different communication scenes and channel situations. A decoder control unit taking a finite-state machine as the control core is designed for supporting the soft decoding algorithm and conventional hard decoding algorithm based on II type Chase, and the circuit area of the decoder is reduced by sharing the hardware between two types of algorithm.
Description
Technical field
The invention belongs to error correction controlled coding technical field, be specifically related to a kind of double mode BCH decoder circuit towards body area network.Application scenarios is wearable device, the low power loss communication system of other related application or any support BCH code.
Background technology
Error correction controlled coding is widely used in various types of communication system, except can increasing the reliability of communication, introduces the power consumption that error correction coding can also reduce communication system, the energy efficiency of elevator system.By coding, transmitting terminal can be issued to corresponding reliability index in less transmitting power.When the power consumption that transmitting terminal is saved owing to introducing error correction controlled coding is greater than the power consumption of encoding and decoding, the reduction of system power dissipation and the lifting of energy efficiency just can be obtained.
In wearable device, also have the application to error correction controlled coding, the body area network standard IEEE 802.15.6 issued for 2012 is for the standard between implanted or wearable device designed by group-net communication.The standard specifies the agreement of physical layer and MAC sublayer, physical layer comprises arrowband, ultra broadband and human body channel three agreements.Narrow band protocol is used for low-power consumption information transmission, employs BCH(63,51) error correction controlled coding.
The coding gain of BCH code is relevant to decoding algorithm, and soft decoding can reach better coding gain, i.e. more transmitting power saving, but can introduce power consumption of more decoding.Due to the deterioration along with communication channel, transmit the raising of the decay experienced in transmitting procedure, introducing the transmitting power saving brought by the error correction controlled coding of stronger error correcting capability can be further remarkable, promotes more favourable so apply soft decoding in this case to system energy efficiency.Contrary, when communication channel is good, coding gain is little but simpler, that encoding and decoding cost is less decoding algorithm saves power consumption more, and energy efficiency is higher.
For body area network, different communication scenes lower channel models is different, therefore makes the highest decoding algorithm of system energy efficiency also be not quite similar.In order to realize the communication of low-power consumption, energy-efficient under different communication scene, needing decoder can support different decoding algorithm, and can switch between algorithm.
Summary of the invention
The object of the present invention is to provide a kind of double mode BCH decoder circuit structure towards body area network, to support soft decoding and hard decoder two kinds of patterns, pattern switching can be carried out according to application scenarios and channel situation, realize low-power consumption, the wireless transmission of energy-efficient.
Double mode BCH decoder circuit structure towards body area network provided by the invention, under soft-decision pattern, adopts the soft decoding algorithm of II type Chase to decode to enter code word.The hard decoder module used in hard decoder module wherein in the soft decoding algorithm of Chase and hard decoder pattern is same module, which reduces hardware spending.Structure of the present invention comprises: hard decoder module, decoding control unit and clock generating module.Hard decoder module in charge is decoded to the word to be decoded of input under hard decoder pattern, and to the cycle tests decoding that each iteration produces under soft decoding schema; Decoding control unit inside comprises finite state machine, cycle tests generation module, candidate codewords buffer memory, decoding output module.The mode of operation of decoding circuit switches and decoding algorithm is controlled by the finite state machine in decoding control unit.Finite state machine receives external control signal, and the status signal that exports of hard decoder module and data, makes state transitions accordingly, controls cycle tests generation module, candidate codewords buffer memory, hard decoder module and clock generating module.Clock generating module is controlled by state machine, generates the clock meeting throughput requirement frequency, and namely utilize frequency divider to generate the clock meeting corresponding modes throughput requirement frequency, the clock be operated under hard decoder pattern is obtained by soft decoding schema clock eight frequency division.
The present invention is except clock and reset terminal, and input signal comprises: (1) model selection:, represents that configuration decoding circuit arrangement works is under hard decoder pattern or under soft decoding schema; (2) hard decision input:, word to be decoded holds serial input to decoding circuit structure thus; (3) undefined position 1: six, represents the position that in enter code word, confidence level is minimum; (4) undefined position 2: six, represents the secondary minimum position of confidence level in enter code word; (5) commencing signal:, became effective before input first word to be decoded, opened decoding circuit.Output signal comprises: (1) decoding accurate indication:, represents the code word whether successfully decoded of input; (2) data effective marker is exported: one, effective when Serial output decoded result; (3) data export: one, Serial output decoded result; (4) ready signal:, represents time invalid that decoding circuit is not carrying out decoding effort, can start new decoding effort.
In the present invention, first hard decoder module generates corresponding syndrome according to the code word of input, and judges whether there is mistake in enter code word according to syndrome, sets error flag signal accordingly; Following error location polynomial computing module is according to syndrome generation error position multinomial; Money search module solves error location polynomial, acquisition errors present vector, and judge whether the mistake of enter code word can correct, whether effectively set successfully decoded mark accordingly, solve the errors present vector Serial output obtained, characterize errors present vector exports and end by start/end mark.
In the present invention, soft decoding schema adopts the soft decoding algorithm of II type Chase to decode, four cycle testss are generated according to undefined position, it is input in hard decoder module respectively and decodes, the code word generated after successfully decoded and the original series not carrying out hard decision are compared, gets the minimum code word of Euclidean distance and export as final coding result.Particularly, when decoder circuit is operated under soft decoded state, the cycle tests generation module of decoder control unit inside is under the control of finite state machine, four cycle testss are generated according to the undefined position 1 inputted and undefined position 2, it is input in hard decoder module respectively and decodes, by the code word that generates after successfully decoded stored in candidate codewords buffer memory; Code word in candidate codewords buffer memory is carried out Euclidean distance with word to be decoded and is compared by four cycle testss rear decoding output module of all having decoded respectively, chooses the minimum code word of Euclidean distance and exports as final coding result.
The present invention completes decode procedure under proposing the control of decoding circuit structure finite state machine in decoder control unit and realizes double mode decoding.The pattern that finite state machine is corresponding according to the value of the mode selection input of decoding circuit, controls other circuit modules and carries out hard decoder or soft decode procedure.Qualified decoded result is stored in the candidate codewords buffer memory in decoder control unit, is controlled to export by the output module in decoder control unit.
The above-mentioned support hard decoder that the present invention proposes and soft decoding double mode BCH decoder circuit structure, can be used for the BCH(63 adopted arrowband physical layer in body area network standard IEEE 802.15.6,51) decoding of code; More excellent decoding schema can be switched under different application scenarioss.Under bad channel, larger channel of decaying, use soft decoding algorithm, and use decoding algorithm when channel is good, thus reach the object that all can promote energy efficiency in the different scenes of body area network.
Accompanying drawing explanation
Figure
it is a kind of double mode BCH decoder circuit structure towards body area network.
Fig. 2 is the soft decoding algorithm schematic diagram of II type Chase.
Fig. 3 is hard decoder modular structure.
Fig. 4 is decoder control unit structure.
Fig. 5 is decoder control unit state machine state transition diagram.
Embodiment
For clearly setting forth object of the present invention, technical scheme and advantage expressly, hereafter by reference to the accompanying drawings and embodiment, the present invention is explained further.
See Fig. 1, the invention provides and a kind ofly support double mode BCH decoding circuit structure, this decoding circuit, except clock and reset terminal, also comprises five input signals and four output signals.Input signal comprises: (1) model selection:, represents that configuration decoding circuit arrangement works is under hard decoder pattern or under soft decoding schema; (2) hard decision input:, word to be decoded holds serial input to decoding circuit structure thus; (3) undefined position 1: six, represents the position that in enter code word, confidence level is minimum; (4) undefined position 2: six, represents the secondary minimum position of confidence level in enter code word; (5) commencing signal:, became effective before input first word to be decoded, opened decoding circuit.Output signal comprises: (1) decoding accurate indication:, represents the code word whether successfully decoded of input; (2) data effective marker is exported: one, effective when Serial output decoded result; (3) data export: one, Serial output decoded result; (4) ready signal:, represents time invalid that decoding circuit is not carrying out decoding effort, can start new decoding effort.Decoding circuit structure comprises: (1) hard decoder module: be used for the code word of input under hard decoder pattern, or carry out the operation of BCH hard decoder to cycle tests to be decoded in each iteration under soft decoding schema; (2) decoder control unit: realize with finite state machine in the design, this control unit receives the original code word and control signal that are input in decoding circuit structure, control clock generating module, mutual with hard decoder module, and the final output of generating solution decoding circuit structure; (3) clock generating module: the pattern worked according to decoding circuit, is controlled to carry out corresponding frequency division to input clock by decoder control unit, generates the clock meeting the requirement of corresponding modes throughput.
In the present invention, hard decoder pattern adopts the decoding algorithm based on BERLEKAMP-MASSEY algorithm, first the syndrome of word to be decoded is calculated, BERLEKAMP-MASSEY is utilized to calculate error location polynomial accordingly, then searching algorithm of spending money solves error location polynomial, judge whether character error to be decoded can be separated, and obtain the error vector characterizing character error position to be decoded, obtaining decoding with word XOR to be decoded exports.
In the present invention, soft decoding schema adopts the soft decoding algorithm of II type Chase to decode, and as shown in Figure 2, decoding algorithm 200, step 201 receives the code word of input and minimum two positions of confidence level, the undefined position 1 namely in Fig. 1 and undefined position 2.Step 202 generates cycle tests accordingly, the value of the feature of cycle tests to be other position be enter code word, all permutation and combination of the minimum position of confidence level initial value or initial value negate respectively, often perform step 202 and generate a new cycle tests, genesis sequence is gray encoding order.The cycle tests of generation is carried out hard decoder by step 203, decoding algorithm is identical with the decoding algorithm that hard decoder pattern adopts, rear step 204 of having decoded judges whether decoded result generates effective code word, if have, then code word is deposited in candidate codewords buffer memory, carry out step 205, otherwise directly carry out step 205.Step 205 judges whether that cycle tests is not decoded in addition, if having, then returns step 202, otherwise enters step 206, compare the Euclidean distance of all candidate codewords and original code word in buffer memory, chooses reckling for decoding output.
Hard decoder module is by syndrome computing module 31, and error location polynomial computing module 32, money search module 33 forms.As shown in Figure 3.Whether syndrome computing module 31 calculates the syndrome of word to be decoded, and judge in code word wrong; Error location polynomial computing module 32 calculates the error location polynomial of word to be decoded accordingly; Money search module 33 pairs of error location polynomials solve, and try to achieve vicious position in word to be decoded, generation error vector, and judge whether the mistake in word to be decoded can separate.The commencing signal of syndrome computing module 31 and data input provide by control unit, start working after commencing signal effectively, word to be decoded passes through data input pin serial input to syndrome computing module, after 63 clock cycle, data have inputted, calculate the syndrome of word to be decoded accordingly, after calculating, the calculating settling signal of output is effective, the syndrome Serial output simultaneously calculated; Meanwhile, syndrome computing module 31 is by judging whether syndrome is whether wrong in 0 judgement word to be decoded, and generation error exists mark accordingly.The calculating settling signal of syndrome computing module 31 and the ready signal phase of error location polynomial computing module 32 with, generate the commencing signal of input module 32, object is that the burr preventing the calculating settling signal of module 31 in module 32 computational process from surprisingly producing has an impact to calculating.After the commencing signal inputted is effective, the ready signal of module 32 drags down, the syndrome that module 32 calculates according to syndrome computing module 31, adopts BERLEKAMP-MASSEY algorithm to calculate the error location polynomial of word to be decoded.After calculating, the ready signal of module 32 is drawn high, and calculate settling signal effective, result of calculation is by error location polynomial Serial output.The calculating settling signal of module 32 and the ready signal phase of money search module 33 with, form the commencing signal of module 33.After input commencing signal is effective, the error location polynomial that module 33 pairs of modules 32 calculate gained solves, and obtains error vector.The value of error vector is 0 in the position that code word to be decoded is error-free, and error-free position is 1.Module 33 Serial output error vector, having calculated rear mistake, to export commencing signal effective, and the next clock cycle starts the first bit data of output error vector, and when outputting to last bit data, mistake end of output mark is effective.Whether the mistake that module 33 also judges in word to be decoded according to the number of times of error location polynomial can separate, if the mistake in word to be decoded can be separated, then successfully decoded mark is effective, otherwise invalid.The ready signal of the effectively rear module of calculating commencing signal of input drags down, and after output, ready signal is drawn high.
Decoder control unit structure proposed by the invention as shown in Figure 4, decoder control unit primarily of cycle tests generation module 41, finite state machine 42, candidate codewords buffer memory 43, and decoding output module 44.Wherein, cycle tests generation module 41 comprises: 3 multiplexers 410,411,412, codeword register group, counter, comparator, etc.The unidirectional shift register that candidate codewords buffer memory 43 forms primarily of several 1 bit register, number is the figure place of information bit in word to be decoded, for buffer memory candidate codewords.Cycle tests generation module 41 generates corresponding cycle tests according to the word to be decoded of input decoder control unit, undefined position 1 and undefined position 2 and send into hard decoder module in decode iteration process, and exports hard decision input when exporting final decoded result to decoding output module.63 bit codewords Parasites Fauna are used for buffer memory word to be decoded, and when being operated under soft-decision pattern, the cycle tests that each decode iteration generates.Inner counter is by finite states machine control, for calculating the data position that present clock period codeword register group exports, and compare with undefined position 1 or undefined position 2, when equal, the data exporting institute's XOR with codeword register group are 1 otherwise are 0.In such a way, the test vector that just XOR gate can be made to export meets: other position is the value of enter code word, all permutation and combination of the position difference initial value that confidence level is minimum or initial value negate.Under soft solution pattern, during first time iteration, XOR gate exports as former word to be decoded; Second time iteration multiplexer 411 selects undefined position 1 to compare with counter, and time equal, comparator selects 1 to export XOR with codeword register group, thus obtains undefined position 1 and remove the data cycle tests contrary with former word to be decoded; During third time iteration, multiplexer 411 is selected undefined position 2 to export with counter to compare, and like this, XOR gate output is the cycle tests that undefined position 1 and 2 is all contrary with word to be decoded; Last iteration, selects undefined position 1, obtains the cycle tests only having undefined position 2 contrary with word to be decoded.Can find out, the order that cycle tests generates is the order of Gray code.Finite state machine 42 is according to the mode select signal of the whole decoding circuit of input, and state transitions is carried out in all outputs of hard decoder module, export decoding accurate indication, ready signal, and the control signal to other modules of decoder control unit, its state transition diagram is as shown in Figure 5.Wait for the state ID LE of code word input, under this state, ready signal is effective, and expression can do decoding effort.After input commencing signal is effective, enter effective code word input state DATA_COLLECTED, state machine control code word register group buffer memory inputs word to be decoded or cycle tests in this condition, generates and also exports corresponding data to hard decoder module.If hard decoder output error mark is effective, then enters and wait for errors present vector pattern ERR_WAIT.Under ERR_WATI pattern, after generating when hard decoder module completes error location polynomial, solving, it is effective that errors present vector exports commencing signal, and state machine enters errors present vector input pattern ERR_COLLECTED.Under ERR_COLLECTED state, state machine controls the cycle tests of decoding and errors present vector to carry out after XOR stored in candidate codewords buffer memory 43, after errors present vector exports, hard decoder unit end signal is effective, state machine judges NextState according to mode of operation: if hard decoder pattern, then enter coding output mode DATA_OUT; If soft decoding schema, then need to judge whether to still have the cycle tests of not decoding, if having, then return DATA_COLLECTED state, if nothing, then enter DATA_OUT state.The data that state machine exports in candidate codewords buffer memory under DATA_OUT state judge and export in decoding output module, if candidate codewords is empty, then controls candidate codewords module and export complete zero, the accurate indication invalid representation code word intangibility of enter code word.Except IDLE state, when state machine is in other all states, ready signal is all invalid, represents that decoding circuit is just busy.Decoding output module 44 mainly comprises: subtracter, power unit, adder, comparator, 3 multiplexers, 2 bit register, and FIFO1, FIFO2, a control logic.Euclidean distance between the decoding more all candidate codewords of output module 44 and word to be decoded, chooses the minimum candidate codewords of Euclidean distance and exports as final decoding.The mode adopting serial to add up calculates the Euclidean distance of word to be decoded and candidate codewords, the two every Bit data subtracts each other, power is added with the cumulative sum of the difference square of all bits before again, finally obtain the Euclidean distance between this candidate codewords and word to be decoded square, because chi square function is increasing function at positive number field, so do not increase extra extracting operation unit not affect final result.For exporting the minimum candidate codewords of Euclidean distance, module 44 uses Ping-pong FIFO to store intermediate object program.First first candidate codewords inputted stored in FIFO1, and tries to achieve the Euclidean distance input control logic of itself and word to be decoded.Second candidate codewords, stored in FIFO2, compares with the Euclidean distance of previous code word after trying to achieve Euclidean distance, if be less than, then control logic controls next code word stored in FIFO1, otherwise stored in FIFO2.Iteration like this, until all candidate codewords have judged, the Euclidean distance of all candidate codewords before if the Euclidean distance of last candidate codewords is less than, then last candidate codewords of control logic control output exports as decoded data, otherwise the data exported in another one FIFO export as decoded data, when exporting decoded data, effective marker is set to effectively, and it is invalid to be set to after output.
Clock generating module in the decoding circuit structure that the present invention proposes, according to mode select signal, is carried out frequency division to input clock, is supplied to hard decoder module and decoder control unit.For the soft decoding algorithm of ChaseII that the present invention adopts, its decoding iteration number of times is 4 times, need carry out at most 4 Euclidean distances and compare when exporting decoded result.Therefore, for meeting the throughput requirement of decoding circuit, circuit working is when soft decoding schema, and clock frequency should be the octuple of hard decoder pattern.In the present invention, the clock frequency of input decoding circuit meets the operating frequency required for soft decoding schema, when decoding circuit is operated under hard decoder pattern, clock generating module, by input clock eight frequency division, inputs to hard decision module and decoder control unit as work clock.This method meets the clock demand under different mode, reaches the object of working in double modes.
Claims (5)
1. towards a double mode BCH decoder circuit for body area network, it is characterized in that: support hard-decision decoding and soft-decision decoding two kinds of patterns, under soft-decision pattern, adopt the soft decoding algorithm of II type Chase to decode to enter code word; The hard decoder module used in hard decoder module wherein in the soft decoding algorithm of Chase and hard decoder pattern is same module; Its structure comprises: hard decoder module, decoding control unit and clock generating module; Wherein:
Described hard decoder module in charge is decoded to the word to be decoded of input under hard decoder pattern, and to the cycle tests decoding that each iteration produces under soft decoding schema;
Described decoding control unit inside comprises finite state machine, cycle tests generation module, candidate codewords buffer memory, decoding output module; The mode of operation switching of decoding circuit and decoding algorithm are by the finite states machine control in decoding control unit; Finite state machine receives external control signal, and the status signal that exports of hard decoder module and data, makes state transitions accordingly, controls cycle tests generation module, candidate codewords buffer memory, hard decoder module and clock generating module;
Described clock generating module is by finite states machine control, and utilize frequency divider to generate the clock meeting corresponding modes throughput requirement frequency, the clock be operated under hard decoder pattern is obtained by soft decoding schema clock eight frequency division.
2. decoder circuit according to claim 1, is characterized in that, input signal comprises:
(1) model selection:, represents that configuration decoding circuit arrangement works is under hard decoder pattern or under soft decoding schema;
(2) hard decision input:, word to be decoded holds serial input to decoding circuit structure thus;
(3) undefined position 1: six, represents the position that in enter code word, confidence level is minimum;
(4) undefined position 2: six, represents the secondary minimum position of confidence level in enter code word;
(5) commencing signal:, became effective before input first word to be decoded, opened decoding circuit;
Output signal comprises:
(1) to decode accurate indication: one, represent the code word whether successfully decoded of input;
(2) data effective marker is exported: one, effective when Serial output decoded result;
(3) data export: one, Serial output decoded result;
(4) ready signal:, represents time invalid that decoding circuit is not carrying out decoding effort, can start new decoding effort.
3. decoder circuit according to claim 1, is characterized in that: first hard decoder module generates corresponding syndrome according to the code word of input, and judges whether there is mistake in enter code word according to syndrome, sets error flag signal accordingly; Following error location polynomial computing module is according to syndrome generation error position multinomial; Money search module solves error location polynomial, acquisition errors present vector, and judge whether the mistake of enter code word can correct, whether effectively set successfully decoded mark accordingly, solve the errors present vector Serial output obtained, characterize errors present vector exports and end by start/end mark.
4. according to the decoder circuit one of claim 1-3 Suo Shu, it is characterized in that: soft decoding schema adopts the soft decoding algorithm of II type Chase to decode; When decoder circuit is operated under soft decoded state, the cycle tests generation module of decoder control unit inside is under the control of finite state machine, four cycle testss are generated according to the undefined position 1 inputted and undefined position 2, it is input in hard decoder module respectively and decodes, by the code word that generates after successfully decoded stored in candidate codewords buffer memory; Code word in candidate codewords buffer memory is carried out Euclidean distance with word to be decoded and is compared by four cycle testss rear decoding output module of all having decoded respectively, chooses the minimum code word of Euclidean distance and exports as final coding result.
5., according to the decoding circuit one of claim 1-3 Suo Shu, it is characterized in that: in decoder control unit finite state machine control under complete decode procedure and realize double mode decoding; The pattern that finite state machine is corresponding according to the value of the mode selection input of decoding circuit, controls other circuit modules and carries out hard decoder or soft decode procedure.
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