CN104716965A - BCH soft decoding algorithm and implementation circuit thereof - Google Patents
BCH soft decoding algorithm and implementation circuit thereof Download PDFInfo
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Abstract
The invention belongs to the technical field of error correction control coding and particularly relates to a BCH soft decoding algorithm and an implementation circuit thereof. Based on a traditional II type Chase BCH soft decoding algorithm, a novel iterative algorithm is proposed, iteration can be ended in advance, so that the iteration times are reduced, and thus the decoding power consumption is reduced. In addition, the invention provides a novel output code determining mode, a Euclidean distance comparing unit which consumes large energy and long time in a traditional Chase soft decoder is omitted, the decoding power consumption is further reduced, and the overall efficiency is improved. The invention further provides a circuit structure for the soft decoding algorithm, wherein a finite-state machine and a hard decoding module are in interaction, and a test sequence generating module and a candidate codeword cache are controlled to complete the whole decoding process.
Description
Technical field
The invention belongs to error correction controlled coding technical field, be specially the soft decoding algorithm of a kind of BCH and realize the circuit structure of this decoding algorithm.
Background technology
Error correction controlled coding is widely used in various types of communication system, except can increasing the reliability of communication, introduces the power consumption that error correction coding can also reduce communication system, the energy efficiency of elevator system.By coding, transmitting terminal can be issued to corresponding reliability index in less transmitting power.When the power consumption that transmitting terminal is saved owing to introducing error correction controlled coding is greater than the power consumption of encoding and decoding, the reduction of system power dissipation and the lifting of energy efficiency just can be obtained.
The coding gain of BCH code is relevant to decoding algorithm, and soft decoding can reach better coding gain, but compared to hard decoder, the cost of soft decoding is higher.The cost of soft decoding is mainly reflected in: 1. more decoding iteration number: the most frequently used II type Chase BCH decoding algorithm, needs to carry out a hard decoder process to all cycle testss, and iterations equals the number of errors that the most multipotency of BCH code is corrected.2. extra hardware spending, soft decoding is except hard decoder module, also to increase extra module, calculate and compare the Euclidean distance between candidate codewords and original sequence of not carrying out hard decision, taking advantage of that this wherein relates to adds, comparison operation, all to take sizable area, and cause a large amount of power consumptions.Therefore, under the prerequisite obtaining coding gain more better than hard decoder, reducing the cost of soft decoding, is problem demanding prompt solution.
Summary of the invention
The present invention is directed to the problem that existing BCH soft decoding cost is high, traditional II type Chase decoding algorithm is improved, devise the soft decoding algorithm of a kind of new BCH, and devise the circuit structure realizing this algorithm.This algorithm, on the basis of traditional C hase algorithm, decreases iterations, and the calculating avoiding Euclidean distance with compare, improve decoding usefulness.
The soft decoding algorithm of BCH that the present invention proposes, concrete steps are:
(1) the maximum correctable error number t that minimal error number is pattern is set, receives enter code word and minimum t the position of confidence level;
(2) generate cycle tests according to enter code word and minimum t the position of confidence level, that is, former enter code word is on minimum t the position of its confidence level, and its value is initial value or this initial value negate of code word itself; The set of cycle tests is all permutation and combination situations of this sequence;
(3) BCH hard decoder is carried out to the cycle tests generated;
(4) if error-free in the hard decoder result display sequence of cycle tests, soft solution iteration is stopped, by this cycle tests stored in candidate codewords buffer memory; If number of errors exceedes error correction scope in the hard decoder result display sequence of cycle tests, then abandon this sequence; If errors correctable in the hard decoder result display sequence of cycle tests, then to compare in this sequence number of errors and decodedly correct minimal error number in cycle tests; If number of errors is less than and decodedly corrects minimal error number in cycle tests in sequence, then by this decoded cycle tests stored in candidate codewords buffer memory, and upgrade the error number of minimal error number cycle tests for this reason; If number of errors is greater than and decodedly corrects minimal error number in cycle tests in sequence, abandon this sequence;
After completing above step, if still have cycle tests not decode, then return step (2) and continue to carry out hard decoder and step afterwards to remaining cycle tests.If all cycle testss have been decoded all, then stop soft solution iteration.
After stopping iteration, to judge in iterative process whether solution appears effective code word to hard decoder module, if not, control candidate codewords buffer memory and export complete zero, it is invalid that correct signal of decoding is set to; Otherwise the content exported in candidate codewords buffer memory, decoding correct signal is set to effectively.
The decoding circuit structure realizing this algorithm comprises hard decoder module, finite state machine, cycle tests generation module and candidate codewords buffer memory four modules.Whole decoding circuit completes decoding algorithm under the control of finite state machine.Finite state machine, according to the control inputs of decoding circuit, controls the cycle tests that cycle tests generation module generates the decoding of each decode iteration.In addition, finite state machine and hard decoder module carry out that control is mutual, data interaction, control hardware decoding circuit and complete decoding algorithm.In decode procedure finite states machine control by qualified candidate codewords stored in candidate codewords buffer memory.The test vector of hard decoder module to grey iterative generation each in decode procedure carries out hard decoder, and to finite state machine output error mark, error number signal, successfully decoded mark, errors present vector, start/end mark.In these signals, whether error flag characterization test sequence is wrong, error number contained in the code word of error number signal indication input hard decoder module, the position that whether the successfully decoded mark mistake characterized in enter code word can correct, errors present vector characterizes mistake, in wrong position be 1 all the other be 0, start/end mark represents start time and the finish time of output error position vector.
In the present invention, start decode procedure when external world's input commencing signal is effective, when hard decoder module decodes error-free cycle tests, namely error flag is invalid, then finite states machine control stops decode iteration, and buffer memory also exports this cycle tests; When hard decoder module decodes wrong but repairable cycle tests, finite state machine judges whether it is less than error number, judges whether its decoded result of reception accordingly and stored in candidate codewords buffer memory, and whether upgrades minimal error number; If hard decoder module decodes not repairable cycle tests, finite state machine directly abandons its decoded result; Hard decoder process terminates each time, and whether finite state machine has the cycle tests of not decoding to determine whether to need to stop decode iteration according to current; Whether solution appears effective code word judges whether successfully decoding according to hard decoder module in iterative process to stop after iteration finite state machine, and controls candidate codewords buffer memory, if successfully decoded, exports data in buffer memory, otherwise exports complete zero.
The present invention, on the basis of traditional soft decoding algorithm of II type Chase BCH, proposes a kind of new iterative algorithm, can shift to an earlier date finishing iteration thus reduce iterations, and then reduces decoding power consumption.In addition the invention allows for a kind of new output encoder judgement mode, Euclidean distance comparing unit very large when eliminating consumption energy consumption in the soft decoder of traditional C hase, further reduces decoding power consumption, promotes overall efficiency.
Accompanying drawing explanation
Fig. 1 is BCH decoding algorithm flow chart.
Fig. 2 is the decoding circuit structured flowchart realizing this decoding algorithm.
Fig. 3 is the internal structure block diagram of hard decoder module.
Fig. 4 is the internal structure block diagram of cycle tests generation module.
Fig. 5 is the internal structure block diagram of candidate codewords buffer memory.
Fig. 6 is finite state machine status transition diagram.
Embodiment
For clearly setting forth object of the present invention, technical scheme and advantage expressly, hereafter by reference to the accompanying drawings and embodiment, the present invention is explained further.
Fig. 1 is the flow chart of BCH decoding algorithm proposed by the invention, and after starting, step 11 arranges the maximum correctable error number t that minimal error number is pattern, receives enter code word and minimum t the position of confidence level.Following step 12 generates cycle tests according to enter code word and minimum t the position of confidence level, that is, former enter code word is on minimum t the position of its confidence level, and its value is initial value or this initial value negate of code word itself.Then carry out step 13 cycle tests of generation feeding BCH hard decoder module is decoded.Whether wrong in the information determination cycle tests that after decoding, step 14 first obtains according to decoding, if error-free in the hard decoder result display sequence of cycle tests, stop soft solution iteration, carry out step 15 then this cycle tests is entered step 21 stored in candidate codewords buffer memory to export code word in buffer memory, coding correct signal is set to effectively; If wrong in sequence, then carry out step 16, if number of errors exceedes error correction scope in the hard decoder result display sequence of cycle tests, then abandon this sequence; If errors correctable in the hard decoder result display sequence of cycle tests, then carry out step 17 and to compare in this sequence number of errors and decodedly correct minimal error number in cycle tests; If be less than, then carry out step 18 by this decoded cycle tests stored in candidate codewords buffer memory, and upgrade the error number of minimal error number cycle tests for this reason, then carry out step 19; If be greater than, abandon this sequence and directly enter step 19.Step 19 judge whether to still have do not carry out decoding candidate codewords, if having, return step 12; If no, stop iteration entering step 20, judge that candidate codewords is cached with candidate codewords, if having, then carry out step 21; If nothing, then export complete zero, it is invalid to be set to by decoding correct signal.
Fig. 2 is the circuit structure realizing BCH decoding algorithm proposed by the invention, and circuit has 2+t input: comprise commencing signal, code word input, represent the signal also having position that t confidence level is minimum; Four outputs: comprise and characterize accurate indication of whether successfully decoding of decoding, be effectively export data effective marker at output decoded data, data export, and characterize the ready signal that decoding circuit can be started working.
Circuit structure comprises hard decoder module, finite state machine, cycle tests generation module and candidate codewords buffer memory four modules.Whole decoding circuit completes decoding algorithm under the control of finite state machine.Finite state machine, according to the control inputs of decoding circuit, controls the cycle tests that cycle tests generation module generates the decoding of each decode iteration.In addition, finite state machine and hard decoder module carry out that control is mutual, data interaction, control hardware decoding circuit and complete decoding algorithm.In decode procedure finite states machine control by qualified candidate codewords stored in candidate codewords buffer memory.The test vector of hard decoder module to grey iterative generation each in decode procedure carries out hard decoder, and to finite state machine output error mark, error number signal, successfully decoded mark, errors present vector, start/end mark.In these signals, whether error flag characterization test sequence is wrong, error number contained in the code word of error number signal indication input hard decoder module, the position that whether the successfully decoded mark mistake characterized in enter code word can correct, errors present vector characterizes mistake, in wrong position be 1 all the other be 0, start/end mark represents start time and the finish time of output error position vector.
As shown in Figure 3, hard decoder module is by syndrome computing module 31, and error location polynomial computing module 32,3 modules such as money search module 33 grade form for hard decoder modular structure in decoding circuit structure proposed by the invention.Hard decoder is mainly divided into three steps: syndrome generates, error location polynomial generates, error location polynomial solves.The step wherein calculating the syndrome of word to be decoded is completed by syndrome computing module, and according to syndrome be whether 0 judge in code word whether wrong.Following syndrome result is input in error location polynomial computing module, and module calculates the error location polynomial of word to be decoded accordingly; Money search module is responsible for solving error location polynomial, and result is vicious position in word to be decoded, is characterized by error vector, and in solution procedure, can judge whether the mistake in word to be decoded can separate according to the relation of polynomial number of times and t.Syndrome computing module 31 is started working after the commencing signal inputted by state machine effectively, and serial received decoding input, calculates its syndrome; After calculating, the calculating settling signal of module 31 is effective, simultaneously by syndrome Serial output; Meanwhile, module 31 judges whether syndrome is 0, and if so, then mistake existence mark is invalid, represent in word to be decoded do not have mistake, otherwise signal is effective.The commencing signal of error location polynomial computing module 32 is by the ready signal of module 32 and the calculating settling signal phase of module 31 and generation.The commencing signal of input module 32 effectively after, its ready signal is low, and module 32 pairs of syndromes carry out iterative computation, adopts BERLEKAMP-MASSEY algorithm mistake in computation position multinomial.After calculating, the ready signal of module 32 is drawn high, and calculate settling signal effective, result of calculation is by error location polynomial Serial output.The commencing signal of money search module 33 by the calculating settling signal of module 12 and the ready signal phase of money search module 13 with obtain.Input commencing signal effectively after, module 33 starts to solve the error location polynomial that module 32 calculates, and the root after solving is the error vector characterizing errors present.The value of error vector is 0 in the position that code word to be decoded is error-free, and error-free position is 1, by module 33 Serial output.After solution procedure completes, to export commencing signal effective for the mistake of module 33, and the next clock cycle starts the first bit data of output error vector, and when outputting to last bit data, mistake end of output mark is effective.In addition, the module 33 also polynomial number of times in misjudgment position judges whether the mistake in word to be decoded can separate, if number of times is less than t, the mistake in word to be decoded can be separated, then successfully decoded mark is effective, otherwise invalid.The ready signal of the effectively rear module of calculating commencing signal of input drags down, and after error location polynomial all exports, ready signal is drawn high.
Cycle tests generation module structure as shown in Figure 4, comprises 3 multiplexers 41,42,43, codeword register group, counter, comparator, etc.; Codeword register group is used for buffer memory word to be decoded, and it is made up of some and 1 bit register, and the code word size that register number is separated by decoder determines.Inner counter is by finite states machine control, calculate the position of data in word to be decoded that present clock period codeword register group exports, it is compared with some in undefined position 1 to undefined position t, is selected by finite states machine control multiplexer 42 by the data compared.When equal, by the data-conversion that codeword register group exports, select its output valve by controlling multiplexer 43, the XOR value namely exporting data with codeword register group is 1 to realize.In the process of soft decoding iteration each time, while this test vector is exported to hard decoder module, control multiplexer 41 by state machine and be stored in codeword register group; When next iteration, state machine controls multiplexer 42 and selects different positional values, and the code word of such opposite position will by negate.Can find out, only have a bit word different between adjacent test sequences, therefore can adjust state machine, the order that cycle tests is generated is the order of Gray code.
Candidate codewords buffer structure of the present invention as shown in Figure 5.Comprise multiplexer, codeword register group, the unidirectional shift register that codeword register group is made up of several 1 bit register, number is the figure place of information bit in word to be decoded, for buffer memory candidate codewords.As when effectively exporting, just control the clock end of candidate codewords buffer memory, and to serial input decoded result in first bit register, decoded result can be displaced in the register of buffer memory successively when state machine judges that the decoding of hard decoder exports.Finally at the end of decoding, state machine is according to whether producing effective code word in decode iteration process, and control multiplexer is using the candidate codewords in buffer memory or export complete zero and export as last solution code data.
Fig. 6 is the state transition diagram of finite state machine in the decoding circuit that proposes of the present invention.After resetting, state machine enters and waits for code word input state IDLE, and arranging minimal error number is 0; Effective code word input state DATA_COLLECTED is entered after input commencing signal is effective, the Parasites Fauna of finite states machine control cycle tests generation module inside in this condition, buffer memory enter code word or cycle tests, generate and export corresponding decoded data to hard decoder module.Terminate when syndrome calculates, and when the error flag of hard decoder module output is effective, state machine enters waits for errors present vector pattern ERR_WAIT; If error flag is invalid, then enters otherwise directly enter decoding output mode DATA_OUT.Under ERR_WATI pattern, when hard decoder module complete error location polynomial generate, solve after, errors present vector export commencing signal effective.Now need to judge whether the number of errors that hard decoder exports is less than minimal error number, if so, finite state machine enters errors present vector input pattern ERR_COLLECTED; If not or the successfully decoded mark of hard decoder module invalid, and still have cycle tests not to be generated and decode, then returning DATA_COLLECTED pattern; If it is complete that all cycle testss have generated decoding all, then enter coding output mode DATA_OUT.The cycle tests that this decode iteration is decoded by finite state machine under ERR_COLLECTED state and the errors present vector that hard decoder module exports carry out after XOR stored in candidate codewords buffer memory, after errors present vector exports, hard decoder unit end signal is effective, finite state machine judges NextState according to mode of operation: if hard decoder pattern, then enter coding output mode DATA_OUT; If soft decoding schema, then need to judge whether to still have the cycle tests of not decoding, if having, then return DATA_COLLECTED state, if nothing, then enter DATA_OUT state.Finite state machine exports the data in candidate codewords buffer memory under DATA_OUT state, to judge in iterative process whether solution appears effective code word to hard decoder module, if not, control candidate codewords buffer memory and export complete zero, it is invalid that decoding correct signal is set to; Otherwise the content exported in candidate codewords buffer memory, decoding correct signal is set to effectively.After output completes, state machine returns IDLE state.Except IDLE state, when state machine is in other all states, ready signal is all invalid, represents that decoding circuit is just busy.
Claims (8)
1. the soft decoding algorithm of BCH, is characterized in that concrete steps are:
(1) the maximum correctable error number t that minimal error number is pattern is set, receives enter code word and minimum t the position of confidence level; Arranging minimal error number before decoding starts is 0;
(2) cycle tests is generated according to enter code word and minimum t the position of confidence level;
(3) BCH hard decoder is carried out to the cycle tests generated;
(4) if error-free in the hard decoder result display sequence of cycle tests, soft solution iteration is stopped, by this cycle tests stored in candidate codewords buffer memory; If number of errors exceedes error correction scope in the hard decoder result display sequence of cycle tests, then abandon this sequence; If errors correctable in the hard decoder result display sequence of cycle tests, then to compare in this sequence number of errors and decodedly correct minimal error number in cycle tests; If number of errors is less than and decodedly corrects minimal error number in cycle tests in sequence, then by this decoded cycle tests stored in candidate codewords buffer memory, and upgrade the error number of minimal error number cycle tests for this reason; If number of errors is greater than and decodedly corrects minimal error number in cycle tests in sequence, abandon this sequence;
After completing above step, if still have cycle tests not decode, then return step (2), continue to carry out hard decoder and step afterwards to remaining cycle tests; If all cycle testss have been decoded all, then stop soft solution iteration;
After the soft solution iteration of stopping, judging in iterative process whether solution appears effective code word to hard decoder module, if not, control candidate codewords buffer memory and export complete zero, it is invalid that correct signal of decoding is set to; Otherwise the content exported in candidate codewords buffer memory, decoding correct signal is set to effectively.
2. the soft decoding algorithm of BCH according to claim 1, is characterized in that: enter code word is binary code.
3. the soft decoding algorithm of BCH according to claim 1, is characterized in that: cycle tests is former enter code word on minimum t the position of its confidence level, and its value is initial value or this initial value negate of code word itself; The set of cycle tests is all permutation and combination situations of this sequence.
4. the realizing circuit of the soft decoding algorithm of BCH as claimed in claim 1, is characterized in that comprising hard decoder module, finite state machine, cycle tests generation module and candidate codewords buffer memory four modules; Whole decoding circuit completes decoding algorithm under the control of finite state machine; Wherein:
Described finite state machine, according to the control inputs of decoding circuit, controls the cycle tests that cycle tests generation module generates the decoding of each decode iteration; In addition, finite state machine and hard decoder module carry out that control is mutual, data interaction, control hardware decoding circuit and complete decoding algorithm; In decode procedure finite states machine control by qualified candidate codewords stored in candidate codewords buffer memory;
The test vector of described hard decoder module to grey iterative generation each in decode procedure carries out hard decoder, and to finite state machine output error mark, error number signal, successfully decoded mark, errors present vector, start/end mark; Wherein, whether error flag characterization test sequence is wrong, error number contained in the code word of error number signal indication input hard decoder module, the position that whether the successfully decoded mark mistake characterized in enter code word can correct, errors present vector characterizes mistake, in wrong position be 1 all the other be 0, start/end mark represents start time and the finish time of output error position vector.
5. the realizing circuit of the soft decoding algorithm of BCH according to claim 4, it is characterized in that starting decode procedure when external world's input commencing signal is effective, when hard decoder module decodes error-free cycle tests, namely error flag is invalid, then finite states machine control stops decode iteration, and buffer memory also exports this cycle tests; When hard decoder module decodes wrong but repairable cycle tests, finite state machine judges whether it is less than error number, judges whether its decoded result of reception accordingly and stored in candidate codewords buffer memory, and whether upgrades minimal error number; If hard decoder module decodes not repairable cycle tests, finite state machine directly abandons its decoded result; Hard decoder process terminates each time, and whether finite state machine has the cycle tests of not decoding to determine whether to need to stop decode iteration according to current; Whether solution appears effective code word judges whether successfully decoding according to hard decoder module in iterative process to stop after iteration finite state machine, and controls candidate codewords buffer memory, if successfully decoded, exports data in buffer memory, otherwise exports complete zero.
6. the realizing circuit of the soft decoding algorithm of BCH according to claim 4, it is characterized in that described hard decoder module is made up of 3 modules such as syndrome computing module 31, error location polynomial computing module 32, money search modules 33, hard decoder is mainly divided into three steps: syndrome generates, error location polynomial generates, error location polynomial solves; The step that the syndrome wherein calculating word to be decoded generates is completed by syndrome computing module, and according to syndrome be whether 0 judge in code word whether wrong; Syndrome result is input in error location polynomial computing module, and this module calculates the error location polynomial of word to be decoded accordingly; Money search module is responsible for solving error location polynomial, and result is vicious position in word to be decoded, is characterized by error vector, and judges whether the mistake in word to be decoded can separate according to the relation of polynomial number of times and t in solution procedure.
7. the realizing circuit of the soft decoding algorithm of BCH according to claim 4, is characterized in that described cycle tests generation module, comprises 3 multiplexers (41,42,43), codeword register group, counter, comparator; Codeword register group is used for buffer memory word to be decoded, and it is made up of some and 1 bit register, and the code word size that register number is separated by decoder determines; Inner counter is by finite states machine control, for calculating the position of data in word to be decoded that present clock period codeword register group exports, it compares with some in undefined position 1 to undefined position t by comparator, is selected by finite states machine control second multiplexer (42) by the data compared; When equal, by the data-conversion that codeword register group exports, select its output valve by controlling the 3rd multiplexer (43), the XOR value namely exporting data with codeword register group is 1 to realize; In the process of soft decoding iteration each time, while this test vector is exported to hard decoder module, control the first multiplexer (41) by state machine and be stored in codeword register group; When next iteration, state machine controls the second multiplexer (42) and selects different positional values, and the code word of such opposite position will by negate.
8. the realizing circuit of the soft decoding algorithm of BCH according to claim 4, it is characterized in that described candidate codewords buffer memory comprises multiplexer, codeword register group, the unidirectional shift register that codeword register group is made up of several 1 bit register, number is the figure place of information bit in word to be decoded, for buffer memory candidate codewords; As when effectively exporting, just control the clock end of candidate codewords buffer memory, and to serial input decoded result in first bit register, decoded result can be displaced in the register of buffer memory successively when state machine judges that the decoding of hard decoder exports; Finally at the end of decoding, state machine is according to whether producing effective code word in decode iteration process, and control multiplexer is using the candidate codewords in buffer memory or export complete zero and export as last solution code data.
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Application publication date: 20150617 |