CN101777926B - General decoder of Turbo product code and method thereof - Google Patents
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Abstract
The invention discloses a general decoder of a Turbo product code and a method thereof. The general decoder consists of an initial information storage module, an external information storage module, an unreliable site calculation module, a algebra decipher module, two first in first out (FIFO) storage modules, a measure comparison module, an external information calculation module, a decipher control module and an interface. The decipher parameters of the general decoder can be configured freely at random, i.e. two-dimensional subcodes and decipher times of the Turbo product code can be selected at random, thus satisfying the requirements of various communication systems on different code lengths, code rates, code delay and throughout; the structured design and flexible use of the device can be realized by not only a programmable logic device but also a special chip; and the pipeline architecture is adopted by several parts of the device, thus improving the throughout of the decoder. The invention gives consideration to three indexes of generality, decipher property and complexity, and can be conveniently and flexibly used in various communication systems with the requirements on code lengths, code rates, realization platforms and error rates.
Description
Technical field
The present invention relates to mobile communication technology field, relate in particular to a kind of general decoder and method thereof of Turbo product code.
Background technology
Turbo code enjoys gazing at of communication circle as a kind of novel error correction coding type, and its error correcting capability can approach the Shannon limit.After Turbo code was proposed by C.Berrou from 1993, the method that has become its realization of focus of chnnel coding research is divided into two types substantially: enhancement mode Turbo product coding (TurboProduct Codes TPC) and enhancement mode convolutional encoding (Turbo Convolutional Codes TCC).TPC shows tempting application prospect in many aspects, and the code efficiency of TPC is high compared with TCC on the one hand, and the main advantage of TPC is that it adopts matrix intersector mode in addition, and this makes system configuration relatively simple.Turbo product coding structure connected in series also has many advantages than the structure of Turbo convolutional encoding parallel join.Mainly that decoding is studied for a kind of general Turbo product code (TPC) herein.Several hard decisions that were once born in the evolution of product code and Soft decision decoding algorithm, all different on implementation complexity and error-correcting performance.But Turbo product code adopts soft inputting and soft output (SISO, Soft-Input Soft-Output) decoded mode of iteration, this interpretation method better performances.
But in the face of different business demand and communication systems, if the decoder of fixed single implements, must have inconvenience, and there is no at present a kind of like this general decoder, most of implementations are all for specific code word or code check.So inventor has proposed this general Turbo product code decoder, for different code length, code check, platform, the communication system of decoding delay and throughput demand is carried out decoding.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of general decoder and method thereof of Turbo product code is provided
The configuration parameter of the general decoder of Turbo product code has: the subcode pattern of Turbo product code, iterations, which comprises at least:
Initial information memory module, the receiving sequence needing for storing each decoding;
External information memory module, for storing each decoding soft information in outside that need and that obtain;
The first first-in first-out module or the second first-in first-out module, for the temporary transient list entries that stores decoding;
Unreliable position computing module, converts list entries according to the unreliable figure place in exterior arrangement parameter, obtains the list entries of algebraic decoding;
Algebraic decoding module, carries out different algebraic decodings according to configuration parameter difference;
Tolerance comparison module, by comparing the Euclidean distance of the output of algebraic decoding module, obtains optimum code word D;
External information computing module, calculates the soft information in outside of this iteration, offers next iteration;
Control module, the sequential to above-mentioned various modules, parameter is selected to control;
Interface module, carries out parameter setting;
External information storage computing module is respectively with the first first-in first-out module, least reliable bits computing module, the input of external information module are connected; Initial information memory module is respectively with the first first-in first-out module, least reliable bits computing module is connected; The first first-in first-out module is connected with external information storage computing module, initial information memory module, the second first-in first-out module, tolerance comparison module respectively; Least reliable bits computing module is connected with initial information memory module, external information memory module, algebraic decoding module respectively; Algebraic decoding module is connected with least reliable computing module, tolerance comparison module respectively; The second first-in first-out module is connected with the first first-in first-out module, the input of external information module respectively; Tolerance comparison module is connected with the first first-in first-out module, algebraic decoding module, the input of external information module respectively; The input of external information module is connected with tolerance comparison module, the second first-in first-out module, external information storage computing module respectively; Above-mentioned module is controlled by control module; In interface module, carry out parameter setting.
It is 64 any Hamming code or extended hamming code and shortening code thereof that the subcode pattern of described Turbo product code can be maximum length code length, and to shorten figure place be Arbitrary Digit, the length that maximum is this code word.
Described iterations is according to the Arbitrary Digit of decoding delay and error rate setting.
Described external information memory module, the capacity of initial information memory module is 64 unit * Unit 64, the capacity of each unit is its quantizing bit number.
The first described first-in first-out module or the capacity of the second first-in first-out module are 2*64 unit, the capacity of each unit is the quantization bit that soft information is inputted in decoding, wherein to read order be the order that data write, after data reading, data be sky in first-in first-out module.
Described algebraic decoding module comprises that component code code length is 64 any Hamming code or extended hamming code and shortening code thereof to the maximum.
The general decoding method of Turbo product code comprises the following steps:
1) parametrization configures, and sets as required two-dimentional subcode and the iterations of Turbo product code decoding in interface module;
2) the demodulation symbol information of receive channel output, deposits the required received information sequence of this decoding in initial information memory module in, and external information memory module initial information is 0, starts once the iterative decoding of row or row;
3) calculate the required sequence information of decoding, deposit in a first-in first-out module, find least reliable 3 is 3 of metric minimum simultaneously, and these 3 code words are got respectively to 0 or 1, obtains 8 candidate codewords sequences;
4) these 8 code words are carried out to algebraic decoding in algebraic decoding module, the algebraic decoding method of different configurations is different, obtains the code word after 8 algebraic decodings;
5) output of the output codons of algebraic decoding and first first-in first-out module is sent into tolerance comparison module, find the code word of Euclidean distance minimum, be judged to the optimum code word of this row or row, second first-in first-out module read in the output of first first-in first-out module simultaneously;
6) output of the output of second first-in first-out module and tolerance comparison module is sent into external information computing module, calculate the soft information in outside of this row or column iteration of this time, and deposit in outside soft information-storing device, this row or column decoding are complete;
7) repeat above-mentioned steps, until all row or column decoding are complete, be listed as or row decoding, whole after an iteration finish;
8) repeat above-mentioned steps, according to parameter configuration, control module is controlled whole process until whole iteration finishes;
Row and the row of Turbo product code subcode, the decoding between row and row adopts pipeline organization.
The present invention has realized code length, and code check and iterations are variable, and multi-platform streamlined Turbo product code decoding, and this decoder has been carried out to a series of tests for the Turbo product code of different subcodes formations and the performance of different iterations decodings.This general decoder has very strong portability, goes for different communication systems.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of Turbo product code general decoder of the present invention;
Fig. 2 is Turbo product code general decoder internal structure block diagram of the present invention;
Fig. 3 is each decode procedure of Turbo product code general decoder of the present invention;
Fig. 4 is the structure of first-in first-out module of the present invention;
Fig. 5 is the workflow of algebraic(al) decoder of the present invention;
Fig. 6 is the flowing structure that the present invention measures comparison module;
Fig. 7 is the iterative decoding process of Turbo product code general decoder of the present invention;
Fig. 8 is the Turbo product code decoding performance test curve figure that (15,11) * (15,11) Hamming code and (31,26) * (31,26) Hamming code form;
Fig. 9 is the Turbo product code decoding performance test curve figure that (31,26) * (31,26) Hamming code and (32,26) * (32,26) extended hamming code form;
Figure 10 is the Turbo product code decoding performance test curve figure of different iterationses.Below in conjunction with accompanying drawing, the present invention is further described:
Embodiment is further described the present invention below in conjunction with accompanying drawing:
The general decoder of Turbo product code can be for different code length, code check, and platform, the communication system of decoding delay and throughput demand is carried out decoding.It is 64 any Hamming code or extended hamming code and shortening code thereof that this subcode two dimension is all chosen as maximum length code length, and to shorten figure place be Arbitrary Digit, the length that maximum is this code word.Can be used in different code length like this, the needs of code check; Decoding number of times can be selected arbitrarily, meets the demand of decoding latency and throughput; Its structurized design is used flexibly, and autgmentability is good, both can realize with programmable logic device, as FPGA, also can use special chip (ASIC) to realize; Many places adopt pipeline organization, have fully improved the throughput of decoder.Can be applicable to different communication systems, easy to use, simple in structure clear.
The general decoder of Turbo product code, its configuration parameter has: the subcode pattern of Turbo product code, iterations, the internal structure of this Turbo product code general decoder as shown in Figure 2, which comprises at least:
Initial information memory module 202, the receiving sequence needing for storing each decoding;
External information memory module 201, for storing each decoding soft information in outside that need and that obtain;
The first first-in first-out module 203 or the second first-in first-out module 206, for the temporary transient list entries that stores decoding;
Unreliable position computing module 204, converts list entries according to the unreliable figure place in exterior arrangement parameter, obtains the list entries of algebraic decoding;
External information computing module 208, calculates the soft information in outside of this iteration, offers next iteration;
External information storage computing module 201 is respectively with the first first-in first-out module 203, least reliable bits computing module 204, external information module input 208 are connected; Initial information memory module 202 is respectively with the first first-in first-out module 203, least reliable bits computing module 204 is connected; The first first-in first-out module 203 is connected with external information storage computing module 201, initial information memory module 202, the second first-in first-out module 206, tolerance comparison module 207 respectively; Least reliable bits computing module 204 is connected with initial information memory module 202, external information memory module 201, algebraic decoding module 205 respectively; Algebraic decoding module 205 is connected with least reliable computing module 204, tolerance comparison module 207 respectively; The second first-in first-out module 206 is connected with the first first-in first-out module 203, external information module input 208 respectively; Tolerance comparison module 207 is connected with the first first-in first-out module 203, algebraic decoding module 205, external information module input 208 respectively; External information module input 208 is connected with tolerance comparison module 207, the second first-in first-out module 206, external information storage computing module 201 respectively; Above-mentioned module is controlled by control module 209; In interface module 101, carry out parameter setting.
It is 64 any Hamming code or extended hamming code and shortening code thereof that the subcode pattern of described Turbo product code can be maximum length code length, and to shorten figure place be Arbitrary Digit, the length that maximum is this code word.
Described iterations is according to the Arbitrary Digit of decoding delay and error rate setting.
Described external information memory module 201, the capacity of initial information memory module 202 is 64 unit * Unit 64, the capacity of each unit is its quantizing bit number.
The first described first-in first-out module 203 or the capacity of the second first-in first-out module 206 are 2*64 unit, the capacity of each unit is the quantization bit that soft information is inputted in decoding, wherein to read order be the order that data write, after data reading, data be sky in first-in first-out module.
Described algebraic decoding module 205 comprises that component code code length is 64 any Hamming code or extended hamming code and shortening code thereof to the maximum.
As shown in Figure 1, need the selectable parameter of Turbo two dimension product code of decoding is iterations P1.1 to the schematic diagram of general Turbo decoder, can arrange according to the demand of complexity; Horizontal and vertical subcode type parameter P1.2, it comprises that maximum length code length is 64 any Hamming code or extended hamming code and shortening code thereof, and to shorten figure place be Arbitrary Digit, the length that maximum is this code word.
Turbo product code decoder inner parameter configuration to these different-formats is different, so the parameter of setting is transmitted into inside by interface module, realizes general Turbo product code decoding.
The general decoding method of Turbo product code comprises the following steps:
1) parametrization configures, and sets as required two-dimentional subcode and the iterations of Turbo product code decoding in interface module;
2) the demodulation symbol information of receive channel output, deposits the required received information sequence of this decoding in initial information memory module in, and external information memory module initial information is 0, starts once the iterative decoding of row or row;
3) calculate the required sequence information of decoding, deposit in a first-in first-out module, find least reliable 3 is 3 of metric minimum simultaneously, and these 3 code words are got respectively to 0 or 1, obtains 8 candidate codewords sequences;
4) these 8 code words are carried out to algebraic decoding in algebraic decoding module, the algebraic decoding method of different configurations is different, obtains the code word after 8 algebraic decodings;
5) output of the output codons of algebraic decoding and first first-in first-out module is sent into tolerance comparison module, find the code word of Euclidean distance minimum, be judged to the optimum code word of this row or row, second first-in first-out module read in the output of first first-in first-out module simultaneously;
6) output of the output of second first-in first-out module and tolerance comparison module is sent into external information computing module, calculate the soft information in outside of this row or column iteration of this time, and deposit in outside soft information-storing device, this row or column decoding are complete;
7) repeat above-mentioned steps, until all row or column decoding are complete, be listed as or row decoding, whole after an iteration finish;
8) repeat above-mentioned steps, according to parameter configuration, control module is controlled whole process until whole iteration finishes;
The concrete decoding flow process of each iteration as shown in Figure 3,
First, be that above-mentioned steps 2 is from initial information memory module 202 and external information memory module 201, to read in sequence and the soft information receiving, because be 64 according to configurable code word maximum length, so the size of RAM is 64 unit, unit * 64, the size of each unit is the quantizing bit number of external information and soft information, by the information receiving, calculate soft input, for the m time iteration
R(m)＝R+α(m)·W(m)
Wherein, the signal that R---decoder receives
R (m)---the soft input signal of m cell decoder
W (m)---the external information of upper level cell decoder output, initial value is zero
α (m)---adjustment factor
The poor difference of sampling standard due to [R] and [W (m)], the sampling standard of [W (m)] is poor larger when starting, along with the increase of iterations, reduce gradually, therefore need to introduce adjustment factor α (m), α (m) had played the effect of inhibition [W (m)] when the decoding initial stage, signal to noise ratio was larger.The value of α (m) is along with iterative process increases progressively, and in the decoding later stage, initial input signal [R] reduces gradually on the impact of soft input, the reliability of the value of W constantly increases, can be used as the Main Basis of decoding, it increases gradually on soft input impact, to reach optimal decoding effect.Obtain after soft input value, just start input value to carry out Soft decision decoding, soft input message is carried out to decoding., soft information is deposited in first-in first-out module 203, as shown in Figure 4, when writing enable signal, R (m) deposits in first-in first-out module the structure of first-in first-out module meanwhile; When reading enable signal, R (m) reads first-in first-out module; First-in first-out module is sky after all reading.In order to prevent overflowing, it is 64 unit * 2 that its size is set.
The 2nd step, above-mentioned steps 3 is in reliable bits computing module 204 least, soft list entries r to be carried out to hard decision to obtain sequence z, and each of z is distributed to reliability value; Get the p position that in z, reliability is minimum, this p position is got respectively to 0 or 1 and obtain 2
pindividual error pattern, is added these error patterns respectively with firmly sentencing the sequence z obtaining, produce candidate codewords set omega;
In an embodiment, make p=3, in Ω, have at most 8 different code words.Can, to doing and compromise between decoding performance and complexity, be easier to realize like this.
The 3rd step, above-mentioned steps 4 is then each code word in candidate codewords set omega to be carried out to algebraic decoding to obtain code word v, and the Turbo product code for different parameters, adopts different algebraic decodings, and this is the core of versatility, as shown in Figure 5.In an embodiment, chosen (15,11) * code word of (15,11), and (31,26) * (31,26), have or not the Hamming code word of check digit to test;
Hamming code word for no parity check position, as embodiment (15,11) * (15,11) and (31,26) * (31,26) directly carry out algebraic decoding, for the Hamming code word that has check digit, first carry out algebraic decoding, then, according to the value of error pattern err and parity check bit c, carry out different processing.
For the Hamming code shortening, first fill out 0, and give high confidence values to filling out 0, carry out the least searching of reliable bits and then carry out algebraic decoding as above.
Simultaneously in the second first-in first-out module 206 of input information in first first-in first-out module 203.
The 4th step, above-mentioned steps 5 is in tolerance comparison module 207, to calculate the Soft decision decoding tolerance of each candidate codewords, selects most probable code word.Conventionally calculate the Euclidean distance between each candidate codewords and soft list entries, select the code word of Euclidean distance minimum as judgement code word D.
The 5th step, above-mentioned steps 3 is to calculate competition code word C, need search for each that obtains adjudicating code word D.So by the input information external information computing module 208 of second first-in first-out module 206, in external information computing module 208 to each in D, in 8 code words of set omega, search for, see and whether have code word contrary with its symbol on relevant position, if there is the contrary code word of symbol,, in the contrary code word of these symbols, be competition code word with the code word of the soft input vector Euclidean distance of this step decoding minimum.If there is not the contrary code word of symbol, there is not competition code word in this position.Specific embodiments as shown in Figure 6, adopts flowing structure.By the i position data[i of 8 candidate codewords] do xor operation with optimum code word D, if 0 is 0 by its corresponding Euclidean distance assignment; If 1 retains its Euclidean distance dis, then relatively obtain between two four relatively large distance value dismin1, dismin2, dismin3, dismin4, then these 4 code words are relatively obtained to relatively large distance dismaxa, dismaxb between two, relatively these 2 values obtain code word corresponding to maximum Euclidean distance again, compete code word C.
If can find competition code word, this external information computational methods are as follows:
Wherein, R----this grade of soft input of decoder
C---this competition code word
D---softly sentence the judgement code word that decoding obtains
Dj---the j position of judgement code word D
J---the j position of soft input R
As can be seen from the above equation, soft output r
j=r
j+ w
jsymbol identical with dj, its absolute value has represented the reliability of soft output; If can not find competition code word in candidate codewords set omega, illustrate that the Euclidean distance of C and R is very large, the reliability of dj is very high; If the Euclidean distance of C and R is far, illustrate that the reliability of dj is very high,
If can not find competition code word, computational methods are:
w
j＝β·dj
As can be seen from the above equation, calculate external information, also need to calculate the value of β.β (m) is used for controlling the output peak value scope of Soft output information, and it can be determined by experiment, and also can estimate by certain methods.The value of B can and correct mistakes initialization by continuous experiment.The normal shortcut calculation that adopts.Can estimate β by the reliability value of soft input, to competing every reliability value of code word in judgement code word D, not be averaged, the β value accuracy obtaining like this will almost, still be easy to realize.
Calculate after the value of external information, deposited in external information memory module 201, just can further calculate soft output.The value that value of soft output equals soft input adds external information,
r′＝r+w
Once complete iteration is divided into a row decoding and a column decoding, and its concrete decoding procedure is identical, and the iterative decoding process that the alternately decoding of row and row has just formed BPTC as shown in Figure 7.According to parameter setting, carry out the iteration of different number of times.The decoding code word of final output gained.And row and the row of Turbo product code subcode, the decoding between row and row adopts pipeline organization, increases decoding speed, improves throughput.
As Fig. 8, shown in 9,10, provided above-mentioned specific embodiments of the present invention and disturbed the ber curve under (awgn channel) condition at random bit.The simulated conditions adopting is BPSK modulation, α { 0.0625,0.125,0.1875,0.25,0.3125,0.375,0.4375,0.5,0.5625,0.625,0.6875,0.75,0.8125,0.875,0.9375,1}.If Fig. 8 is the decoding performance of the Turbo product code that adopts different length subcode to form: (15,11) * (15,11) and two kinds of TPC codes of (31,26) * (31,26).As whether Fig. 9 increases the decoding performance of the TPC code of check digit.As Figure 10 be the asynchronous Performance Ratio of iterations.Along with the further increase of iterations, the improvement of decoding performance is slow gradually; When iterations is increased to a certain degree, performance just remains unchanged substantially, can not improve.Therefore, we need to select suitable iterations when carrying out decoding, when obtaining optimal performance, guarantee that complexity is lower.
As mentioned above, maximum feature of the present invention is that its Turbo product code that different subcodes are formed all can be translated, and considers speed and flexibility, and the present embodiment selects FPGA to test this general Turbo product code decoder.But the Structured Design of this device also can use special chip (ASIC) to realize, under the little situation of data throughout, can also use digital signal processor (DSP) to realize, in addition, in conjunction with the general design cycle of computer software, it is also feasible utilizing software to realize.
The present invention is a kind of general Turbo product code decoder and method thereof.Method described here and circuit, single component separated from one another can be traditional completely, we require their combination to protect as invention.The foregoing is only the embodiment of certain applications, but true spirit of the present invention and scope are not limited to this, any those of ordinary skill in the art can amendment body component concrete grammar, realize the Turbo product code decoding of different application occasion.The present invention is only limited by appended claim book and equivalence techniques scheme thereof, and we require these as the present invention, to protect.
Claims (9)
1. a general decoder for Turbo product code, its configuration parameter has: the subcode pattern of Turbo product code, iterations, is characterized in which comprises at least:
Initial information memory module (202), the receiving sequence needing for storing each decoding;
External information memory module (201), for storing each decoding soft information in outside that need and that obtain;
The first first-in first-out module (203) and the second first-in first-out module (206), for the temporary transient list entries that stores decoding;
Least reliable bits computing module (204), converts list entries according to the unreliable figure place in exterior arrangement parameter, obtains the list entries of algebraic decoding;
Algebraic decoding module (205), carries out different algebraic decodings according to configuration parameter difference;
Tolerance comparison module (207), by comparing the Euclidean distance of the output of algebraic decoding module, obtains optimum code word D;
External information computing module (208), calculates the soft information in outside of this iteration, offers next iteration;
Control module (209), the sequential to above-mentioned various modules, parameter is selected to control;
Interface module (101), carries out parameter setting;
External information memory module (201) is respectively with the first first-in first-out module (203), least reliable bits computing module (204), external information computing module (208) are connected; Initial information memory module (202) is respectively with the first first-in first-out module (203), least reliable bits computing module (204) is connected; The first first-in first-out module (203) is connected with external information memory module (201), initial information memory module (202), the second first-in first-out module (206), tolerance comparison module (207) respectively; Least reliable bits computing module (204) is connected with initial information memory module (202), external information memory module (201), algebraic decoding module (205) respectively; Reliable bits computing module (204), tolerance comparison module (207) are connected algebraic decoding module (205) respectively with least; The second first-in first-out module (206) is connected with the first first-in first-out module (203), external information computing module (208) respectively; Tolerance comparison module (207) is connected with the first first-in first-out module (203), algebraic decoding module (205), external information computing module (208) respectively; External information computing module (208) is connected with tolerance comparison module (207), the second first-in first-out module (206), external information memory module (201) respectively; External information memory module (201) to external information computing module (208) is controlled by control module (209); In interface module (101), carry out parameter setting.
2. the general decoder of a kind of Turbo product code according to claim 1, is characterized in that, the subcode pattern of described Turbo product code is that maximum length code length is any Hamming code of 64.
3. the general decoder of a kind of Turbo product code according to claim 1, is characterized in that, the subcode pattern of described Turbo product code is extended hamming code.
4. the general decoder of a kind of Turbo product code according to claim 1, is characterized in that, the shortening code that the subcode pattern of described Turbo product code is Hamming code, and to shorten figure place be Arbitrary Digit, the code length that maximum is subcode.
5. the general decoder of a kind of Turbo product code according to claim 1, is characterized in that, described iterations is according to the Arbitrary Digit of decoding delay and error rate setting.
6. the general decoder of a kind of Turbo product code according to claim 1, it is characterized in that, described external information memory module (201), the capacity of initial information memory module (202) is 64 unit * Unit 64, and the capacity of each unit is in unit, to store the quantizing bit number of information.
7. the general decoder of a kind of Turbo product code according to claim 1, it is characterized in that, the first described first-in first-out module (203) and the capacity of the second first-in first-out module (206) are 2*64 unit, the capacity of each unit is the quantization bit that soft information is inputted in decoding, wherein to read order be the order that data write, after data reading, data be sky in first-in first-out module.
8. use a general decoding method for the Turbo product code of general decoder as claimed in claim 1, it is characterized in that comprising the following steps:
1) parametrization configures, and sets as required two-dimentional subcode and the iterations of Turbo product code decoding in interface module;
2) the demodulation symbol information of receive channel output, deposits the required received information sequence of decoding in initial information memory module in, and external information memory module initial information is 0, starts once the iterative decoding of row or row;
3) calculate the required sequence information of decoding, deposit in the first first-in first-out module, find least reliable 3 is 3 of metric minimum simultaneously, and this 3 bit word is got respectively to 0 or 1, obtains 8 candidate codewords sequences;
4) these 8 candidate codewords sequences are carried out to algebraic decoding in algebraic decoding module, the algebraic decoding method of different configurations is different, obtains the code word after 8 algebraic decodings;
5) output of the output codons of algebraic decoding module and the first first-in first-out module is sent into tolerance comparison module, find the code word of Euclidean distance minimum, be judged to the optimum code word of the capable or row of this iterative decoding, the second first-in first-out module is read in the output of the first first-in first-out module simultaneously;
6) output of the output of the second first-in first-out module and tolerance comparison module is sent into external information computing module, calculate the soft information in outside of this iterative decoding row or column iteration, and deposit in external information memory module, this iterative decoding is capable or column decoding is complete;
7) repeat above-mentioned steps, until all row or column decoding are complete, be listed as or row decoding, whole after an iteration finish;
8) repeat above-mentioned steps, according to parameter configuration, control module is controlled whole process until whole iteration finishes.
9. the general decoding method of a kind of Turbo product code according to claim 8, is characterized in that, row and the row of described Turbo product code subcode, and the decoding between row and row adopts pipeline organization.
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| CN102568581B (en) * | 2010-12-20 | 2015-09-09 | 中国科学院电子学研究所 | A kind of laddering code translator being applicable to programmable storage |
| CN102523076B (en) * | 2012-01-04 | 2014-05-14 | 西安电子科技大学 | Universal and configurable high-speed Turbo code decoding method |
| US9391641B2 (en) * | 2013-04-26 | 2016-07-12 | SK Hynix Inc. | Syndrome tables for decoding turbo-product codes |
| CN106209324B (en) * | 2016-09-18 | 2023-05-19 | 幻视互动（北京）科技有限公司 | Intelligent head display device based on multi-frequency wireless networking module realized by FPGA |
| CN107682019B (en) * | 2017-09-28 | 2020-12-22 | 成都傅立叶电子科技有限公司 | TPC high-speed decoding method |
| CN109714061B (en) * | 2017-10-25 | 2023-04-14 | 中兴通讯股份有限公司 | Decoding method and device of Turbo product code and computer readable storage medium |
| CN110661534B (en) * | 2018-06-29 | 2024-06-18 | 中兴通讯股份有限公司 | Method and device for improving Turbo decoding performance and computer equipment |
| CN110661535B (en) * | 2018-06-29 | 2022-08-05 | 中兴通讯股份有限公司 | Method, device and computer equipment for improving Turbo decoding performance |
| CN114421976B (en) * | 2022-01-25 | 2023-09-08 | 电子科技大学 | TPC iterative decoding method and decoder based on probability calculation |
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