CN102594369B - Quasi-cyclic low-density parity check code decoder based on FPGA (field-programmable gate array) and decoding method - Google Patents

Abstract

The invention discloses a low-storage capacity high-speed QC-LDPC (quasi-cyclic low-density parity check) code decoder based on an FPGA (field-programmable gate array) and a decoding method, which are mainly used for solving the problem of low utilization efficiency of memory resources of a node update processing unit and an RAM (random access memory) of the decoder in the prior art. The decoder can simultaneously process two frames of decoding data, the decoder is used for setting an external information value of the first frame of data as all-zero and setting the second frame of data as a channel for receiving likelihood ratio information in the data initialization phase, so that a variable node processing unit and a check node processing unit can completely alternately process the two data frames in parallel in the whole decoding process, effectively shorten the work clock cycle required for processing the two frames of data and enable the decoding throughput to be about two times as that of a traditional design method. According to the decoder disclosed by the invention, a dynamic address access management method is adopted in external information access, and the parallel access of the two frames of decoding data can be realized in the single RAM; and compared with the existing decoder, the utilization efficiency of BRAM (broadcast recognition access method) resources is doubled in comparison with the existing decoders, and the decoder can be used for error correction in information transmission of a physical layer based on LDPC codes.

Description

Quasi-cyclic Low-density Parity-check Codes decoder and interpretation method based on FPGA

Technical field

The invention belongs to communication technical field, relate to channel error correction encoding decoder, particularly a kind of Quasi-cyclic Low-density Parity-check Codes decoder and interpretation method based on FPGA, can be used for the physical layer information transmission error correction based on LDPC code.

Background technology

Tradition quasi-cyclic low-density verification QC-LDPC code decoder is mainly made up of variable node computing module VNU, check node calculation module CNU, check equations computing module PCU and some memory modules, wherein memory module comprises three parts, respectively channel initial information memory module RAM_F, iteration external information memory module RAM_M and decoding code word memory module RAM_C, as shown in Figure 1.The QC-LDPC code decoder that is m × n for basic matrix block count, VNU module comprises n concrete variable node computing unit VNU _j, 1≤j≤n, CNU module comprises m variable node computing unit CNU _i, 1≤i≤m, RAM_F module comprises n block RAM memory block F _j, 1≤j≤n, RAM_M module comprises m × n block RAM memory block M _{i, j}, 1≤i≤m, 1≤j≤n.Every F _jcontain one and CNU _ithe read port being connected, every M _{i, j}contain two reading-writing port, two ports all and VNU _jand CNU _ibe connected.Channel information in external information and RAM_F in RAM_M all uses static address way to manage, and the external information that each node is corresponding and the read/write address of channel information are fixed value.If it is z × z that the submatrix of LDPC verification battle array divides block size, the specific works process of QC-LDPC code decoder iterative decoding is as follows: (1) initialization: the channel information sequence of reception is divided into n piecemeal and stores respectively n F in RAM_F into _jin memory block, by the external information memory block M in RAM_M _{i, j}, 1≤i≤m, it is complete zero that 1≤j≤n is initialized as, and initialization iterations iter is set to 0 time; (2) variable node upgrades: each variable node computing unit VNU _jthe M that sequential update is coupled _{i, j}in z external information, external information of every renewal, VNU _jrespectively from F _jand M _{i, j}read port in read a channel information and an external information, carry out the renewal of variable node and calculate and the judgement of this decoding code word, new external information and decoding code word are write respectively to M _{i, j}in RAM_C.Reading, calculate and writing with pipeline system of each nodal information completes; (3) check-node upgrades: each check node calculation unit CNU _ithe M that sequential update is coupled _{i, j}in z external information, external information CNU of every renewal _ifrom the M being attached thereto _{i, j}read port in read an external information, the renewal of carrying out check-node after calculating is returned new external information into M _{i, j}in.Reading, calculate and writing with pipeline system of each check-node information completes.Meanwhile, PCU takes out decoding codeword information from RAM_C, and code word and check matrix are multiplied each other, and produces syndrome vector; (4) by iterations iter cumulative 1.If the syndrome calculating vector, for complete zero, represents that the decoding code word that this time judgement obtains is legal-code, or iter reached maximum iteration time MAX_ITER, proceeds to so step (5)

By decode results output, otherwise, turn back to step (2) and proceed the iterative computation of next round; (5) the decoding code word in RAM_C memory module is read as final decode results output.

In the access of memory, VNU and CNU are a kind of access method of switched to the read-write of RAM_M, and in the time that VNU works, the access right of RAM_M is by VNU module controls, and in the time that CNU works, the access right of RAM_M is by CNU module controls.Memory M _{i, j}in reading and writing data adopt static address way to manage, the memory address of each extrinsic information data is fixed value.Z extrinsic information data of the sub-piecemeal of each check matrix is stored in the M corresponding with it _{i, j}in, z is the dimension of syndrome matrix, i, and j is respectively row piecemeal sequence number and the row piecemeal sequence number of syndrome matrix.VNU in step (2) _jneed column major order read-write M _{i, j}in z external information, this submatrix first row is fixed as 0～z to the external information reference address of z row, while reading and writing data, its initial reference address is 0, the read/write address cumulative 1 of every next external information; CNU in step (3) _iread and write M by row order _{i, j}in z extrinsic information data, if the cycle offset of the capable j row of i syndrome matrix is α _ij, the reference address of the extrinsic information data that this submatrix x is capable is so (α _ij+ x) modz, while reading and writing data, initial reference address is α _ij, every next read/write address is that a upper address adds the 1 rear value to z delivery, the read/write address schematic diagram of this static address way to manage is as shown in Figure 2.

Because the iterative decoding process of LDPC code is the process that a variable node and check-node alternately transmit external information, VNU and CNU input and output each other, in the course of work of traditional ldpc code decoder, VNU and CNU only have a side in work simultaneously, most for the treatment of circuit in decoder in half decoding time in idle condition, therefore cause the utilization ratio of FPGA hardware resource lower, Fig. 3 has provided both work schedules in iterative decoding process.

For the lower problem of traditional ldpc code decoder hardware resource utilization efficiency, the decoder design method of the decoding simultaneously of a kind of two frame data, the different external informations of decoding computing unit alternate treatment two frames is suggested.The variable node computing unit VNU of decoder is connected two frame coding data with check node calculation unit CNU simultaneously, RAM_F1 and RAM_F2 store respectively the channel information of two Frames, RAM_M1 and RAM_M2 store respectively the external information of two Frames, RAM_C1 and RAM_C2 store respectively the judgement code word of two Frames, its decode procedure is as follows: (1) initialization: two frame channel information sequences are stored into respectively in RAM_F1 and RAM_F2, the iterative processing number of times that external information in RAM_M1 and RAM_M2 is initialized as to complete zero, two Frame is made as 0 time; The variable node of (2) first frames upgrades: first VNU processing unit completes the variable node renewal of the first frame data, and now CNU processing unit is temporarily idle; The parallel renewal of variable node of the check-node of (3) first frames and the second frame: the check-node that CNU processing unit completes the first frame data upgrades, VNU processing unit jumps to the variable node renewal that completes the second frame data on the second frame simultaneously; (4) exchange two frame data are processed: if in last round of renewal, CNU upgrades the first frame data, and VNU upgrades the second frame data, and CNU forwards the renewal that completes check-node on the second frame to, and VNU forwards the renewal that completes variable node on the first frame to; Otherwise the check-node that CNU completes the first frame data upgrades, the variable node that VNU completes the second frame data upgrades; (5) complete zero if the syndrome vector of two frames is, or reached maximum iteration time, proceed to step (6) by decode results output, otherwise, proceed to step (4) and proceed the exchange iterative processing of two frame data; (6) the decoding code word of RAM_C1 and RAM_C2 two memory modules is read as final decode results output.

The VPU of this improved two frame parallel decoding methods and CPU upgrade sequential as shown in Figure 4.Due to VPU two Frames different with CPU alternate treatment, the decoder throughput that the method design obtains approaches the twice of traditional design method, but because each ram port in FPGA can only be read and write the data on address at every turn, adopt traditional static address management method, reading and writing of each external information need to take two different ports, the port number of every block RAM resource mostly is 2 most, therefore two frame data of decoder must be stored in respectively in two different block RAMs, and the RAM resource requirement quantity of this decoder is the twice of conventional method.In addition, because decoder only has VNU in running order in the decoding incipient stage, there is free timeslot in CNU, and the method is not accomplished the complete parallel work of VNU and CNU two processing units.

Summary of the invention

The object of the invention is to the deficiency for above-mentioned prior art, a kind of Quasi-cyclic Low-density Parity-check Codes decoder and interpretation method based on FPGA is provided, to reduce the quantity that takies of FPGA storage resources, improve the utilization ratio of logical resource and RAM resource in decoder, and improve the decoding throughput of decoder.

For achieving the above object, check code decoder of the present invention, comprising:

Variable node computing module VNU, upgrades and calculates for the variable node external information to decoding, wherein comprises n variable node computing unit VNU _j, 1≤j≤n, the row piecemeal quantity that n is basic matrix;

Check node calculation module CNU, upgrades and calculates for the check-node external information to decoding, wherein comprises m check node calculation unit CNU _i, 1≤i≤m, the row piecemeal quantity that m is basic matrix;

Whether check equations computing module PCU is legal-code for verification decode results;

Channel initial information memory module RAM_F, for the channel likelihood ratio information of storing received, wherein comprises n block RAM memory block F _j, 1≤j≤n;

Iteration external information memory module RAM_M, the iteration external information of mutually transmitting for storing iterative decoding process variable node and check-node, wherein comprises m × n block RAM memory block M _{i, j}, 1≤i≤m, 1≤j≤n;

Decoding code word memory module RAM_C, the code word result obtaining for storing decoding;

It is characterized in that:

Every block RAM in tri-modules of described RAM_F, RAM_M and RAM_C is all stored two different frame coding data;

Described every memory block F _jin contain two read ports, these two read ports all with check node calculation unit CNU _ibe connected, be responsible for respectively reading of the different channel initial information of two frames;

Described every memory block M _{i, j}in contain two reading-writing port, its read-write mode is " write-after-read pattern ", each reading-writing port all with variable node computing unit VNU _jwith check node calculation unit CNU _ibe connected, the each read-write of being responsible for a frame iteration external information of each port.

For achieving the above object, check code decoding method of the present invention, comprises the steps:

1) initialization: the each memory block F that the two frame channel likelihood ratio information that receive is deposited in to channel initial information memory module RAM_F according to the row piecemeal segmentation of check matrix H _iin, the address realm of two frame data is respectively 0～z-1 and z～2z-1, and z is the dimension of syndrome matrix; The first frame external information in iteration external information memory module RAM_M is initialized as to complete zero, the second frame external information and is initialized as channel reception likelihood ratio information; Iterations iter is initialized as 0 time;

2) check-node of the variable node to the first frame data and the second frame data upgrades:

2a) the each variable node computing unit VNU in variable node computing module _jupgrade one by one the M being attached thereto with row order _{i, j}in z external information, wherein VNU of the first frame _jupgrade the variable node computing unit calculating, M for carrying out j row variable node in VNU _{i, j}for storing the memory block of the capable j row of i syndrome matrix external information in RAM_M;

2b) the each check node calculation unit CNU in check node calculation module _iupgrade one by one with row order the M being attached thereto _{i, j}in z external information, wherein CNU of the second frame _iupgrade the check node calculation unit calculating, M for carrying out the capable check-node of i in CNU _{i, j}for storing the memory block of the capable j row of i syndrome matrix external information in RAM_M;

3) variable node of the check-node to the first frame data and the second frame data upgrades:

3a) the each check node calculation unit CNU in check node calculation module _iupgrade one by one with row order the M being attached thereto _{i, j}in z external information of the first frame;

3b) the each variable node computing unit VNU in variable node computing module _jupgrade one by one the M being attached thereto with row order _{i, j}in z external information of the second frame;

4) iterations iter is added to 1, calculate the syndrome vector s of the first frame coding result ₁syndrome vector s with the second frame coding result ₂if, s ₁=s ₂=0 or iter equal maximum iteration time MAX_ITER, execution step 5), otherwise forward step 2 to) proceed iterative decoding calculate;

5) from decoding code word memory module RAM_C, reading respectively two frame coding court verdicts exports as decode results.

The present invention is because the external information value of the first frame data is set to full 0 by the data initialization stage at decoder, the external information value of the second frame data is made as to channel and receives likelihood ratio information, can make code check node processing unit just can walk abreast together with variable node processing unit and carry out the iteration renewal processing of two frame coding data in the incipient stage of decode procedure, effectively shorten and processed the required work clock cycle of two decoding data frames, thereby improved the decoding throughput of whole decoder; Simultaneously because the present invention has adopted dynamic address access management method in the access of external information, make variable node processing unit and code check node processing unit only need a ram port just can complete the read-write of a frame extrinsic information data, thereby can in monolithic RAM, realize the storage and inquire of two frame coding data simultaneously, compared with traditional design method, the BRAM resource utilization of decoder can double.

Realize result and show, the present invention can, in the case of the FPGA hardware resource quantity of QC-LDPC code decoder use is substantially constant, improve nearly one times by total decoding throughput of conventional decoder.

Brief description of the drawings

Fig. 1 is traditional ldpc code decoder structural representation;

Fig. 2 is the read/write address schematic diagram of existing static address way to manage;

Fig. 3 is the iteration working timing figure of VNU and CNU in conventional decoder;

Fig. 4 is that VPU and the CPU of existing improved two frame parallel decodings upgrades sequential chart;

Fig. 5 is low memory space high speed decoder structure chart provided by the invention;

Fig. 6 is the flow chart of low memory space high speed decoding method provided by the invention;

Fig. 7 is the external information dynamic address access schematic diagram in interpretation method of the present invention;

Fig. 8 is decoding performance analogous diagram of the present invention.

Embodiment

With reference to Fig. 5, low memory space high speed decoder structure provided by the invention mainly comprises 6 parts, is respectively variable node computing module VNU, check node calculation module CNU, check equations computing module PCU, channel initial information memory block RAM_F, iteration external information memory block RAM_M and decoding code word memory block RAM_C.Wherein, variable node computing module VNU, upgrades calculating for the variable node external information that completes decoding, and it comprises n variable node computing unit VNU _j, 1≤j≤n, the row piecemeal quantity that n is basic matrix; Check node calculation module CNU, upgrades calculating for the check-node external information that completes decoding, and it comprises m check node calculation unit CNU _i, 1≤i≤m, the row piecemeal quantity that m is basic matrix; Whether check equations computing module PCU is legal-code for verification decode results; Channel initial information memory module RAM_F, for the channel likelihood ratio information of storing received, it comprises n block RAM memory block F _j, 1≤j≤n; Iteration external information memory module RAM_M, the iteration external information of mutually transmitting for storing iterative decoding process variable node and check-node, it comprises m × n block RAM memory block M _{i, j}, 1≤i≤m, 1≤j≤n; Decoding code word memory module RAM_C, the code word result obtaining for storing decoding.Wherein, in the each RAM memory block in RAM_F, RAM_M and RAM_C, all have the decoding data of different two frames, they respectively: the decoding data of storing in RAM_F is that different two frame channels receive likelihood ratios; The decoding data of storing in RAM_C is two different frame coding court verdicts; The two frame coding data of storing in RAM_M are external information initial value, the initial external information of this first frame data storage is check-node external information, its value is full 0, and the initial external information of this second frame data storage is variable node external information, the likelihood ratio that its value receives for channel.

In decoder, the annexation of each module is as follows:

Every memory block F in RAM_F _jin contain two read ports, these two read ports all with check node calculation unit CNU _ibe connected, be responsible for respectively reading of the different channel initial information of two frames; Every memory block M in RAM_M _{i, j}in contain two reading-writing port, its read-write mode is " write-after-read pattern ", each reading-writing port all with variable node computing unit VNU _jwith check node calculation unit CNU _ibe connected, each port is each is responsible for the reading and writing of a frame iteration external information.The write port of RAM_C is connected with PCU with VNU respectively with read port, and VNU deposits judgement code word RAM_C in from write port, and PCU reads inspection from read port by judgement code word, and whether it is legal-code.

With reference to Fig. 6, low memory space high speed decoding method provided by the invention, its step is as follows:

Step 1, initialization: the each memory block F that the two frame channel likelihood ratio information that receive is deposited in to channel initial information memory module RAM_F according to the row piecemeal segmentation of check matrix H _jin, the address realm of two frame data is respectively 0～z-1 and z～2z-1, F _jfor storing the memory block of j row syndrome matrix channel initial information in RAM_M, z is the dimension of syndrome matrix; The first frame external information in iteration external information memory module RAM_M is initialized as to complete zero, the second frame external information and is initialized as channel reception likelihood ratio information; Iterations iter is initialized as 0 time;

Step 2, the check-node of the variable node to the first frame data and the second frame data upgrades:

Each variable node computing unit VNU in variable node computing module _jupgrade one by one the M being attached thereto with row order _{i, j}in z external information of the first frame; Meanwhile, the each check node calculation unit CNU in check node calculation module _iupgrade one by one with row order the M being attached thereto _{i, j}in z external information, wherein VNU of the second frame _jupgrade the variable node computing unit calculating, CNU for carrying out j row variable node in VNU _iupgrade the check node calculation unit calculating, M for carrying out the capable check-node of i in CNU _{i, j}for storing the memory block of the capable j row of i syndrome matrix external information in RAM_M;

Described variable node computing unit VNU _jthe renewal of each external information is divided into three steps: VNU _jfirst respectively from M _{i, j}and F _jin read required external information and the channel likelihood ratio information calculated of upgrading; VNU _jcarry out the renewal calculating of variable node according to the external information of reading and channel likelihood ratio information again, and complete the decoding bit decision of this node; VNU _jthe extrinsic information data finally renewal being calculated and decoding decision bits write respectively M _{i, j}in decoding code word memory module RAM_C.

Described check node calculation unit CNU _ithe renewal of each external information is also divided into three steps: CNU _ifirst from M _{i, j}in read to upgrade and calculate required external information; CNU _icarry out again the renewal calculating of variable node according to the external information of reading; CNU _ithe external information finally renewal being calculated is written back to M _{i, j}in;

Described variable node computing unit VNU _jwith check node calculation unit CNU _ito the renewal of each external information, need to be to M _{i, j}in extrinsic information data read and write, wherein M _{i, j}in the read-write of extrinsic information data adopt a kind of dynamic address access management method, often carry out the renewal of an external information, the external information memory address of each variable node and check-node will change, its address distribution method is as follows:

A) by M _{i, j}in z external information initial storage address of the first frame data be made as respectively 0～z-1, the z of the second frame data external information initial storage address is made as respectively to z～2z-1, z is the dimension of syndrome matrix;

B) after each variable node external information is upgraded and calculated, the memory address of this extrinsic information data will, from new distribution, be d if it reads address _v, its writing address will be set as (d _v+ L _v) modz, L _vit is VNU carries out variable node renewal streamline computational length to an extrinsic information data;

C) after each check-node external information is upgraded and calculated, the memory address of this extrinsic information data will, from new distribution, be d if it reads address _h, its writing address will be set as (d _h+ L _h) modz, L _hit is CNU carries out check-node renewal streamline computational length to an extrinsic information data.

For example, to the first frame variable node, if the initial storage address of its external information is l, and there is (l+2L _v+ L _h) modz < z, the address access process that its external information iteration is upgraded is as follows: variable node upgrades for the first time, and read and the writing address of this external information are respectively l and l+L _v; Check-node upgrades for the first time, and reading with writing address of this external information is respectively l+L _vand l+L _v+ L _h, variable node upgrades for the second time, and reading with writing address of this external information is respectively l+L _v+ L _hand l+2L _v+ L _h, after, the writing address that each check-node upgrades is read address for it and is added L _hresult to z delivery afterwards, the writing address that each variable node upgrades is read address for it and is added L _vresult to z delivery afterwards, as shown in Figure 7.

The address that this address distribution method makes the node external information that current needs read is identical with the address of upgrading the node external information that complete needs write, read-write mode by reading-writing port is set to " write-after-read pattern ", can in single reading-writing port, complete reading and writing of two variable node external informations or two check-node external informations simultaneously.

Step 3, the variable node of the check-node to the first frame data and the second frame data upgrades:

Each check node calculation unit CNU in check node calculation module _iupgrade one by one with row order the M being attached thereto _{i, j}in z external information of the first frame, the each variable node computing unit VNU in variable node computing module simultaneously _jupgrade one by one the M being attached thereto with row order _{i, j}in z external information of the second frame;

Step 4, adds 1 by iterations iter, calculates the syndrome vector s of the first frame coding result ₁syndrome vector s with the second frame coding result ₂if, s ₁=s ₂=0 or iter equal maximum iteration time MAX_ITER, execution step 5, otherwise forward to step 2 proceed iterative decoding calculate;

Step 5 is read respectively two frame coding court verdicts and is exported as decode results from decoding code word memory module RAM_C.

Decoder effect of the present invention can and realize result by following theory analysis and further illustrate:

1. the two frame start node extrinsic information data of storing in iteration external information memory module of the present invention are respectively variable node external information and check-node external information, make variable node processing unit and the code check node processing unit can complete parallel alternate treatment two Frames in whole decode procedure, in the situation that decoder work clock is identical, the throughput of its decoding is the twice of conventional decoder, higher than the decoding throughput of improved two frame parallel decoders.The present invention has adopted dynamic address access management method in the access of external information, can in monolithic RAM, realize the storage and inquire of two frame coding data simultaneously, compared with improved two frame parallel decoders, the required BRAM resource of decoder can reduce half.

2. decoder of the present invention and interpretation method realize on the XC4VLX80FPGA of Xilinx company.This decoder is 5/6 based on code check, the QC-LDPC code that code length is 2304, and decoding algorithm is normalization minimum-sum algorithm, Fig. 8 is the decoding performance of this QC-LDPC code under awgn channel, BPSK modulation condition.

Traditional decoder, improved two frame parallel decoders and low memory space high speed decoder of the present invention on ISE10.1 platform to realize result data as shown in the table.

The result that realizes on table 1Xilinx FPGAXC4VLX80 is added up

As seen from Table 1, the decoding throughput of low memory space high speed decoder of the present invention is 190Mbps, approach the twice of conventional decoder throughput, the throughput of more improved two frame parallel decoders is slightly high, decoder for decoding throughput of the present invention does not reach the twice of conventional decoder completely, is because the operation clock frequency of this decoder is lower slightly compared with conventional decoder.On the usage quantity of hardware resource, the required Slice resource of decoder of the present invention is slightly high compared with conventional decoder, substantially suitable with improved two frame parallel decoders, the required RAM resource of decoder of the present invention is identical with conventional decoder, is the half of the RAM resource of improved two frame parallel decoders.

The present invention's known technology that detailed description is not this area.

Claims (2)

1. the low memory space high speed QC-LDPC code decoder based on FPGA, comprising:

Variable node computing module VNU, upgrades and calculates for the variable node external information to decoding, wherein comprises n variable node computing unit VNU _j, 1≤j≤n, the row piecemeal quantity that n is basic matrix;

Check node calculation module CNU, upgrades and calculates for the check-node external information to decoding, wherein comprises m check node calculation unit CNU _i, 1≤i≤m, the row piecemeal quantity that m is basic matrix;

Whether check equations computing module PCU is legal-code for verification decode results;

Channel initial information memory module RAM_F, for the channel likelihood ratio information of storing received, wherein comprises n block RAM memory block F _j, 1≤j≤n;

Iteration external information memory module RAM_M, the iteration external information of mutually transmitting for storing iterative decoding process variable node and check-node, wherein comprises m × n block RAM memory block M _i,j, 1≤i≤m, 1≤j≤n;

Decoding code word memory module RAM_C, the code word result obtaining for storing decoding;

It is characterized in that:

Every block RAM in tri-modules of described RAM_F, RAM_M and RAM_C is all stored two different frame coding data, be that the two frame coding data of storing in iteration external information memory module RAM_M are external information initial value, wherein the initial external information of the first frame data storage is check-node external information, its value is full 0, the initial external information of the second frame data storage is variable node external information, the likelihood ratio that its value receives for channel; The decoding data of storing in channel initial information memory module RAM_F is that two different frame channels receive likelihood ratio; The decoding data of storing in decoding code word memory module RAM_C is two different frame coding court verdicts;

Described every memory block F _jin contain two read ports, these two read ports all with check node calculation unit CNU _ibe connected, be responsible for respectively reading of the different channel initial information of two frames;

Described every memory block M _i,jin contain two reading-writing port, its read-write mode is " write-after-read pattern ", each reading-writing port all with variable node computing unit VNU _jwith check node calculation unit CNU _ibe connected, the each read-write of being responsible for a frame iteration external information of each port.

2. the low memory space high speed QC-LDPC code coding method based on FPGA, comprises the steps:

1) initialization: the each memory block F that the two frame channel likelihood ratio information that receive is deposited in to channel initial information memory module RAM_F according to the row piecemeal segmentation of check matrix H _jin, the address realm of two frame data is respectively 0～z-1 and z～2z-1, F _jfor storing the memory block of j row syndrome matrix channel initial information in RAM_F, z is the dimension of syndrome matrix; The first frame external information in iteration external information memory module RAM_M is initialized as to complete zero, the second frame external information and is initialized as channel reception likelihood ratio information; Iterations iter is initialized as 0 time;

2) check-node of the variable node to the first frame data and the second frame data upgrades:

2a) the each variable node computing unit VNU in variable node computing module _jupgrade one by one the M being attached thereto with row order _i,jin z external information of the first frame:

2a1) by VNU _jrespectively from M _i,jand F _jin read required external information and the channel likelihood ratio information calculated of upgrading; M _i,jin z external information initial storage address of the first frame data be respectively 0～z-1, each external information upgrade after its memory address will change, wherein VNU _jupgrade the variable node computing unit calculating, M for carrying out j row variable node in VNU _i,jfor storing the memory block of the capable j row of i syndrome matrix external information in RAM_M;

2a2) by VNU _jcarry out the renewal calculating of variable node according to the external information of reading and channel likelihood ratio information, and complete the decoding bit decision of this node;

2a3) by VNU _jthe extrinsic information data that renewal is calculated and decoding decision bits write respectively M _i,jin decoding code word memory module RAM_C, if the external information of this variable node is at M _i,jin the address of reading be d _v, writing address is set to (d _v+ L _v) mod z, L _vvNU _jan extrinsic information data is carried out to variable node and upgrade the streamline length of calculating, symbol mod represents modulo operation;

2b) the each check node calculation unit CNU in check node calculation module _iupgrade one by one with row order the M being attached thereto _i,jin z external information of the second frame:

2b1) by CNU _ifrom M _i,jin read to upgrade and calculate required external information; The z of the second frame data external information initial storage address is respectively z～2z-1, and after each external information renewal, its memory address will change, wherein CNU _iupgrade for carrying out the capable check-node of i in CNU the check node calculation unit calculating;

2b2) by CNU _icarry out the renewal of variable node calculates according to the external information of reading;

2b3) by CNU _ithe external information that renewal is calculated is written back to M _i,jin; If the address of reading of check-node external information is d _h, writing address is set to (d _h+ L _h) mod z, L _hthat CNU carries out to an extrinsic information data streamline length that check-node renewal is calculated;

3) variable node of the check-node to the first frame data and the second frame data upgrades:

3a) the each check node calculation unit CNU in check node calculation module _iupgrade one by one with row order the M being attached thereto _i,jin z external information of the first frame:

3a1) by CNU _ifrom M _i,jin read to upgrade and calculate required external information;

3a2) by CNU _icarry out the renewal of variable node calculates according to the external information of reading;

3a3) by CNU _ithe external information that renewal is calculated is written back to M _i,jin; If the address of reading of check-node external information is d _h, writing address is set to (d _h+ L _h) mod z, L _hthat CNU carries out to an extrinsic information data streamline length that check-node renewal is calculated;

3b) the each variable node computing unit VNU in variable node computing module _jupgrade one by one the M being attached thereto with row order _i,jin z external information of the second frame:

3b1) by VNU _jrespectively from M _i,jand F _jin read required external information and the channel likelihood ratio information calculated of upgrading;

3b2) by VNU _jcarry out the renewal calculating of variable node according to the external information of reading and channel likelihood ratio information, and complete the decoding bit decision of this node;

3b3) by VNU _jthe extrinsic information data that renewal is calculated and decoding decision bits write respectively M _i,jin RAM_C, if the external information of this variable node is at M _i,jin the address of reading be d _v, writing address is set to (d _v+ L _v) mod z, L _vthat VNU carries out to an extrinsic information data streamline length that variable node renewal is calculated;

4) iterations iter is added to 1, calculate the syndrome vector s of the first frame coding result ₁syndrome vector s with the second frame coding result ₂if, s ₁=s ₂=0 or iter equal maximum iteration time MAX_ITER, execution step 5), otherwise forward step 2 to) proceed iterative decoding calculate;

5) from decoding code word memory module RAM_C, reading respectively two frame coding court verdicts exports as decode results.

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