CN108494410A - Interpretation method, device, equipment and medium - Google Patents
Interpretation method, device, equipment and medium Download PDFInfo
- Publication number
- CN108494410A CN108494410A CN201810276823.5A CN201810276823A CN108494410A CN 108494410 A CN108494410 A CN 108494410A CN 201810276823 A CN201810276823 A CN 201810276823A CN 108494410 A CN108494410 A CN 108494410A
- Authority
- CN
- China
- Prior art keywords
- iterative process
- values
- llr
- total
- last
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
Abstract
An embodiment of the present invention provides a kind of interpretation method, device, equipment and media.This method includes：In first time iterative process, it is based on log-likelihood ratio initial value LLR_INIT, obtains the V2C values of first time iterative process；The V2C values of first time iterative process are cached, and discharge the memory space shared by the LLR_INIT；In each secondary iterative process after first time iterative process, based on the V2C values cached in last iterative process, the log-likelihood ratio total value LLR_TOTAL of current iteration process is obtained；According to the LLR_TOTAL of current iteration process, this decoding result is obtained.
Description
Technical field
The present invention relates to technical field of data processing more particularly to a kind of interpretation method, device, equipment and media.
Background technology
Low-density checksum (Low-Density Parity-Check, LDPC) code has excellent decoding performance, energy
Shannon limit is approached under a variety of channels, has been widely used in all kinds of digital communication systems and storage system.
In the various interpretation methods of LDPC code at present using it is relatively broad be Layered Min_Sum interpretation methods, it
If the check matrix of LDPC code is divided into dried layer (layer), iterated to calculate using Min_Sum interpretation methods between each layer.
However, Layered Min_Sum interpretation methods must all use LLR_INIT in each iterative process, (logarithm is seemingly
So than initial value), thus the register for caching LLR_INIT must wait until that decoding is completed (to reach maximum iteration or be decoded into
Work() it can discharge later, delay the input of next frame data, to which the throughput of ldpc code decoder can be influenced.
Invention content
An embodiment of the present invention provides a kind of interpretation method, device, equipment and media, to improve gulping down for ldpc code decoder
Spit rate.
In a first aspect, an embodiment of the present invention provides a kind of interpretation method, it is applied to low-density check ldpc code decoder,
The method includes：
In first time iterative process, it is based on log-likelihood ratio initial value LLR_INIT, obtains first time iterative process
V2C values；
The V2C values of first time iterative process are cached, and discharge the memory space shared by the LLR_INIT；
In each secondary iterative process after first time iterative process, based on the V2C values cached in last iterative process,
Obtain the log-likelihood ratio total value LLR_TOTAL of current iteration process；
According to the LLR_TOTAL of current iteration process, this decoding result is obtained.
Optionally, the method further includes：
In each secondary iterative process after the first iteration, the LLR_TOTAL of last iterative process is obtained；
Offset between this layer that the last layer being directed to according to last iterative process and current iteration process are directed to is right
The LLR_TOTAL of last iterative process is shifted；
C2V values progress subtraction operation to LLR_TOTAL and last iterative process after displacement, obtains and caches this
The V2C values of iterative process.
Optionally, the method further includes：
The minimum value of the V2C values cached in last iterative process is assigned to the C2V values of current iteration process；
Based on the V2C values cached in last iterative process, the LLR_TOTAL of current iteration process is obtained, including：
Add operation is carried out to the V2C values and the C2V values of current iteration process that are cached in last iterative process, obtains this
The LLR_TOTAL of secondary iterative process.
Optionally, it is based on LLR_INIT, obtains the V2C values of first time iterative process, including：
LLR_INIT is assigned to the V2C values of first time iterative process；
The method further includes：
The minimum value of the V2C values of first time iterative process is assigned to the C2V values of first time iterative process；
Add operation is carried out to the V2C values and the C2V values of first time iterative process that are cached in first time iterative process, is obtained
The LLR_TOTAL of first time iterative process.
Second aspect, an embodiment of the present invention provides a kind of code translators, are applied to low-density check ldpc code decoder,
Described device includes：
First obtains module, is configured as in first time iterative process, is based on log-likelihood ratio initial value LLR_INIT,
Obtain the V2C values of first time iterative process；
Memory management module, is configured as the V2C values of caching first time iterative process, and discharges shared by the LLR_INIT
Memory space；
Second obtains module, is configured as in each secondary iterative process after first time iterative process, based on the last time
The V2C values cached in iterative process obtain the log-likelihood ratio total value LLR_TOTAL of current iteration process；
Third obtains module, is configured as the LLR_TOTAL according to current iteration process, obtains this decoding result.
Optionally, described device further includes：
Module is obtained, is configured as in each secondary iterative process after the first iteration, last iterative process is obtained
LLR_TOTAL；
Shift module is configured as the sheet that the last layer being directed to according to last iterative process is directed to current iteration process
Offset between layer, shifts the LLR_TOTAL of last iterative process；
Subtraction operation module is configured as subtracting the C2V values of LLR_TOTAL and last time iterative process after displacement
Method operates, and obtains and cache the V2C values of current iteration process.
Optionally, described device further includes：
First assignment module is configured as the minimum value of the V2C values cached in last iterative process being assigned to this
The C2V values of iterative process；
Second, which obtains module, includes：
Submodule is obtained, the C2V values to the V2C values and current iteration process that are cached in last iterative process are configured as
Add operation is carried out, the LLR_TOTAL of current iteration process is obtained.
Optionally, it first obtains module and includes：
Assignment submodule is configured as LLR_INIT being assigned to the V2C values of first time iterative process；
Described device further includes：
Second assignment module is configured as the minimum value of the V2C values of first time iterative process being assigned to first time iteration
The C2V values of process；
Add operation module is configured as the V2C values to being cached in first time iterative process and first time iterative process
C2V values carry out add operation, obtain the LLR_TOTAL of first time iterative process.
The third aspect, an embodiment of the present invention provides a kind of decoding equipments, including：It is at least one processor, at least one
Memory and computer program instructions stored in memory are realized such as when computer program instructions are executed by processor
The method of first aspect in the above embodiment.
Fourth aspect, an embodiment of the present invention provides a kind of computer readable storage mediums, are stored thereon with computer journey
Sequence instructs, and the method such as first aspect in the above embodiment is realized when computer program instructions are executed by processor.
Interpretation method, device, equipment and medium provided in an embodiment of the present invention, centered on variable node, to variable section
The V2C values of point carry out caching for the iterative calculation between layer, and C2V values are intermediate quantities.LLR_ in first time iterates to calculate
INIT is included in the V2C values of first time iterative process, in subsequent iterative process, without using LLR_INIT, is only existed
First time iterative process can use LLR_INIT, thus the register of caching LLR_INIT can be allowed just to release after the first iteration
It puts, it is spare so as to the data that receive next frame, data transmission efficiency is improved, handling up for ldpc code decoder is also improved
Rate.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, will make below to required in the embodiment of the present invention
Attached drawing is briefly described, for those of ordinary skill in the art, without creative efforts, also
It can be obtain other attached drawings according to these attached drawings.
Fig. 1 is the flow chart of interpretation method provided in an embodiment of the present invention.
Fig. 2 is the time diagram using Layered Min_Sum interpretation methods in the related technology.
Fig. 3 is the time diagram of the interpretation method provided using the embodiment of the present disclosure.
Fig. 4 is the schematic diagram of code translator provided in an embodiment of the present invention.
Fig. 5 is the schematic diagram of decoding equipment provided in an embodiment of the present invention.
Specific implementation mode
The feature and exemplary embodiment of various aspects of the invention is described more fully below, in order to make the mesh of the present invention
, technical solution and advantage be more clearly understood, with reference to the accompanying drawings and embodiments, the present invention is further retouched in detail
It states.It should be understood that specific embodiment described herein is only configured to explain the present invention, it is not configured as limiting the present invention.
To those skilled in the art, the present invention can be real in the case of some details in not needing these details
It applies.Below to the description of embodiment just for the sake of by showing that the example of the present invention is better understood from the present invention to provide.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence " including ... ", it is not excluded that including
There is also other identical elements in the process, method, article or equipment of the element.
Interpretation method provided in an embodiment of the present invention is more fully understood for those skilled in the art, to the embodiment of the present invention
Before the interpretation method of offer illustrates, Layered Min_Sum interpretation methods in the related technology are illustrated first.
Layered Min_Sum interpretation methods in the related technology include the following steps：
1) V2C=LLR_TOTAL-C2V_OLD；
2) C2V_NEW=MIN (V2C)；
3) LLR_TOTAL=V2C+C2V_NEW=LLR_INIT+C2V_ALL
From above-mentioned steps it is found that using Layered Min_Sum interpretation methods in the related technology, in being with check-node
The heart caches the C2V values of all check-nodes, and for the iterative calculation between layer, V2C values are intermediate quantities.Each iteration
LLR_TOTAL (needing to use LLR_TOTAL=LLR_INIT+C2V_ALL) all must be obtained using LLR_INIT.It is thus slow
Depositing the register of LLR_INIT must wait until that decoding is completed to discharge after (reaching maximum iteration or successfully decoded),
The input of next frame data is delayed, to which the throughput of ldpc code decoder can be influenced.
To improve the throughput of ldpc code decoder, an embodiment of the present invention provides a kind of interpretation methods.Fig. 1 is the present invention
The flow chart for the interpretation method that embodiment provides, as shown in Figure 1, this approach includes the following steps：
Step S11：In first time iterative process, it is based on log-likelihood ratio initial value LLR_INIT, obtains changing for the first time
For the V2C values of process；
Step S12：The V2C values of first time iterative process are cached, and discharge the memory space shared by the LLR_INIT；
Step S13：In each secondary iterative process after first time iterative process, based on being cached in last iterative process
V2C values, obtain the log-likelihood ratio total value LLR_TOTAL of current iteration process；
Step S14：According to the LLR_TOTAL of current iteration process, this decoding result is obtained.
Different from being cached in the related technology to the C2V values of all check-nodes, use is provided in an embodiment of the present invention
Interpretation method carries out caching for the iterative calculation layer, C2V centered on variable node between the V2C values of variable node
Value is intermediate quantity.LLR_INIT is included in the V2C values of first time iterative process in first time iterates to calculate, subsequent
In iterative process, without using LLR_INIT, LLR_INIT only can be used in first time iterative process, thus can allow caching
The register of LLR_INIT just discharges after the first iteration, spare so as to the data that receive next frame, improves number
According to efficiency of transmission, the throughput of ldpc code decoder is also improved.
Fig. 2 is the time diagram using Layered Min_Sum interpretation methods in the related technology.
Fig. 3 is the time diagram of the interpretation method provided using the embodiment of the present disclosure.Comparison diagram 2 and Fig. 3 can be seen that
Using Layered Min_Sum interpretation methods in the related technology, need after currently decoding and terminating, data input
Allow can be just raised；The interpretation method provided using the embodiment of the present disclosure, after the completion of first time iteration, data
Input allow can be raised, and the inflow of data flow is advanced by, and improve the handling capacity of entire ldpc code decoder.It is translating
During the realization of code device, the data input buffer of decoder periphery can restore within the very short time after starting decoding
Allow states.
In one embodiment, it is based on LLR_INIT, obtains the V2C values of first time iterative process, including：
LLR_INIT is assigned to the V2C values of first time iterative process；
The method further includes：
The minimum value of the V2C values of first time iterative process is assigned to the C2V values of first time iterative process；
Add operation is carried out to the V2C values and the C2V values of first time iterative process that are cached in first time iterative process, is obtained
The LLR_TOTAL of first time iterative process.
In the embodiment of the present invention, LLR_INIT is assigned to V2C in the initialization of first time iteration, later this information
It is embodied in V2C always, subsequent iterative process is no longer needed for input LLR_INIT.Obtaining first time iterative process
After V2C values, above-mentioned steps 2 are executed) and step 3), add operation is carried out, the LLR_TOTAL of first time iterative process is obtained.
In one embodiment, the method further includes：
The minimum value of the V2C values cached in last iterative process is assigned to the C2V values of current iteration process；
Based on the V2C values cached in last iterative process, the LLR_TOTAL of current iteration process is obtained, including：
Add operation is carried out to the V2C values and the C2V values of current iteration process that are cached in last iterative process, obtains this
The LLR_TOTAL of secondary iterative process.
In each secondary iterative process after the first iteration, the LLR_TOTAL of current iteration process is obtained, is equally held
Row above-mentioned steps 2) and step 3), add operation is carried out, the LLR_TOTAL of current iteration process is obtained.
For the LLR_TOTAL of each iterative process, judge whether it is successfully decoded, if successfully decoded or reached maximum
Iterations then export this decoding result.
In the embodiment of the present invention, execute above-mentioned steps 2) and the premise of step 3) obtain and cache current iteration process
V2C values.In one embodiment, the V2C values of current iteration process are obtained and cache, including：
In each secondary iterative process after the first iteration, the LLR_TOTAL of last iterative process is obtained；
Offset between this layer that the last layer being directed to according to last iterative process and current iteration process are directed to is right
The LLR_TOTAL of last iterative process is shifted；
C2V values progress subtraction operation to LLR_TOTAL and last iterative process after displacement, obtains and caches this
The V2C values of iterative process.
Since proposition of the embodiment of the present invention caches the value of V2C, so needing to calculate upper the one of current iteration process
The LLR_TOTAL of secondary iterative process is spare.
When current iteration process is second of iterative process, last iterative process is first time iterative process, is obtained
The method of the LLR_TOTAL of first time iterative process is described above.It is that N, (N is big to third time in current iteration process
In 3 integer) secondary iterative process when, last iterative process is second to the N-1 time iterative process, is obtained for the second time to the
The LLR_TOTAL of each iterative process in N-1 iterative process is equally to execute above-mentioned steps 2) and step 3), carry out addition
Operation obtains second of LLR_TOTAL to the N-1 times iterative process.
Since there is offsets between different layer, so needing to use Shifting.Obtaining upper primary iteration
Between this layer that the LLR_TOTAL of process, the last layer being directed to according to last iterative process and current iteration process are directed to
Offset shifts the LLR_TOTAL of last iterative process, the LLR_TOTAL after being shifted.After obtaining displacement
LLR_TOTAL after, execute above-mentioned steps 1), to after displacement LLR_TOTAL and the C2V values of last iterative process carry out
Subtraction operates, and obtains and cache the V2C values of current iteration process.
It is found that adding (step 1) to be operated for subtraction afterwards different from first subtracting in the related technology, step 3) is process from the above analysis
Add operation) computation sequence, interpretation method provided in an embodiment of the present invention is first carried out using the computation sequence subtracted afterwards is first added
Add operation in step 2) and step 3), the LLR_TOTAL for obtaining last iterative process is spare, then executes in step 1)
Subtraction operation, then shift, displacement after execute step 1) in subtraction operation, obtain the V2C values of current iteration process, after
The continuous add operation executed in step 2) and step 3) obtains current iteration using formula LLR_TOTAL=V2C+C2V_NEW
The LLR_TOTAL of process.
Based on same inventive concept, the embodiment of the present invention also provides a kind of code translator, is applied to low-density check LDPC
Code decoder.Fig. 4 is the schematic diagram of code translator provided in an embodiment of the present invention.As shown in figure 4, the device 200 includes：
First obtains module 201, is configured as in first time iterative process, is based on log-likelihood ratio initial value LLR_
INIT obtains the V2C values of first time iterative process；
Memory management module 202, is configured as the V2C values of caching first time iterative process, and discharges the LLR_INIT
Shared memory space；
Second obtains module 203, is configured as in each secondary iterative process after first time iterative process, is based on upper one
The V2C values cached in secondary iterative process obtain the log-likelihood ratio total value LLR_TOTAL of current iteration process；
Third obtains module 204, is configured as the LLR_TOTAL according to current iteration process, obtains this decoding result.
Optionally, described device further includes：
Module is obtained, is configured as in each secondary iterative process after the first iteration, last iterative process is obtained
LLR_TOTAL；
Shift module is configured as the sheet that the last layer being directed to according to last iterative process is directed to current iteration process
Offset between layer, shifts the LLR_TOTAL of last iterative process；
Subtraction operation module is configured as subtracting the C2V values of LLR_TOTAL and last time iterative process after displacement
Method operates, and obtains and cache the V2C values of current iteration process.
Optionally, described device further includes：
First assignment module is configured as the minimum value of the V2C values cached in last iterative process being assigned to this
The C2V values of iterative process；
Second, which obtains module, includes：
Submodule is obtained, the C2V values to the V2C values and current iteration process that are cached in last iterative process are configured as
Add operation is carried out, the LLR_TOTAL of current iteration process is obtained.
Optionally, it first obtains module and includes：
Assignment submodule is configured as LLR_INIT being assigned to the V2C values of first time iterative process；
Described device further includes：
Second assignment module is configured as the minimum value of the V2C values of first time iterative process being assigned to first time iteration
The C2V values of process；
Add operation module is configured as the V2C values to being cached in first time iterative process and first time iterative process
C2V values carry out add operation, obtain the LLR_TOTAL of first time iterative process.
An embodiment of the present invention provides a kind of decoding equipments, including：At least one processor, at least one processor and
Computer program instructions stored in memory realize such as above-mentioned embodiment party when computer program instructions are executed by processor
Interpretation method in formula.
An embodiment of the present invention provides a kind of computer readable storage mediums, are stored thereon with computer program instructions, when
It is realized such as the interpretation method in the above embodiment when computer program instructions are executed by processor.
It can be realized by decoding equipment in conjunction with the interpretation method of Fig. 1 embodiment of the present invention described.Fig. 5 shows this hair
The hardware architecture diagram for the decoding equipment that bright embodiment provides.
Decoding equipment may include processor 301 and be stored with the memory 302 of computer program instructions.
Specifically, above-mentioned processor 301 may include central processing unit (CPU) or specific integrated circuit
(Application Specific Integrated Circuit, ASIC), or may be configured to implement implementation of the present invention
One or more integrated circuits of example.
Memory 302 may include the mass storage for data or instruction.For example unrestricted, memory
302 may include hard disk drive (Hard Disk Drive, HDD), floppy disk, flash memory, CD, magneto-optic disk, tape or logical
With the combination of universal serial bus (Universal Serial Bus, USB) driver or two or more the above.It is closing
In the case of suitable, memory 302 may include the medium of removable or non-removable (or fixed).In a suitable case, it stores
Device 302 can be inside or outside data processing equipment.In a particular embodiment, memory 302 is nonvolatile solid state storage
Device.In a particular embodiment, memory 302 includes read-only memory (ROM).In a suitable case, which can be mask
The ROM of programming, programming ROM (PROM), erasable PROM (EPROM), electric erasable PROM (EEPROM), electrically-alterable ROM
(EAROM) or the combination of flash memory or two or more the above.
Processor 301 is by reading and executing the computer program instructions stored in memory 302, to realize above-mentioned implementation
Any one interpretation method in example.
In one example, decoding equipment may also include communication interface 303 and bus 310.Wherein, as shown in figure 5, processing
Device 301, memory 302, communication interface 303 are connected by bus 310 and complete mutual communication.
Communication interface 303 is mainly used for realizing in the embodiment of the present invention between each module, device, unit and/or equipment
Communication.
Bus 310 includes hardware, software or both, and the component of decoding equipment is coupled to each other together.For example and
It is unrestricted, bus may include accelerated graphics port (AGP) or other graphics bus, enhancing Industry Standard Architecture (EISA) bus,
Front side bus (FSB), super transmission (HT) interconnection, the interconnection of Industry Standard Architecture (ISA) bus, infinite bandwidth, low pin count (LPC)
Bus, memory bus, micro- channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X)
Bus, Serial Advanced Technology Attachment (SATA) bus, Video Electronics Standards Association part (VLB) bus or other suitable buses
Or the combination of two or more the above.In a suitable case, bus 310 may include one or more buses.To the greatest extent
Specific bus has been described and illustrated in the pipe embodiment of the present invention, but the present invention considers any suitable bus or interconnection.
In addition, in conjunction with the interpretation method in above-described embodiment, the embodiment of the present invention can provide a kind of computer-readable storage
Medium is realized.It is stored with computer program instructions on the computer readable storage medium；The computer program instructions are handled
Device realizes any one interpretation method in above-described embodiment when executing.
It should be clear that the invention is not limited in specific configuration described above and shown in figure and processing.
For brevity, it is omitted here the detailed description to known method.In the above-described embodiments, several tools have been described and illustrated
The step of body, is as example.But procedure of the invention is not limited to described and illustrated specific steps, this field
Technical staff can be variously modified, modification and addition after the spirit for understanding the present invention, or suitable between changing the step
Sequence.
Functional block shown in structures described above block diagram can be implemented as hardware, software, firmware or their group
It closes.When realizing in hardware, it may, for example, be electronic circuit, application-specific integrated circuit (ASIC), firmware appropriate, insert
Part, function card etc..When being realized with software mode, element of the invention is used to execute program or the generation of required task
Code section.Either code segment can be stored in machine readable media program or the data-signal by being carried in carrier wave is passing
Defeated medium or communication links are sent." machine readable media " may include any medium for capableing of storage or transmission information.
The example of machine readable media includes electronic circuit, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), soft
Disk, CD-ROM, CD, hard disk, fiber medium, radio frequency (RF) link, etc..Code segment can be via such as internet, inline
The computer network of net etc. is downloaded.
It should also be noted that, the exemplary embodiment referred in the present invention, is retouched based on a series of step or device
State certain methods or system.But the present invention is not limited to the sequence of above-mentioned steps, that is to say, that can be according in embodiment
The sequence referred to executes step, may also be distinct from that the sequence in embodiment or several steps are performed simultaneously.
The above description is merely a specific embodiment, it is apparent to those skilled in the art that,
For convenience of description and succinctly, the system, module of foregoing description and the specific work process of unit can refer to preceding method
Corresponding process in embodiment, details are not described herein.It should be understood that scope of protection of the present invention is not limited thereto, it is any to be familiar with
Those skilled in the art in the technical scope disclosed by the present invention, can readily occur in various equivalent modifications or substitutions,
These modifications or substitutions should be covered by the protection scope of the present invention.
Claims (10)
1. a kind of interpretation method, which is characterized in that it is applied to low-density check ldpc code decoder, the method includes：
In first time iterative process, it is based on log-likelihood ratio initial value LLR_INIT, obtains the V2C of first time iterative process
Value；
The V2C values of first time iterative process are cached, and discharge the memory space shared by the LLR_INIT；
In each secondary iterative process after first time iterative process, based on the V2C values cached in last iterative process, obtain
The log-likelihood ratio total value LLR_TOTAL of current iteration process；
According to the LLR_TOTAL of current iteration process, this decoding result is obtained.
2. according to the method described in claim 1, it is characterized in that, the method further includes：
In each secondary iterative process after the first iteration, the LLR_TOTAL of last iterative process is obtained；
Offset between this layer that the last layer being directed to according to last iterative process and current iteration process are directed to, to upper one
The LLR_TOTAL of secondary iterative process is shifted；
C2V values progress subtraction operation to LLR_TOTAL and last iterative process after displacement, obtains and caches current iteration
The V2C values of process.
3. according to the method described in claim 1, it is characterized in that, the method further includes：
The minimum value of the V2C values cached in last iterative process is assigned to the C2V values of current iteration process；
Based on the V2C values cached in last iterative process, the LLR_TOTAL of current iteration process is obtained, including：
Add operation is carried out to the V2C values and the C2V values of current iteration process that are cached in last iterative process, this is obtained and changes
For the LLR_TOTAL of process.
4. according to the method described in claim 1, it is characterized in that, based on LLR_INIT, the V2C of first time iterative process is obtained
Value, including：
LLR_INIT is assigned to the V2C values of first time iterative process；
The method further includes：
The minimum value of the V2C values of first time iterative process is assigned to the C2V values of first time iterative process；
Add operation is carried out to the V2C values and the C2V values of first time iterative process that are cached in first time iterative process, obtains first
The LLR_TOTAL of secondary iterative process.
5. a kind of code translator, which is characterized in that be applied to low-density check ldpc code decoder, described device includes：
First obtains module, is configured as in first time iterative process, is based on log-likelihood ratio initial value LLR_INIT, obtains
The V2C values of first time iterative process；
Memory management module, is configured as the V2C values of caching first time iterative process, and discharges depositing shared by the LLR_INIT
Store up space；
Second obtains module, is configured as in each secondary iterative process after first time iterative process, based on last iteration
The V2C values cached in the process obtain the log-likelihood ratio total value LLR_TOTAL of current iteration process；
Third obtains module, is configured as the LLR_TOTAL according to current iteration process, obtains this decoding result.
6. device according to claim 5, which is characterized in that described device further includes：
Module is obtained, is configured as in each secondary iterative process after the first iteration, last iterative process is obtained
LLR_TOTAL；
Shift module, be configured as this layer that the last layer being directed to according to last iterative process and current iteration process are directed to it
Between offset, the LLR_TOTAL of last iterative process is shifted；
Subtraction operation module is configured as the C2V values progress subtraction behaviour to LLR_TOTAL and last iterative process after displacement
Make, obtains and cache the V2C values of current iteration process.
7. device according to claim 5, which is characterized in that described device further includes：
First assignment module is configured as the minimum value of the V2C values cached in last iterative process being assigned to current iteration
The C2V values of process；
Second, which obtains module, includes：
Submodule is obtained, V2C values and the C2V values of current iteration process to being cached in last iterative process is configured as and carries out
Add operation obtains the LLR_TOTAL of current iteration process.
8. device according to claim 5, which is characterized in that first, which obtains module, includes：
Assignment submodule is configured as LLR_INIT being assigned to the V2C values of first time iterative process；
Described device further includes：
Second assignment module is configured as the minimum value of the V2C values of first time iterative process being assigned to first time iterative process
C2V values；
Add operation module is configured as the C2V values to the V2C values and first time iterative process that are cached in first time iterative process
Add operation is carried out, the LLR_TOTAL of first time iterative process is obtained.
9. a kind of decoding equipment, which is characterized in that including：At least one processor, at least one processor and it is stored in institute
The computer program instructions in memory are stated, are realized when the computer program instructions are executed by the processor as right is wanted
Seek the method described in any one of 1-4.
10. a kind of computer readable storage medium, is stored thereon with computer program instructions, which is characterized in that when the calculating
The method as described in any one of claim 1-4 is realized when machine program instruction is executed by processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810276823.5A CN108494410A (en) | 2018-03-30 | 2018-03-30 | Interpretation method, device, equipment and medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810276823.5A CN108494410A (en) | 2018-03-30 | 2018-03-30 | Interpretation method, device, equipment and medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108494410A true CN108494410A (en) | 2018-09-04 |
Family
ID=63317090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810276823.5A Pending CN108494410A (en) | 2018-03-30 | 2018-03-30 | Interpretation method, device, equipment and medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108494410A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101106381A (en) * | 2007-08-09 | 2008-01-16 | 上海交通大学 | Hierarchical low density check code decoder and decoding processing method |
| CN102394661A (en) * | 2011-11-08 | 2012-03-28 | 北京邮电大学 | LDPC (low density parity check) decoder and decoding method based on layer decoding processing |
| CN102412847A (en) * | 2004-11-23 | 2012-04-11 | 三星电子株式会社 | Method and apparatus for decoding low density parity check code using united node processing |
| CN102594369A (en) * | 2012-02-27 | 2012-07-18 | 西安电子科技大学 | Quasi-cyclic low-density parity check code decoder based on FPGA (field-programmable gate array) and decoding method |
| US20160055057A1 (en) * | 2014-08-25 | 2016-02-25 | Dong-Min Shin | Storage device including error correction decoder and operating method of error correction decoder |
-
2018
- 2018-03-30 CN CN201810276823.5A patent/CN108494410A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412847A (en) * | 2004-11-23 | 2012-04-11 | 三星电子株式会社 | Method and apparatus for decoding low density parity check code using united node processing |
| CN101106381A (en) * | 2007-08-09 | 2008-01-16 | 上海交通大学 | Hierarchical low density check code decoder and decoding processing method |
| CN102394661A (en) * | 2011-11-08 | 2012-03-28 | 北京邮电大学 | LDPC (low density parity check) decoder and decoding method based on layer decoding processing |
| CN102594369A (en) * | 2012-02-27 | 2012-07-18 | 西安电子科技大学 | Quasi-cyclic low-density parity check code decoder based on FPGA (field-programmable gate array) and decoding method |
| US20160055057A1 (en) * | 2014-08-25 | 2016-02-25 | Dong-Min Shin | Storage device including error correction decoder and operating method of error correction decoder |
Non-Patent Citations (2)
| Title |
|---|
| AHMED M. SADEK等: ""Flexible FPGA implementation of Min-Sum decoding algorithm for regular LDPC codes"", 《2016 11TH INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING & SYSTEMS (ICCES)》 * |
| 徐芬: ""LDPC码固定比特位删除译码算法研究及在大容量光通信中的应用"", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2953307B1 (en) | Polar code decoding method and decoder | |
| Yuan et al. | Architecture optimizations for BP polar decoders | |
| CN104124979B (en) | The interpretation method and code translator of polar code | |
| Xu et al. | XJ-BP: Express journey belief propagation decoding for polar codes | |
| Yuan et al. | LLR-based successive-cancellation list decoder for polar codes with multibit decision | |
| EP3639376B1 (en) | Polar decoder with llr-domain computation of f-function and g-function | |
| KR20070039353A (en) | Method for updating check node in low density parity check decoder | |
| US7657819B2 (en) | Method and apparatus for termination of iterative turbo decoding | |
| JP2014099944A (en) | Methods and apparatus for low-density parity check decoding using hardware sharing and serial sum-product architecture | |
| US20180269900A1 (en) | Decoding Method and Decoder for Low-Density Parity-Check Code | |
| CN109802688B (en) | Multilevel LDPC decoding system and method | |
| Delomier et al. | Model-based design of hardware sc polar decoders for fpgas | |
| CN108494410A (en) | Interpretation method, device, equipment and medium | |
| CN109327280B (en) | Segmented coding method and device | |
| CN108270508B (en) | Cyclic redundancy check CRC implementation method, device and network equipment | |
| US11063614B1 (en) | Polar decoder processor | |
| CN104796160A (en) | Decoding method and device | |
| US9590658B1 (en) | High-speed low-power LDPC decoder design | |
| WO2016000197A1 (en) | Decoding method and device | |
| US20140223267A1 (en) | Radix-4 viterbi forward error correction decoding | |
| CN107872231A (en) | LDPC interpretation methods and device | |
| Jeong et al. | Fast multibit decision polar decoder for successive-cancellation list decoding | |
| Lewandowsky et al. | Design and evaluation of information bottleneck LDPC decoders for software defined radios | |
| Lee et al. | A uniformly segmented SC-flip decoder for polar codes with memory reduction methods | |
| CN108886370B (en) | Convolutional LDPC decoding method, device, decoder and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20190808 Address after: 518067 Dongjiaotou Workshop D24/F-02, Houhai Avenue, Shekou Street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: SHENZHEN UNIONMEMORY INFORMATION SYSTEM Co.,Ltd. Address before: 100176 Beijing Daxing District Beijing Economic and Technological Development Zone No. 58 Jinghai Road, No. 5 Building No. 3, No. 305 Applicant before: BEIJING LENOVO SOFTWARE Ltd. |
|
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180904 |