CN106571829B - A kind of high-speed adaptive DVB-S2 ldpc decoder and interpretation method based on FPGA - Google Patents
A kind of high-speed adaptive DVB-S2 ldpc decoder and interpretation method based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6552—DVB-T2
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Abstract
The present invention relates to a kind of high-speed adaptive DVB-S2 ldpc decoder and interpretation method based on FPGA: (1) matrixing, generation left matrix are quasi- cyclic, and right matrix be the new matrix for converting double diagonally (RTS) submatrixs of lower triangle；(2) RAM and the number of iterations are initialized；(3) two parts matrix is respectively completed variable node information update and write back data.(4) check-node information update and write-back, while syndrome vector s is calculated, the number of iterations iter adds 1；(5) if syndrome vector s=0 or reaching maximum number of iterations, (6) are gone to step, otherwise, (3) is gone to step and continues next round iterative processing；(6) decoding decision bits are read, code word is exported.
Description
Technical field
The present invention relates to a kind of adaptive ldpc decoder technologies for meeting DVB-S2 standard, especially a kind of to be based on FPGA
High-speed adaptive DVB-S2 ldpc decoder and interpretation method.
Background technique
European second generation digital satellite television broadcast (DVB-S2) standard provide a kind of high power spectral efficient from
Coded modulation scheme is adapted to, the program is widely used in satellite broadcasting television system.In order to by this height
The adaptive coding and modulating scheme of effect be applied to EES earth exploration satellite, 2013, international space data system Advisory Board
(CCSDS) 131.3-B-1 standard (CCSDS space link protocols over ETSI dvb-s2 standard
CCSDS 131.3-b-1, blue book, march 2013) it gives using DVB-S2 standard and transmits CCSDS transmission frame
Technical solution solves the problem of format compatibility of DVB-S2 and CCSDS.
However, since the peak transfer rate of satellite broadcasting television system only has 135Mbps, and EES earth exploration satellite is most
Big transmission rate is then up to several Gbps, the adaptive compiled code device design side DVB-S2 at this stage based on satellite broadcasting television system
Case and chip are not directly applicable EES earth exploration satellite.DVB-S2 LDPC encoder and decoder with adaptive ability
High-throughput realize the higher adaptive decoding device of technology, especially complexity realization of High Speed technology, be DVB-S2 adaptive
Scheme is answered to apply the key technical problem of required solution on EES earth exploration satellite.
Being applied on EES earth exploration satellite based on the ldpc decoder designing technique of DVB-S2 standard at this stage all has office
It is sex-limited.Wherein, some decoder implementation methods can the different code rate of compatible with DVB-S2 standard, but its rate is unable to satisfy the earth
The requirement of explorer satellite.Such as: document (Van Ying, Dan Bo, Shuangqu Huang, Bo Xiang, Yun Chen,
Xiaoyang Zeng,“A Cost efficient LDPC decoder for DVB-S2,”IEEE 8th
International Conference on ASIC, 2009.ASICON'09) TDMP algorithm is used, realize DVB-S2 standard code
A length of 64,800 11 kinds of codes, decoding handling capacity are 135Mbps；Document (C.Marchand, L.Conde-Canencia and
E.Boutillon,“High-speed conflict-free layered LDPC decoder for the DVB-S2,-T2
and-C2 standards,”2013 IEEE Workshop on Signal Processing Systems,pp118-123)
Realizing a handling capacity based on FPGA is 200Mbps adaptive decoding device.And other some decoder implementations, although
It can be realized higher decoding throughput, but its design is designed itself just for the matrix of code rate single in standard, is decoded
Device does not have the adaptive ability of code-rate-compatible actually, such as: document (Seok-Min Kim, Chang-Soo Park, and Sun-
Young Hwang,“A Novel Partially Parallel Architecture for High-throughput LDPC
Decoder for DVB-S2, " IEEE Trans.Consumer Electronics, Vol.56, No.2, May 2010) design
One has the module B/CFM of variable node and check-node function simultaneously, and the DVB-S2 ldpc decoder maximum of realization gulps down
The amount of spitting can reach 1020Mbps；Document (Tae Hun Kim, Tae Doo Park, Gun Yeol Park, Hae Chan
Kwon,Ji Won Jung,“High Throughput LDPC Decoder Architecture for DVB-S2,”ICUFN
2013, pp430-434) HSS strategy and simple check-node more new algorithm are used, is realized using the framework for saving storage resource
Obtained cbr (constant bit rate) decoder, handling capacity can be more than 2Gbps.
Summary of the invention
Technology of the invention solves the problems, such as: it is adaptive to overcome the deficiencies of the prior art and provide a kind of high speed based on FPGA
DVB-S2 ldpc decoder and interpretation method are answered, it can not only complete the compatible decoding of various code rate, but also can be realized and handle up greatly
The high-speed coding of rate, and have the characteristics that memory resource utilization rate is high.
The technical solution of the invention is as follows: a kind of high-speed adaptive DVB-S2 ldpc decoder based on FPGA, special
Sign be the decoder include: CTRL control module, components of system as directed external information memory module RAM_M, check-node update and
Check equations computing module CPM, RTS network exchange module, verification external information memory module RAM_C, variable node processing module
VNM, channel information memory module RAMF and output memory module RAM_OUT；
The channel information memory module RAMF, for the channel channel information of storage decoder input port input, by N
A memory is constituted, and N is the column block count of check matrix；It is divided into message part external information memory RAM _ QC and check part
External information memory RAM _ RTS two parts, wherein RAM_QC includes N-q memory RAM, is denoted as Ri, 1≤i≤N-q；RAM_
RTS includes q memory RAM, is denoted as Fi, 1≤i≤q, q are the interval constant that code rate is corresponded in DVB-S2 standard；The RAM_
QC provides the channel information of message part during decoding for VNM, and the RAM_RTS provides the channel of check part for VNM
Information；
The variable node processing module VNM, the update calculating of variable node external information is sentenced with code word during completing decoding
It definitely calculates, it is made of N number of code check node processing unit, is divided into message part variable node processing unit VNU and check part
Variable node processing unit VTU two parts, wherein VNU is N-q, is denoted as VNUi, 1≤i≤N-q, VTU are q, are denoted as VTUi,
1≤i≤q；VNUiFrom the memory R in RAM_QCiThe middle channel information for obtaining message part, while correspondence is obtained from RAM_M
External information, carry out variable node and update to calculate and codeword decision calculates, updated external information and codeword decision result are returned
It writes in RAM_M, and RAM_OUT is written into codeword decision result；VTUiFrom the memory F in RAM_RTSiMiddle acquisition information portion
The channel information divided, while corresponding external information is obtained from RAM_C, it carries out variable node and updates calculating and codeword decision meter
It calculates, updated external information and codeword decision result is written back in RAM_C, and RAM_OUT is written into codeword decision result；
The CPM module is responsible for the syndrome that check-node is updated and verified and is calculated, it is updated single by q check-node
First CNU and q check equations computing unit PCU composition, are denoted as CNU respectivelyiAnd PCUi, 1≤i≤q；CNUiAnd PCUiRespectively from
The external information and codeword decision that acquisition variable node updates in RAM_M and RAM_C are as a result, CNUiSchool is carried out according to external information
Node updates calculating is tested, updated external information is written back to RAM_M and RAM_C, PCUiCompanion is calculated according to codeword decision
CTRL control module is sent into formula vector s, and by syndrome vector s；
The components of system as directed external information memory module RAM_M is responsible for storage message part submatrix H1 tNonzero element pair
The external information answered, for the VNU in VNMiWith the CNU in CPMiExternal information exchange；Each decoding iteration, first VNUiFrom
External information is read in RAM_M, carries out that result is written back to RAM_M after variable node update calculates, then CNUiIt is read from RAM_M
Enter external information, carries out that updated external information is written back to RAM_M after check-node update calculates；
The verification external information memory module RAM_C is responsible for storage check part submatrix H2 tNonzero element it is corresponding
External information, for the VTU in VNMiWith the CNU in CPMiExternal information exchange, by 2q MCiMemory composition, is labeled as MCi,
1≤i≤2q；Each decoding iteration, first VTUiRead in external information from RAM_C, carry out variable node update calculate after will after
As a result it is written back to RAM_C, then CNUiExternal information is read in from RAM_C by RTS network exchange module, carries out check-node more
Updated external information is written back to RAM_C after new calculating；
The RAM_C stores check part submatrix H2 tThe corresponding external information of nonzero element, storage mode is,
H2 tIn each sub-line store nonzero element using the memory that two depth are L, L is cyclic shift length, H2 tIt is corresponding outer
Information needs 2q memory to store, and line number is denoted as s, the corresponding memory of each row be respectively (s=0 | MC1,MC2), (s=
1|MC3,MC4) ..., (s=q-1 | MC2q-1,MC2q)；E [c] [d] indicates H2 tNonzero element, c, 1≤c≤q × L indicate column
Mark, due to H2 tRow weight be 1 or 2, enable d, 0≤d≤1 indicates H2 tD-th of nonzero element.For H2 t, share 2q non-zero entry
Element, respectively (E [0] [0], E [0] [1]), (E [1] [0], E [1] [1]), (E [2] [0], E [2] [1]) ..., (E [q × L-2]
[0], [q × L-2] [1] E), (E [q × L-1] [0]), they respectively correspond the line number 0, q of original matrix, 2q ..., 359q, and 1, q
+1,2q+1,…,359q+1,…,q-1,q+q-1,2q+q-1,…,359q+q-1；
The RTS network exchange module, for solving the problems, such as that CNU and VNU concurrent reading and concurrent writing alignment of data is inconsistent, size
Each memory MC for 2q × 2q, in it and RAM_Ci, 1≤i≤2q connection；2q input/output port is divided into q group, input terminal
Slogan be respectively (2,3), (4,5) ... (2q, 1), the output end slogan being respectively grouped be respectively (1,2), (3,4) ... (2q-1,
2q)；
The CTRL control module is responsible for the coordinated control of decoder each section, and the syndrome sent according to CPM module
Vector s judges that decoder continues loop iteration and is also off；
The output memory module RAM_OUT adjudicates code word for storing the decoding that generates in iterative decoding process, and
It is exported at the end of decoding.
High-speed adaptive DVB-S2 LDPC interpretation method based on FPGA, it is characterized in that steps are as follows:
(1) to original checksums matrix H=[H of LDPC code in DVB-S2 standard1|H2] capable transformation is carried out, obtain new matrix
Ht=[H1 t|H2 t], by converting rear left matrix H1 tIt is a quasi- cyclic submatrix, abbreviation QC matrix, right matrix H2 tIt is one
A row converts the lower double diagonal submatrix of triangle, abbreviation RTS matrix；
The row map function of check matrix is that row sequence is adjusted to 0, q, 2q by row matrix exchange ..., 359q, 1, q+
1,2q+1 ..., 359q+1 ..., q-1, q+q-1 ..., 359q+q-1, wherein q be corresponded in DVB-S2 standard code rate interval it is normal
Number.It is adjusted, the message part H of check matrix H1Become the quasi- cyclic matrix H of q × 45 piecemeal composition1 t, Mei Gefen
Block size is L × L, and L is double diagonal arrangement matrix Hs of cyclic shift length and check part2H is transformed to through space2 t, obtain one
A new row converts lower triangle dual-diagonal matrix.
(2) according to the transformed partitioning of matrix, by the storage of information bit information corresponding to the data frame received to letter
It ceases in memory block RAM_QC, by the storage of corresponding check bit information into verification memory block RAM_RTS, while external information being stored
The content of block RAM _ C and RAM_M is initialized as zero, initializes the number of iterations iter=1；
(3) external information, VNU are read from RAM_C and RAM_Mi, 1≤i≤45-q progress matrix H1 tOutside partial variable node
Information update calculates and codeword decision, VTUi, 1≤i≤q progress matrix H2 tPartial variable node external information updates calculating and code
Word judgement, and result is written back in RAM_C and RAM_M；RAM_OUT is also written in codeword decision result simultaneously, defeated for decoding
Out；
VTUi, it is VTU that 1≤i≤q variable node external information, which updates calculating process,iRespectively from external information memory block
MC(2i) % (2q)And MCT, (2i+1) % (2q)Middle 2p external information of reading and the p channel information of reading from RAM_RTS, it is updated
For information back into identical RAM_RTS storage address, p is the degree of parallelism of design of encoder, and read/write address sequence isL is cyclic shift length；
(4) the updated external information of variable node and codeword decision are read as a result, CNU from RAM_C and RAM_Mi, 1≤i≤
Q carries out the calculating of check-node external information according to extrinsic information data, and result is written back in RAM_C and RAM_M；PCUi, 1≤i
≤ q carries out syndrome vector s according to codeword decision result and calculates；The number of iterations iter adds 1；
The process that check-node updates and syndrome vector calculates is, from memory RAM _ M (n-2) p H1 tSquare
Battle array external information and come from memory MC2s-1,MC2s2p H2 tMatrix external information, while it being sent to CNU, it updates and counts by CNU
After calculation, it is as a result written back to memory RAM _ M and MCt,2s-1,MCt,2sIdentical address in；Meanwhile PCU is carried out according to verification battle array
Corresponding decoding decision bits are read, calculates the check value of each equation, forms syndrome vector s；
(5) if syndrome vector s=0 or the number of iterations iter=MAX_ITER, goes to step (6), MAX_ITER is decoding
The maximum number of iterations of device setting；Otherwise, (3) are gone to step and continue next round iterative processing；
(6) decoding decision bits are read from RAM_OUT, exports code word.
The invention has the following advantages over the prior art:
(1) after carrying out capable transformation to LDPC check matrix first when ldpc decoder of the invention is realized, it is equivalent to decoding
When, the position of institute's solving equations changed but separate equation is constant, so will not influence decoding performance.However, this new row
Transformation matrix HtIt is but given by the quasi- circulation QC submatrix on the left side and the check part submatrix on the right and is realized high-speed adaptive decoding
Device brings convenience.This is because being studied in the high speed decoder document of LDPC at this stage largely about quasi- cyclic
Ldpc decoder, quasi- cycle characteristics can reduce the complexity of memory access, and block characteristic is advantageously implemented part parallel
Decoder.And for check part submatrix H2 t, the present invention only needs the matrix of this structure of primary study to translate in high speed multi code Rate of Chinese character
It is how mutually compatible with the framework of quasi-cyclic matrix when code device design；
(2) framework that ldpc decoder of the present invention uses QC-RTS compatible, using variable node processing unit VNU and VTU
QC submatrix and the corresponding variable node of RTS submatrix are handled using separating, and for code check node processing unit
CNU needs QC submatrix to cooperate to combine with RTS submatrix and handle check-node.Such an approach achieves RTS
Matrix and QC submatrix part are compatible on degree of parallelism, are successfully applied to the characteristic of QC high-speed adaptive design of encoder
The part RTS, to realize high-speed adaptive DVB-S2 ldpc decoder；
(3) part ldpc decoder RTS of the invention is convenient for by using the RAM module of bit wide and the same specification of depth
The multiplexing of storage resource when code-rate-compatible designs, and RTS network exchange module is introduced, successfully avoid each processing unit pair
The access conflict problem of RTS memory；
(4) decoder of the present invention adapts to all code rates of DVB-S2 standard and block length, and this implementation method gulps down
The amount of spitting can meet the needs of not homologous ray according to degree of parallelism flexible modulation, have stronger practicability.And it is adaptive in high-throughput
Should on apparent advantage, can apply to the case where peak transfer rate of EES earth exploration satellite is up to several Gbps.
Technical solution of the present invention in satellite receiver Successful utilization and pass through associated communication system test.
Detailed description of the invention
Fig. 1 is the QC-RTS decoder architecture block diagram for DVB-S2 standard of the invention；
Double diagonal arrangement matrix non-zero distribution diagram of element that Fig. 2 is 36 × 36；
Fig. 3 is q=10, the matrix non-zero distribution diagram of element that the dual-diagonal matrix of L=5 is converted through space；
Fig. 4 is HtThe structure chart of matrix.
Specific embodiment
Using it is proposed by the present invention improve node processing degree of parallelism QC-LDPC decoder and interpretation method, below with
The LDPC code for five code rates that the code length chosen in DVB-S2 standard is 16200 carries out the compatible FPGA realization of High Speed of self-adaption code rate
For come the present invention will be described in detail.
The H-matrix of LDPC code includes two parts in DVB-S2 standard:
H=[H1|H2]
Wherein, H1Size be M × K, H2It is the matrix for the double diagonal arrangements of lower triangle that a size is M × M, such as Fig. 1 institute
Show, Fig. 2 gives the H in the case of a M=362, the point in Fig. 2 indicates nonzero element " 1 ".Matrix H1Row have periodically,
I.e. every q row (the q value of five kinds of code rates is as shown in table 1) obtains lower q row for loopy moving one to the right as one piece of entirety, recycles to the right
Moving 360 times can be obtained check matrix H1。
The corresponding q value of five kinds of code rates that 1. code length of table is 16200
| Code rate | 2/5 | 3/5 | 2/3 | 7/9 | 8/9 |
| q | 27 | 18 | 15 | 10 | 5 |
By doing capable transformation to H, the row of matrix need to only be pressed 0, q, 2q ..., 359q, 1 by when transformation, q+1,2q+1 ...,
359q+1 ..., q-1, q+q-1 ..., the sequential transformations of 359q+q-1.H1It can be transformed to the quasi- circulation knot of q × 45 piecemeal
The matrix H of structure1 t, each piecemeal size is the cyclic shift matrices of a L × L (360 × 360).Corresponding double diagonal arrangements
Matrix H2Also H is transformed to by same row2 t, obtain a new row and convert lower triangle dual-diagonal matrix (referred to as RTS).
Fig. 3 gives q=10, an example of L=5, and the point in Fig. 3 indicates nonzero element " 1 ".
So new row transformation matrix may be expressed as: Ht=[H1 t|H2 t], wherein H2 tIt is the RTS square of a qL × qL
Battle array, and H1 tIt is a QC submatrix, its basic matrix size is q × (45-q), as shown in figure 4,1 element of each of basic matrix
Can by the matrix of L × L, cyclic shift extends to the right, L=360, the row weight d of the check matrix herecWith column weight dvSuch as
Shown in table 3,12 (6) in table 2 indicate that column weight is 12 to have 6.
The row weight d of 2. 5 kinds of code rate LDPC codes of tablecValue and column weight dvValue
| Code rate | H1 tDv | H2 tDv | HtDc |
| 2/5 | 12(6),3(12) | 2(27) | 6(27) |
| 3/5 | 12(9),3(18) | 2(18) | 11(18) |
| 2/3 | 13(3),3(27) | 2(15) | 10(15) |
| 7/9 | 3(35) | 2(10) | 12(3),11(1),13(6) |
| 8/9 | 4(5),3(35) | 2(5) | 27(5) |
Since processing unit occupies most of resource of a large amount of decoder, adaptively translated to effectively design one
Code device, processing unit between different code rates should farthest shared resources.By analytical table 3, at available two kinds
Manage the minimum number of device CNU and VNU.
The case where CNU is used to carry out check-node information, the i.e. update of row information, and row weighs 10,11,12,13 can be designed
It is the CNU of 13 situations for a kind of row weight, so adaptive decoding device needs three kinds of row weights situation { 6 (27), 27 (5), 13 (18) },
I.e. adaptive decoding device needs 27p 6 input, and the CNU of 5p 27 input and 18p 13 input is denoted as CNU-6, CNU- respectively
27 and CNU-13, p is the degree of parallelism being noted above here.Similarly, VNU is used to carry out variable node information, i.e. column information
Update, column weight is that { 12,13 } and { 2,3 } can separately design as the VNU that column weight the is 13 situations and VNU that column weight is 3 situations.Institute
Three kinds of row weights situation { 4 (5), 13 (6), 3 (45) } are needed with decoder, i.e. decoder needs 5p (4+1) inputs, 9p (13+
1) VNU with 45p (3+1) inputs are inputted, are denoted as VNU-4, VNU-13 and VNU-3 respectively.So having obtained processing unit
It is total as shown in table 3.
The quantity of 3. processor unit of table
The external information of QC submatrix and RTS submatrix is respectively stored in memory block RAM_M and memory block MCtIn.
RTS submatrix H is indicated with E [c] [d]2 tNonzero element, c (1≤c≤q × L) indicate column mark, due to H2 tRow
Weight is 1 or 2, and d (0≤d≤1) is enabled to indicate H2 tD-th of nonzero element.For H2 t, share 2q nonzero element, respectively (E
[0][0],E[0][1]),(E[1][0],E[1][1]),(E[2][0],E[2][1]),…,(E[q×L-2][0],E[q×L-
2] [1]), (E [q × L-1] [0]) they respectively correspond original matrix H2Line number 0, q, 2q ..., 359q, 1, q+1,2q+
1,…,359q+1,…,q-1,q+q-1,2q+q-1,…,359q+q-1.In order to more clearly provide RTS submatrix, table 4 is provided
H2 t2q nonzero element.
Nonzero element position in table 4.RTS submatrix
It can be seen that, RTS submatrix is divided into q row block from table 4, and s (0≤s≤q-1) a row block includes accurate
L=360, ground sub-line r (0≤r≤L-1).Each sub-line s stores nonzero element using the memory that two depth are L, institute
2q memory is needed to store with the corresponding external information of RTS submatrix, corresponding memory is defined as MCt,x,(1≤x≤
2q), this 2q memory be respectively (s=0 | MCt,1,MCt,2), (s=1 | MCt,3,MCt,4) ..., (s=q-1 | MCt,2q-1,
MCt,2q)。
This storage mode of RTS can efficiently solve memory access conflict problem, this is because in CNU processing
Stage, CNU need to read two memory blocks, i.e. MC corresponding to each row block st,2s-1,MCt,2s.And in VNU processing stage,
VNU needs to read two memory blocks, i.e. MC corresponding to sT, (2s) % (2q),MCT, (2s+1) % (2q)?.In order to make CNU and VNU
These memories can be alternately read, the RTS network exchange module of a 2q × 2q is introduced, with memory MCt,xIt is corresponding defeated
Inbound port number is (2,3), and (4,5) ... (2q, 1), output end slogan is (1,2), (3,4) ... (2q-1,2q).
The corresponding channel information of RTS submatrix is stored in memory FtIn, from memory MCt,xContent it is found that right with it
The row number answered is respectively 0+y, q+y, 2q+y ..., q × (L-1)+y, here y (0≤y≤q-1), memory FtIt is by the suitable of column
Sequence carries out storage channel information.In VNU processing stage, each memory FtIt needs and two memory MCt,xCarry out data friendship
Mutually.
As shown in Figure 1, adaptive DVB-S2 ldpc decoder of the invention includes 3 kinds of storage units: channel information storage
Unit (RAM_QC, RAM_RTS), external information storage unit (RAM_M, RAM_C) and hard decision storage unit.For the present invention
Decoder architecture, the depth of each memory isIt can guarantee to decode using the depth of twice of information frame data
Device is decoded while receiving channel information, and guarantees that the CNU and VNU alternating data different to two frames decode.Institute
There is memory to be all made of dual-port mode.
Since the columns of different code rate basic matrixs is n, so channel information memory can be multiplexed, n=is needed in total
45 memories store channel information, i.e. n-q RAMF and q Ft。
However, the multiplex mode for external information is more complicated, and in a decoder, external information memory number and basic matrix
Nonzero element it is directly proportional, know from the above, the corresponding basic matrix of multi code Rate of Chinese character QC submatrix has different nonzero elements, enables g
Indicate the number of the nonzero element of multi code Rate of Chinese character QC submatrix basic matrix, gmax=162.In view of RTS submatrix needs 2q MCt
Memory.So adaptive decoding device needs g in totalmax+ 2q=198 memory stores external information.According to analysis above,
The present invention gives amount of memory required for each code rate LDPC code, as shown in table 5, it is seen then that five kinds of code-rate-compatibles
The adaptive ldpc decoder of DVB-S2 needs 198+45=243 block storage in total.
The amount of memory used shared by the every kind of code rate of table 5.
| Code rate | 2/5 | 3/5 | 2/3 | 7/9 | 8/9 |
| RAMF | 18 | 27 | 30 | 35 | 40 |
| Ft | 27 | 18 | 15 | 10 | 5 |
| RAMMC | 108 | 162 | 120 | 105 | 125 |
| MCt | 54 | 36 | 30 | 20 | 10 |
| Channel information | 45 | 45 | 45 | 45 | 45 |
| External information | 162 | 198 | 150 | 125 | 135 |
| It amounts to | 207 | 243 | 195 | 170 | 180 |
For this QC-RTS decoder architecture proposed by the present invention, in Xilinx Virtex7 xc7vx485t FPGA
On realize the adaptive ldpc decoder of DVB-S2 of five kinds of code-rate-compatibles, comprehensive and placement-and-routing uses Xilinx
Vivado 2015.1.When realizing, using 6 bit quantizations.
Decoder of the invention can be configured as any degree of parallelism, it is contemplated that the money for this block FPGA that the present invention uses
The case where source, selection degree of parallelism p=5.Therefore, as shown in table 4, it is respectively necessary for 27p=135 CNU-6,5p=25 CNU-27
With 18p=90 CNU-13 and 5p=25 VNU-4,9p=45 VNU-13 and 45p=90 VNU-3.
It can be seen that, channel information and external information need 243 pieces of dual-port 18kbits BRAM in total, sentence firmly from table 5
Certainly the size of memory block RAMC isNeed to occupy the both-end of 7 pieces of 18kbits
Mouth BRAM, so this adaptive decoding device needs to occupy 250 pieces of dual-port BRAM.For Virtex7FPGA, two pieces
The BRAM of 18Kbits is merged into the BRAM of one piece of 36Kbits automatically, that is, needs the BRAM resource of 250/2=125 block 36Kbits.
In view of maximum row weight is 27, maximum column weight is 13, and CNU and VNU are all made of c=6 and v=in our design
6 level production lines, so this adaptive decoding device needsA clock cycle completes an iteration, when
When 10 path channels information are input to decoder parallel, receive a frame and need 16200/10=1620 clock cycle, so maximum
The number of iterations can be set toIt is secondary.This patent is translated using the CNU and VNU alternating data different to two frames
Code, so decoder can receive the case where 20 path channels information input parallel simultaneously.Pass through placement-and-routing's decoding of the invention
The maximum functional clock frequency of device is 250Mhz, and the maximum throughput of adaptive decoding device is 250MHz × 20=5Gbps.
The adaptive ldpc decoder of 5 kinds of code-rate-compatibles of DVB-S2 and the individually designed decoder of various code rates are occupied
Resource is as shown in table 6 below:
7/9,8/9,5/6,2/3,2/5, the 3/5 code rate LDPC code hardware resource of compatibility that table 6.DVB-S2 code length is 16200
It can see from upper table, resource ratio used in the LDPC adaptive decoding device of this 5 kinds of code rates of the compatibility of design
The resource more 67% that maximum decoder (3/5 code rate) occupies when individually designed, the maximum number of iterations of decoder are 10
Secondary, handling capacity is 250MHz × 20=5Gbps.With the decoder handling capacity highest in the background technique Literature of specification
2.25Gbps is compared, and handling capacity is higher, and decoder of the invention is very easy to realize code-rate-compatible, i.e. adaptivity, disappears
The hardware resource of consumption is less.And this design can also be neatly by improving the parallel number in 360 pieces, further to mention
The handling capacity of high ldpc decoder can also dynamically change in 360 pieces and walking along the street degree, to adjust ldpc decoder occupancy
Hardware resource meets the transmission demand of different hardware platforms difference handling capacity.
Technical solution of the present invention in satellite receiver Successful utilization and pass through associated communication system test.
The content that description in the present invention is not described in detail belongs to the well-known technique of professional and technical personnel in the field.
The above, optimal specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.
Claims (2)
1. a kind of high-speed adaptive DVB-S2 ldpc decoder based on FPGA, it is characterised in that the decoder includes: CTRL
Control module, components of system as directed external information memory module RAM_M, check-node updates and check equations computing module CPM, RTS net
Network Switching Module, verification external information memory module RAM_C, variable node processing module VNM, channel information memory module RAMF and
Export memory module RAM_OUT；
The channel information memory module RAMF, for the channel information of storage decoder input port input, by N number of memory
It constitutes, N is the column block count of check matrix；It is divided into message part external information memory RAM _ QC and check part external information is deposited
Reservoir RAM_RTS two parts, wherein RAM_QC includes N-q memory RAM, is denoted as Ri, 1≤i≤N-q；RAM_RTS includes q
A memory RAM, is denoted as Fi, 1≤i≤q, q are the interval constant that code rate is corresponded in DVB-S2 standard；The RAM_QC is being decoded
The channel information of message part is provided for VNM in the process, the RAM_RTS provides the channel information of check part for VNM；
The variable node processing module VNM, variable node external information updates calculating and codeword decision meter during completing decoding
It calculates, it is made of N number of code check node processing unit, is divided into message part variable node processing unit VNU and check part variable
Endpoint processing unit VTU two parts, wherein VNU is N-q, is denoted as VNUi, 1≤i≤N-q, VTU are q, are denoted as VTUi, 1≤i
≤q；VNUiFrom the memory R in RAM_QCiThe middle channel information for obtaining message part, while being obtained outside corresponding from RAM_M
Information carries out variable node and updates calculating and codeword decision calculating, updated external information and codeword decision result are written back to
In RAM_M, and RAM_OUT is written into codeword decision result；VTUiFrom the memory F in RAM_RTSiMiddle acquisition message part
Channel information, while corresponding external information is obtained from RAM_C, it carries out variable node and updates calculating and codeword decision calculating, it will
Updated external information and codeword decision result are written back in RAM_C, and RAM_OUT is written in codeword decision result；
The CPM module is responsible for the syndrome that check-node is updated and verified and is calculated, it is by q check-node updating unit CNU
It is formed with q check equations computing unit PCU, is denoted as CNU respectivelyiAnd PCUi, 1≤i≤q；CNUiAnd PCUiRespectively from RAM_M
With the external information that updates of variable node and codeword decision are obtained in RAM_C as a result, CNUiVerification section is carried out according to external information
Point, which updates, to be calculated, and updated external information is written back to RAM_M and RAM_C, PCUiSyndrome is calculated according to codeword decision
Vector s, and syndrome vector s is sent into CTRL control module；
The components of system as directed external information memory module RAM_M is responsible for storage message part submatrix H1 tNonzero element it is corresponding
External information, for the VNU in VNMiWith the CNU in CPMiExternal information exchange；Each decoding iteration, first VNUiFrom RAM_M
External information is read in, carries out that result is written back to RAM_M after variable node update calculates, then CNUiOuter letter is read in from RAM_M
Breath carries out that updated external information is written back to RAM_M after check-node update calculates；
The verification external information memory module RAM_C is responsible for storage check part submatrix H2 tThe corresponding outer letter of nonzero element
Breath, for the VTU in VNMiWith the CNU in CPMiExternal information exchange, by 2q MCiMemory composition, is labeled as MCi, 1≤i
≤2q；Each decoding iteration, first VTUiExternal information is read in from RAM_C, carries out result after inciting somebody to action after variable node update calculates
It is written back to RAM_C, then CNUiExternal information is read in from RAM_C by RTS network exchange module, is carried out check-node and is updated meter
Updated external information is written back to RAM_C after calculation；
The RTS network exchange module, for solving the problems, such as that CNU and VNU concurrent reading and concurrent writing alignment of data is inconsistent, size 2q
Each memory MC in × 2q, it and RAM_Ci, 1≤i≤2q connection；2q input/output port is divided into q group, input terminal slogan
Respectively (2,3), (4,5) ... (2q, 1), the output end slogan being respectively grouped are respectively (1,2), (3,4) ... (2q-1,2q)；
The CTRL control module is responsible for the coordinated control of decoder each section, and the syndrome vector sent according to CPM module
S judges that decoder continues loop iteration and is also off；
The output memory module RAM_OUT adjudicates code word for storing the decoding generated in iterative decoding process, and is decoding
At the end of exported；
Wherein: the storage check part submatrix H in the verification external information memory module RAM_C2 tNonzero element it is corresponding
External information, storage mode are H2 tIn each sub-line store nonzero element using the memory that two depth are L, L is circulation
Shift length, H2 tCorresponding external information needs 2q memory to store, and line number is denoted as s, the corresponding memory difference of each row
For (s=0 | MC1,MC2), (s=1 | MC3,MC4) ..., (s=q-1 | MC2q-1,MC2q)；E [c] [d] indicates H2 tNonzero element,
C, 1≤c≤q × L indicate column mark, due to H2 tRow weight be 1 or 2, enable d, 0≤d≤1 indicates H2 tD-th of nonzero element；It is right
In H2 t, 2q nonzero element is shared, respectively (E [0] [0], E [0] [1]), (E [1] [0], E [1] [1]), (E [2] [0], E [2]
[1]) ..., (E [q × L-2] [0], E [q × L-2] [1]), (E [q × L-1] [0]), they respectively correspond the line number of original matrix
0,q,2q,…,359q,1,q+1,2q+1,…,359q+1,…,q-1,q+q-1,2q+q-1,…,359q+q-1。
2. the high-speed adaptive DVB-S2 LDPC interpretation method based on FPGA, it is characterised in that steps are as follows:
(1) to original checksums matrix H=[H of LDPC code in DVB-S2 standard1|H2] capable transformation is carried out, obtain new matrix Ht=
[H1 t|H2 t], by converting rear left matrix H1 tIt is a quasi- cyclic submatrix, abbreviation QC matrix, right matrix H2 tIt is a row
Convert the lower double diagonal submatrix of triangle, abbreviation RTS matrix；
(2) according to the transformed partitioning of matrix, information bit information corresponding to the data frame received is stored to information and is deposited
It stores up in block RAM _ QC, by the storage of corresponding check bit information into verification memory block RAM_RTS, while by external information memory block
The content of RAM_C and RAM_M is initialized as zero, initializes the number of iterations iter=1；
(3) external information, VNU are read from RAM_C and RAM_Mi, 1≤i≤45-q progress matrix H1 tPartial variable node external information
Update calculating and codeword decision, VTUi, 1≤i≤q progress matrix H2 tPartial variable node external information updates to calculate to be sentenced with code word
Certainly, and by result it is written back in RAM_C and RAM_M；RAM_OUT is also written in codeword decision result simultaneously, for decoding output；
(4) the updated external information of variable node and codeword decision are read as a result, CNU from RAM_C and RAM_Mi, 1≤i≤q according to
Extrinsic information data carries out the calculating of check-node external information, and result is written back in RAM_C and RAM_M；PCUi, 1≤i≤q root
Syndrome vector s is carried out according to codeword decision result to calculate；The number of iterations iter adds 1；
(5) if syndrome vector s=0 or the number of iterations iter=MAX_ITER, goes to step (6), MAX_ITER sets for decoder
The maximum number of iterations set；Otherwise, (3) are gone to step and continue next round iterative processing；
(6) decoding decision bits are read from RAM_OUT, exports code word；
Wherein: the row map function of check matrix is that row sequence is adjusted to 0, q by row matrix exchange in the step (1),
2q ..., 359q, 1, q+1,2q+1 ..., 359q+1 ..., q-1, q+q-1 ..., 359q+q-1, wherein q is in DVB-S2 standard
The interval constant of corresponding code rate；It is adjusted, the message part H of check matrix H1Become the quasi- circulation of q × 45 piecemeal composition
Structure matrix H1 t, each piecemeal size is L × L, and L is cyclic shift length, double diagonal arrangement matrix Hs of check part2By
Row is transformed to H2 t, obtain a new row and convert lower triangle dual-diagonal matrix；
VTU in the step (3)i, it is VTU that 1≤i≤q variable node external information, which updates calculating process,iIt is deposited respectively from external information
Store up block MC(2i) % (2q)And MCT, (2i+1) % (2q)Middle 2p external information of reading and the p channel information of reading from RAM_RTS, update
For information back afterwards into identical RAM_RTS storage address, p is the degree of parallelism of design of encoder, and read/write address sequence isL is cyclic shift length；
The process that check-node in the step (4) updates and syndrome vector calculates is, from memory RAM _ M (n-
2) p H1 tMatrix external information and come from memory MC2s-1,MC2s2p H2 tMatrix external information, while it being sent to CNU,
After CNU is updated and calculated, it is as a result written back to memory RAM _ M and MCt,2s-1,MCt,2sIdentical address in；Meanwhile PCU
It carries out reading corresponding decoding decision bits according to verification battle array, calculates the check value of each equation, form syndrome vector s.
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| CN109802687B (en) * | 2018-12-25 | 2023-05-02 | 西安空间无线电技术研究所 | High-speed code rate compatible LDPC encoder of QC-LDPC code based on FPGA |
| CN109831214A (en) * | 2018-12-29 | 2019-05-31 | 中国电子科技集团公司第二十研究所 | A kind of full parellel ldpc decoder and FPGA implementation method |
| CN110278000B (en) * | 2019-07-16 | 2020-12-11 | 南京中科晶上通信技术有限公司 | Decoding method for realizing architecture by parallel decoding of LDPC code FPGA based on DVB-S2 standard |
| CN111313911A (en) * | 2019-11-22 | 2020-06-19 | 南京大学 | Degree self-adaptive fixed-point decoding algorithm suitable for 5G LDPC code |
| CN110808742A (en) * | 2019-11-22 | 2020-02-18 | 南京大学 | Efficient decoder framework suitable for 5G LDPC code |
| CN112272029B (en) * | 2020-10-22 | 2024-04-09 | 西安空间无线电技术研究所 | LDPC decoder implementation method based on DVB-S2 standard |
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