CN110808742A - Efficient decoder framework suitable for 5G LDPC code - Google Patents
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract
The invention discloses a decoder framework with high throughput rate and low complexity, which is universally used for 5G LDPC codes for the first time. Firstly, by utilizing the partial orthogonality of the 5G LDPC code base matrix, the number of clock cycles is reduced by adopting a layer combination technology, and meanwhile, the area consumption of a check information memory is reduced. Secondly, since the row weight of the 5G LDPC is very irregular, a distributed storage structure is adopted to reduce the storage resource consumption. Finally, in order to solve the problems of high delay and high complexity caused by large-scale reading and writing of the internet, the soft message memory is realized by adopting a shift structure, so that the input and output number of the internet is greatly reduced. In addition, information rearrangement is applied in the internet to optimize the internal architecture thereof. Compared with the conventional design, the area of the decoder disclosed by the invention is greatly reduced, higher throughput rate can be provided, and the throughput rate-area ratio is increased to 2.68 times of the original throughput rate-area ratio.
Description
Technical Field
The invention relates to a decoder architecture design in the technical field of communication coding, in particular to a decoder architecture which is suitable for 5G LDPC codes and has high throughput rate and low complexity.
Background
Error correction codes are a very important component of modern communication systems. In the latest 5G communication standard, LDPC codes are adopted as a channel coding scheme due to their superior error correction performance and relatively low decoding complexity. Unlike conventional LDPC codes, 5G LDPC codes are required to be rate compatible in order to support hybrid automatic repeat request (HARQ). Therefore, the base matrix is a cascade of a high code rate LDPC code matrix and a Low Density Generator Matrix (LDGM). The row weight columns of the 5G LDPC code are extremely irregular, the row weight of each check node and the column weight of each variable node are greatly different. The third generation partnership project (3GPP) provides two base matrices, base matrix 1(BG1) and base matrix 2(BG2), for a 5G LDPC code. The two base matrices have similar structures. Wherein BG1 is used for codewords with higher code rate and code length, and BG2 is used for codewords with lower code rate and code length.
The existing LDPC decoder architecture mainly comprises three types, namely a full parallel architecture, a full serial architecture and a partial parallel architecture. In order to obtain a good tradeoff between throughput and hardware complexity, a layered decoding architecture based on partial parallelism is currently in common use. By adopting the layered decoding, the convergence rate can be increased under the condition of not influencing the decoding performance, so that the required iteration times are reduced, and the throughput rate is improved. Although the design of the decoding architecture of LDPC has been widely studied, at present, there is no decoder designed specifically for 5G LDPC codes. In consideration of the structural particularity, the adopted general decoding architecture causes great resource waste and less ideal throughput rate. Therefore, a great research space exists in the design and optimization problem of the 5G LDPC code decoder.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to solve the problems and provide a high-throughput and low-complexity 5G LDPC decoder. The specific invention content is as follows:
a high throughput, low complexity decoder architecture for 5G LDPC codes in general, comprising:
1) a controller for generating all control signals in the decoder;
2) a soft message memory for storing the soft decision message for each bit. To be able to support massively parallel reading and initializing soft decision messages of all bits, the memory is implemented by a register set. To reduce the resource consumption of the input to the internet, the soft decision messages corresponding to the extension bits are stored separately from the soft decision messages corresponding to the core bits. The memory in which the soft decision messages corresponding to the extension bits are stored is implemented using a shift architecture, so that the address of the required data can be fixed. Based on this, the memory corresponding to the portion only needs to input and output one set of data at a time;
3) and the check information memory is used for storing the check information obtained by calculation of each check node. To be able to support simultaneous read and write operations, the unit is implemented using a dual port random access memory (DRAM). In order to reduce the area consumption, a distributed structure is adopted. First, a threshold value is preset
For determining the size of the row weight of each layer. Secondly, for line weights less than or equal toThe layer (2) stores all check messages output by the check nodes in the first sub-memory. For line weights greater than
For the check message output by each check node, the address message in the check message is stored in the second sub-memory, and the rest of the check message is stored in the first sub-memory. It is worth noting that since the second sub-memory is only applied to the row weight larger than that
So that its depth is much smaller than the first sub-memory;
4) a read interconnect network for reading the soft message values from the soft message memory and selecting the maximum row weight corresponding to the current execution layerAnd outputting the group soft message. To reduce the internet consumption, the corresponding input messages for each output in each layer are reordered in a manner that minimizes the number of inputs required to produce each output. The sorting is completed off line, so that hardware resources are not occupied;
5) and the shifter shifts the soft decision messages according to the shifting factors corresponding to each group of soft decision messages, so that the interior of the soft decision messages can be arranged according to a correct sequence. The shift factor of each group of messages at the current layer is the shift coefficient of the column of the corresponding base matrix at the current layer minus the last non-negative shift coefficient of the column. Thus, a re-shift when writing a message to the soft message memory is omitted. In addition, before being loaded into the soft message memory, the input data needs to be reversely shifted according to the last shift coefficient of the column of the corresponding base matrix, so as to ensure the position correctness of each group of messages during the first shift. Before output, the output data needs to be shifted according to the last shift coefficient of the column of the corresponding base matrix to ensure that the output code words are sequenced according to the correct sequence;
6) the variable node unit is used for generating variable information transmitted to the check node by the variable node;
7) and the check node unit is used for generating a check message transmitted to the variable node. To reduce the storage width, the output data is arranged in a compressed format. For example, for the min-sum decoder, in each check node, only the sign bit of each check message, the minimum input variable message and its corresponding address, and the second minimum input variable message are output;
8) the decompressor is used for converting the check information from a compressed form into an uncompressed form;
9) write-in internetwork, generated based on currently executing layer
The group updated soft message generates the required messages in the soft message store.
In the proposed architecture, the partial orthogonality of the base matrix of the 5G LDPC code is exploited, and two layers of orthogonal parts are treated as one layer for decoding. Therefore, the required number of clock cycles can be greatly reduced, thereby improving the throughput rate. In addition, the depth of the check message memory can be reduced accordingly.
The decoder framework provided by the invention has the following beneficial effects:
firstly, the number of layers of a decoder is reduced, so that the number of required clock cycles is reduced, and the throughput rate is improved;
secondly, the width and the depth of the check information memory are greatly reduced, and the area consumption is reduced;
finally, the area and latency of the read and write interconnect network is optimized.
Based on the advantages, the decoder framework provided by the invention greatly reduces the area and delay required by the 5G LDPC decoder, and improves the throughput rate-area efficiency ratio.
Drawings
FIG. 1 is a top level architecture of a decoder according to the present invention;
FIG. 2 is a schematic diagram of the orthogonal property of the basis matrix 2;
FIG. 3 is a schematic diagram of an embodiment of a parity information storage device in the decoder according to the present invention;
FIG. 4 is a diagram illustrating a soft message memory shift structure in a decoder according to the present invention;
fig. 5 is a schematic diagram of a BG2 matrix structure.
Detailed Description
The decoder architecture proposed by the present invention will be further explained with reference to the accompanying drawings. It is specifically noted that the embodiments described with reference to the drawings are exemplary and intended to be illustrative of the invention and are not to be construed as limiting the invention.
Fig. 1 is a top-level architecture diagram of a decoder according to the present invention, in which a layered decoding structure is employed, and the number of layers is equal to the number of rows of the corresponding codeword base matrix, denoted as L. The parallel coefficients of the decoder are equal to the spreading factor of the base matrix, denoted z. In the proposed decoding architecture, all control signals are generated by a controller. First, a message derived from a channel is shifted by an input shifter and loaded into a soft message memory. And the input shifter performs reverse shift according to the last shift coefficient on the column of the base matrix corresponding to each group of messages. Each decoding iteration consists of L decoding layers. In each decoding layer, first, a soft decision message is read out from a soft message memory and input to a read interconnection network which generates a maximum repetition corresponding to a currently executing layer according to the current decoding layer
And (4) grouping the soft messages. Secondly, each group of soft messages is circularly shifted in the shifter, and the shift factor is the shift coefficient of the column of the base matrix corresponding to the group of messages at the current layer minus the last non-negative shift coefficient of the column. The shifted messages are sent to the variable node unit for generating variable messages, which are sent to the check node unit for generating check messages. For different decoding algorithms, the generation modes of the check messages are different, so the realization mode of the check node unit is not specified in the invention. The check message then serves two purposes. One is to store it in the check information memory for use in generating the variable message in the next decoding iteration. To reduce the bit width of the check information memory, it is arranged in a compressed format. For example, for a min-sum decoder, in each check node, only the sign bit of the check message, the min-input variable message and its corresponding address, and the second min-input variable message are output. And the second is that the soft decision message is decompressed by a decompressor and then combined with the variable message of the current iteration to generate an updated soft decision message value. The updated soft decision messages are ordered and selected in the write-in-the-internet to ensure that they are stored in the correct soft message decoder address. After all decoding layer operations are completed, decoding completes one iteration. When the maximum number of iterations T is reachedmaxThen, the decoding is terminated and the decoded codeword is output. It should be noted that before being output, the decoded codeword needs to be shifted according to the last shift coefficient of the column of the corresponding base matrix, so as to ensure that the output data are ordered according to the correct sequence.
Fig. 2 is a schematic diagram of the orthogonal characteristic of the base matrix 2. It can be seen that the 21 st to 42 th rows of the matrix are orthogonal, which means that any one variable node is not connected to two consecutive layers in the orthogonal part at the same time. Thus, we can treat two successive layers in the orthogonal portion as one layer, which can provide two benefits. Firstly, the required cycle number can be reduced by reducing the number of decoding layers, so that the throughput rate is improved; secondly, the reduction of the decoding layer number can lead the check information to be storedThe depth of the device is correspondingly reduced, and further the consumption of storage resources is reduced. Considering that the line weights of the orthogonal parts are all less than
Lamination does not cause an increase in memory width. For the BG2 matrix, L can be lowered from 42 to 31 using lamination. Therefore, the number of decoding cycles and the consumption of the check information memory can be reduced by 26.2%. For the BG1 matrix, the percentage reduction was 28.3%.
Fig. 3 is a schematic diagram of a specific structure of the check information storage in the decoder according to the present invention. Since the row weights of the 5G LDPC code are very irregular, there is a large difference between the row weights of the respective rows. Typically the width of the memory needs to match the maximum row weight. When decoding is performed using the min-sum decoder, the width of the check information storage can be expressed as
Where q is the number of quantized bits of the check message. This design is wasteful for the lower row weight layer. Therefore, the present invention provides a distributed storage method for the verification information storage, and the specific structure is shown in fig. two. First, a threshold value is preset
For determining the size of the row weight of each layer. Secondly, for line weights less than or equal to
The layer (2) stores all check messages output by the check nodes in the first sub-memory. For line weights greater than
For the check message output by each check node, the address message in the check message is stored in the second sub-memory, and the rest of the check message is stored in the first sub-memory. It is worth noting that since the second sub-memory is only applied to the row weight larger than thatSo that its depth is much smaller than the first sub-memory. Based on this, the resource consumption of the check information storage can be further reduced. For example, for the BG1 matrix
Setting to 15, the check information memory size can be reduced by 15.2% at this time; for the BG2 matrixSet to 8, the check information memory size can now be reduced by 13.7%. When combined with the layer merging technique, the check information memory size can be reduced by 39.1% and 36.3% for BG1 and BG2 matrices, respectively.
Fig. 4 is a schematic diagram of a soft message memory shift structure in the decoder according to the present invention. Because the size of the internet plays a leading role in the whole area, power consumption and time delay of the decoder, the invention provides two improvement modes for reducing the resource consumption. First, the number of incoming and outgoing messages of the internet is reduced. Taking BG2 matrix as an example, fig. 5 is a schematic structural diagram of BG2 matrix. Since it includes 52 columns, the number of sets of input messages reading the internet is 52. Considering the bottom right corner (matrix I) of BG2 as the identity matrix, each iteration layer will only use a set of soft decision messages corresponding to the partial matrix in order. Based on this, the present invention stores the soft decision information corresponding to the partial matrix independently, and implements the partial memory by adopting a cyclic shift mode, and the specific structure is shown in fig. 4. With this architecture, the storage addresses of the soft messages required by all iteration layers in the part can be fixed to be the same. Therefore, the part of the memory only outputs and inputs one group of data at a time, thereby greatly reducing the number of input and output of the interconnection network. For a BG2 matrix, the number of inputs to the read interconnect and the number of outputs to the write interconnect may be reduced from 52 to 16. Second, in order to minimize the area and delay required to generate each output in the internetwork, the corresponding input messages for each output in each layer are reordered in a manner that minimizes the number of inputs required to generate each output. The sequencing is completed off-line, thus not occupying hardware resources.
Example (b): the decoder architecture disclosed by the invention is realized by taking a 5G LDPC code defined by BG2 as an example, wherein the code length is 2600, the code rate is 1/5. The decoder is described by Verilog language, the obtained RTL is synthesized by using Synopsys tool, and the adopted process is CMOS process of TSMC 90 nm. The comprehensive results show that after the optimization method disclosed by the invention is used, the working frequency of the decoder is increased from 121Mhz to 164MHZ, and the area is 1.831mm2Down to 1.236mm2The throughput rate is improved from 524Mbps to 947 Mbps. For a more intuitive comparison, we also compare throughput-power consumption ratios. By using the optimization method disclosed by the invention, the throughput-power consumption ratio of the decoder is 286.1Mbps/mm2Is increased to 766.2Mbps/mm2And the speed is increased to 2.68 times of the original speed.
While the invention has been described with reference to specific preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (7)
1. A decoder framework with high throughput rate and low complexity, which is generally used for 5G LDPC codes, adopts a layered decoding structure, and is characterized by comprising the following units:
1) a controller for generating all control signals in the decoder;
2) a soft message memory for storing the soft decision message for each bit. In order to be able to support massively parallel read and initialization operations, the memory is implemented by register sets;
3) and the check information memory is used for storing the check information obtained by calculation of each check node. In order to support simultaneous read and write operations, the unit is implemented using a dual port random access memory (DRAM);
4) a read internetwork for reading soft messages from the soft message memory and selecting the soft message corresponding to the current soft messageMaximum row weight of execution layer
Outputting the group soft message;
5) the shifter shifts the soft decision messages according to the shift factors corresponding to each group of soft decision messages, so that the interior of the soft decision messages can be arranged according to a correct sequence;
6) the variable node unit is used for generating variable information transmitted to the check node by the variable node;
7) a check node unit for generating a check message corresponding to each variable node;
8) the decompressor is used for converting the check message from a compressed form into an uncompressed form;
9) writing to the Internet based on current generation
The group updated soft message generates a message that is input into the soft message store.
2. The high-throughput, low-complexity decoder architecture of claim 1, wherein two layers of orthogonal portions are treated as one layer for decoding using partial orthogonality of the base matrix of the 5G LDPC code. Therefore, the required number of clock cycles can be reduced, thereby improving throughput. Furthermore, the depth of the check message memory of claim 1 can be reduced accordingly.
3. The soft message memory of claim 1, wherein soft decision messages corresponding to extension bits are stored separately from soft decision messages corresponding to core bits in order to reduce resource consumption for input to the read and write internetworks of claim 1. The memory in which the soft decision messages corresponding to the extension bits are stored is implemented using a shift architecture, so that the memory address of the required data can be fixed. Based on this, the partial memory only needs to input and output one set of data at a time.
4. The shifter of claim 1,
1) the shift factor of each group of messages at the current layer is the shift coefficient of the column of the corresponding base matrix at the current layer minus the last non-negative shift coefficient of the column. Thus, the re-shifting required when writing messages to the soft message memory is eliminated;
2) before being loaded into a soft message memory, input data needs to be reversely shifted according to the last shift coefficient of the column of the corresponding base matrix so as to ensure the position correctness of each group of messages during the first shift;
3) before output, the output data needs to be shifted according to the last shift coefficient of the column of the corresponding base matrix, so as to ensure that the output code words are ordered according to the correct sequence.
5. The check node unit of claim 1, wherein the output data is arranged in a compressed format. For example, for a min-sum decoder, in each check node, only the sign bit of the check message, the min-input variable message and its corresponding address, and the second min-input variable message are output.
6. The check information storage according to claim 1, implemented in a distributed structure for reducing area consumption, wherein:
1) presetting a threshold value
Used for judging the size of each layer of row weight;
2) for row weight less than or equal to
The layer (2) stores all check messages output by the check nodes in a first sub-memory;
3) for line weights greater thanFor the check message output by each check node, storing the address message in the check message in a second sub-memory, and storing the rest part of the check message in a first sub-memory;
4) the second sub-memory being only applied to row weights greater than
Thus having a depth much smaller than the first sub-memory.
7. The read and write internetworking of claim 1, wherein, to reduce the hardware resource consumption of the internetworking, the corresponding input messages in each layer for each output are reordered in a manner that minimizes the number of inputs required to produce each output. The sequencing is completed off-line, thus not occupying hardware resources.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211790A (en) * | 2020-02-25 | 2020-05-29 | 重庆邮电大学 | High-throughput-rate LDPC decoding algorithm and architecture for 5G terminal |
| WO2021233788A1 (en) * | 2020-05-18 | 2021-11-25 | Accelercomm Ltd | Low density parity check decoder, electronic device, and method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101707485A (en) * | 2009-02-03 | 2010-05-12 | 天津博微科技有限公司 | LDPC decoding method combining bit flipping (BF) and majority logic (MLG) |
| US20160197701A1 (en) * | 2013-07-22 | 2016-07-07 | Samsng Electronics Co., Ltd. | Apparatus and Method for Receiving Signal in Communication System Supporting Low Density Parity Check Code |
| CN106571829A (en) * | 2016-10-27 | 2017-04-19 | 西安空间无线电技术研究所 | FPGA-based high-speed adaptive DVB-S2 LDPC decoder and decoding method |
| CN110071726A (en) * | 2019-04-16 | 2019-07-30 | 南京大学深圳研究院 | The building method and its code translator of combining LDPC code in multi-layered unit flash memory |
| CN110192349A (en) * | 2017-01-06 | 2019-08-30 | 诺基亚技术有限公司 | The method and apparatus for using and generating for the LDPC basis matrix based on vector |
-
2019
- 2019-11-22 CN CN201911161918.3A patent/CN110808742A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101707485A (en) * | 2009-02-03 | 2010-05-12 | 天津博微科技有限公司 | LDPC decoding method combining bit flipping (BF) and majority logic (MLG) |
| US20160197701A1 (en) * | 2013-07-22 | 2016-07-07 | Samsng Electronics Co., Ltd. | Apparatus and Method for Receiving Signal in Communication System Supporting Low Density Parity Check Code |
| CN106571829A (en) * | 2016-10-27 | 2017-04-19 | 西安空间无线电技术研究所 | FPGA-based high-speed adaptive DVB-S2 LDPC decoder and decoding method |
| CN110192349A (en) * | 2017-01-06 | 2019-08-30 | 诺基亚技术有限公司 | The method and apparatus for using and generating for the LDPC basis matrix based on vector |
| CN110071726A (en) * | 2019-04-16 | 2019-07-30 | 南京大学深圳研究院 | The building method and its code translator of combining LDPC code in multi-layered unit flash memory |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211790A (en) * | 2020-02-25 | 2020-05-29 | 重庆邮电大学 | High-throughput-rate LDPC decoding algorithm and architecture for 5G terminal |
| CN111211790B (en) * | 2020-02-25 | 2023-09-29 | 重庆邮电大学 | High throughput LDPC decoding algorithm and architecture for 5G terminal |
| WO2021233788A1 (en) * | 2020-05-18 | 2021-11-25 | Accelercomm Ltd | Low density parity check decoder, electronic device, and method therefor |
| US11962326B2 (en) | 2020-05-18 | 2024-04-16 | Accelercomm Limited | Low density parity check decoder, electronic device, and method therefor |
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