CN104702292A - Implementation method for partially-parallel LDPC decoder - Google Patents

Abstract

The invention discloses an implementation method for a partially-parallel LDPC decoder. The implementation method for the partially-parallel LDPC decoder mainly solves the problem of high LDPC decoder hardware implementation complexity of an existing DVB-X2 system. The implementation method includes steps that (1) regulating the sequence of log-likelihood ratio information input by the LDPC decoder; (2) converting the input one-way data into 180-way parallel data; (3) initializing a variable node according to a partially-parallel decoding structure with degree of parallelism 180; (4) updating a verification node; (5) updating the variable node; (6) when the set maximum iterations is finished, calculating hard judgment information; (7) judging the hard judgment information; (8) regulating the sequence of the judgment information, and outputting the decoding result according to the sequence corresponding to the decoder input sequence.

Description

A kind of implementation method of part parallel ldpc decoder

Technical field

The invention belongs to wireless communication technology field, relate to a kind of implementation method of part parallel ldpc decoder, specifically, relate to a kind of implementation method being applicable to the part parallel ldpc decoder of DVB-X2 system.

Background technology

For guarantee information can the transmission of high efficient and reliable, require that communication system has certain EDC error detect correction ability.Forward error correction effectively can improve the impact of interchannel noise on information transmission, be widely applied in modern digital communication systems, the study hotspot in the error-correcting code technique of the low density parity check code (Low Density ParityCheck, LDPC) of programmable single-chip system shannon limit performance this field especially.In recent years, for second generation digital video broadcasting (Digital Video Broadcasting-Satellite 2, Terrestrial 2 or Cable 2, is referred to as DVB-X2) low cost of LDPC code of system, high speed FPGA realize getting the attention.The hard-wired complexity of existing ldpc code decoder is higher, how to reduce the hard-wired resource occupation of ldpc decoder, becomes the emphasis of scholar and technical staff's research in the industry.

Ldpc code decoder can adopt full serial decoding architecture, full parellel decoding architecture or Partly parallel decoding structure to realize.Full serial decoding architecture only has a variable node updating block and a check-node updating block, within each clock cycle, only carry out the renewal of check-node or only carry out the renewal of variable node, its hardware realization of decoding structure is simple, but because calculating processes all in this structure all adopt pipelined burst row relax, make its decoding latency very serious, and time delay can increase with the increase of code length, causes its decoding throughput very low, can not meet the throughput requirement of DVB-X2 up to 80Mbps.And the renewal of all check-nodes and variable node is carried out within the same clock cycle in full parellel decoding architecture simultaneously, its decoding rate is fast, throughput is high, but with what to sacrifice decoding complexity be cost, and along with its decoding complexity exponential increase of increase of code length.LDPC code definition 16200 and 64,800 two kinds of length in DVB series standard, full parellel decoding architecture implementation complexity is too high, is unfavorable for that related chip is popularized.Parallel processing between each submodule of Partly parallel decoding structure, but there is serial process each submodule inside again, in the decoding rate and decoding throughput etc. of decoding complexity, the taking of hardware resource, decoder, Partly parallel decoding structure is the compromise of full serial and full parellel decoding architecture, is the main direction of studying of current engineering circles and academia.For part parallel ldpc decoder, degree of parallelism and decoder inter-process mode weigh the important indicator of its implementation structure quality.2010, G.Fernandes appears for the first time and propose a kind of Hardware Implementation adopting the ldpc decoder of Partly parallel decoding structure in its thesis for the doctorate " Parallel Algorithms and Architectures for LDPCDecoding ", degree of parallelism is 180, the designs such as inner use tubbiness shifting processing module and decoding parameter difference ROM storage, make it in complexity and throughput, achieve good compromise, but decoding complexity is still higher, and not do not carry out special design optimization for characteristics such as the multi code Rate of Chinese character of DVB-X2, length code coexist.

Summary of the invention

In order to overcome the defect existed in prior art, the present invention utilizes the field programmable gate array (FPGA) extensively adopted in digital processing field at present, propose a kind of implementation method of part parallel ldpc decoder, by optimizing data shifts module and decoding parameter memory module in ldpc decoder, to reach the object reducing the complexity that it realizes further.

Its technical scheme is as follows:

Realizing technical thought of the present invention is: the implementation method of the LDPC low complex degree Partly parallel decoding device of the present invention's design, comprise following process: the order of the log-likelihood ratio information of adjustment ldpc code decoder input, and 1 circuit-switched data of input is converted into the parallel data in 180 tunnels, by the Partly parallel decoding structure that degree of parallelism is 180, the data shifts module improved is used to carry out initialization to variable node, carry out the update process of check-node, and then carry out the renewal of variable node, when completing set maximum iteration time, calculate hard decision information, finally hard decision information is adjudicated, the order of adjustment discriminative information, export the decode results of corresponding order.An implementation method for part parallel ldpc decoder, comprises the following steps:

1) order adjustment is carried out to the log-likelihood ratio be input in decoder (LLR) information flow, obtain LLR information flow a;

2) by step 1) described in LLR information flow a be converted to 180 parallel circuit-switched data, be stored in first memory RAM1, after frame data finish receiving, by the data conversion storage in first memory RAM1 in second memory RAM2;

3) again input data are deposited in first memory RAM1 when next frame data arrives, simultaneously, the Rate Control information that encoded control module inputs according to decoder, what export second memory RAM2 under corresponding code check reads address information, export the data in second memory RAM2, obtain LLR information flow b, the LLR information of its corresponding variable node i is L (P _i), P _irepresent the probabilistic information of variable node i;

4) the Rate Control information that encoded control module inputs according to decoder, exports the encoded control information of corresponding code check, and LLR information flow b is shifted by control data shift module, obtains the initial value L of variable node ⁽⁰⁾(q _ij), q _ijrepresent that variable node i passes to the outside probabilities information of check-node j;

5) when decoding enable signal is effective, according to the encoded control parameter of the corresponding code check that encoded control module exports, upgrade check-node, the more new formula of check-node is as follows:

$L^{\left(k\right)}\left(r_{\mathrm{ji}}\right)=\mathrm{\α}\underset{i^{\′}\∈R_j\backslash i}{\mathrm{\Π}}\mathrm{sgn}\left(L^{\left(k\right)}\left(q_{i^{\′}j}\right)\right)\·\underset{i^{\′}\∈R_j\backslash i}{\min }\left(\right|L^{\left(k\right)}\left(q_{i^{\′}j}\right)\left|\right).$

Wherein k is the iterations of decoding, and initial value is 0, α is modifying factor, R _jrepresent the set of all variable nodes be connected with check-node j, R _ji represent the set of all variable nodes be connected with check-node j except variable node i, i ' ∈ R _ji represent i ' be set R _jelement in i, L ^(k)(r _ji) be the LLR information of the check-node j that kth time iteration obtains, wherein r _jirepresent that check-node j passes to the outside probabilities information of variable node i; L ^(k)(q _{i ' j}) represent the LLR information of kth time iteration variations per hour node i ' transmit to check-node j, q _{i ' j}represent that variable node i ' passes to the outside probabilities information of check-node j; Sgn (L ^(k)(q ^{i ' j})) represent and ask L ^(k)(q _{i ' j}) symbol, represent and ask all sgn (L meeting variable node i ' ^(k)(q _{i ' j})) product, | L ^(k)(q _{i ' j}) | represent L ^(k)(q _{i ' j}) absolute value, represent to obtain and allly meet variable node i ' ∈ R _ji | L ^(k)(q _{i ' j}) | minimum value;

6) according to the encoded control parameter that encoded control module exports, usage data shift module is by step 5) in the LLR information of check-node that calculates be shifted, for the renewal of variable node;

7) when step 6) described in the displacement of check-node LLR information complete after, decoding enable signal becomes effectively again, now according to the encoded control parameter that encoded control module exports, upgrade variable node, the more new formula of variable node is as follows:

$L^{\left(k\right)}\left(q_{\mathrm{ij}}\right)=L\left(P_i\right)+\underset{j^{\′}\∈C\left(i\right)\backslash j}{\mathrm{\Σ}}{L}^{\left(k\right)}\left(r_{j^{\′}i}\right),$

Wherein C (i) represents the set of all check-nodes be connected with variable node i, C (i) j represent the set of all check-nodes be connected with variable node i except check-node j, j ' ∈ C (i) j represent j ' be set C (i) the element of j, L ^(k)(q _ij) represent the LLR information of the variable node i that kth time iteration obtains, L ^(k)(r _{j ' i}) check-node j ' transmits to variable node i when representing kth time iteration LLR information, r _{j ' i}represent that check-node j ' passes to the outside probabilities information of variable node i, represent and ask all L meeting check-node j ' ^(k)(r _{j ' i}) and;

8) according to the encoded control parameter that encoded control module exports, usage data shift module is by step 7) in the LLR information of variable node that calculates be shifted, for the renewal of check-node in decoding iteration process next time;

9) iterations k increases by 1, repeats step 5) ~ 8), carry out decoding iteration process next time;

10) when iterations k reaches the maximum iteration time h of setting, calculate the hard decision information of all variable nodes, carry out hard decision and court verdict is carried out buffer memory, its computing formula is as follows:

$L^{\left(h\right)}\left(q_i\right)=L\left(P_i\right)+\underset{j\∈C\left(i\right)}{\mathrm{\Σ}}{L}^{\left(h\right)}\left(r_{\mathrm{ji}}\right)$

Wherein j ∈ C (i) represents that j is the element in set C (i), represent and solve all L meeting check-node j ^(k)(r _ji) and, r _jirepresent that check-node j passes to the outside probabilities information of variable node i;

11) adjust the order of discriminative information, according to the order corresponding with decoder input sequence, decode results is exported.Meanwhile, decoding enable signal becomes effectively;

12) step 3 is repeated) ~ 11) decoding is carried out to next frame data.

Preferably, wherein step 3), step 4), step 5), step 6), step 7) and step 8) described in encoded control module, a larger read only memory ROM is used to store the decoding parameter of different code check, more traditional method storing different code check parameter with multiple read only memory ROM, make use of FPGA device property, reduce the hard-wired resource occupation of ldpc decoder.And the encoded control parameter that encoded control module exports mainly comprises: the enable signal that the shift position of the shift position of the enable parameter of decoding, data shifts module and the degree of depth of displacement, data shifts module occurs first and data memory module RAM2 read address.

Preferably, wherein step 4), step 6) and step 8) described in data shifts module, it realizes the output that have employed conditional parallel mode control data shift module, improves the hard-wired maximum functional clock of ldpc decoder FPGA.

Preferably, wherein said step 5) in the renewal process of check-node, carry out as follows:

5a) calculate the absolute value of the LLR information of all variable nodes | L ^(k)(q _ij) |;

5b) calculate all minimum values meeting the LLR information of variable node i '

5c) calculate all products meeting the sign bit of the LLR information of variable node i '

5d) the updated value of calculation check node $L^{\left(k\right)}\left(r_{\mathrm{ji}}\right)=\mathrm{\α}\underset{i^{\′}\∈R_j\backslash i}{\mathrm{\Π}}\mathrm{sgn}\left(L^{\left(k\right)}\left(q_{i^{\′}j}\right)\right)\·\underset{i^{\′}\∈R_j\backslash i}{\min }\left(\right|L^{\left(k\right)}\left(q_{i^{\′}j}\right)\left|\right).$

Preferably, wherein said step 7) in the renewal process of variable node, carry out as follows:

7a) calculate the LLR information of all check-node j ' and

Control information 7b) exported according to encoded control module exports the initial value L (P of the variable node stored in RAM2 _i);

7c) calculate the LLR information of the variable node that kth time iteration obtains

Preferably, wherein said step 10) in the calculating of hard decision information, carry out as follows:

10a) according to decoding iteration complete enable signal calculate all check-node LLR information and

Variable node initial value L (P 10b) stored in Sequential output RAM2 _i);

10c) calculate the hard decision information of all variable nodes

10d) according to step 10c) the hard decision information L that calculates ^(h)(q _i) sign bit carry out decoding judgement;

10e) by step 10d) in the discriminative information that obtains carry out buffer memory, export for decoding.

Beneficial effect of the present invention is:

1) the present invention adopts a read only memory ROM to store the decoding parameter of multiple code check, the control information of the different code checks inputted by decoder exports the decoding parameter of corresponding code check, avoid in traditional ldpc code decoder the method using different read only memory ROM to store different code check decoding parameter in state modulator module, reduce the hard-wired resource occupation of ldpc code decoder FPGA.On Xilinx ML605 FPGA development board, its RAM takies resource and has dropped to 36% by original 41%.

2) the present invention adopts the output of conditional parallel mode control data shift module, by the implementation method of multiple adder and Do statement in more traditional ldpc code decoder, improves the hard-wired maximum functional clock of ldpc code decoder FPGA.

Accompanying drawing explanation

Fig. 1 is realization flow figure of the present invention;

Fig. 2 is the decoding block diagram of ldpc decoder of the present invention;

Fig. 3 is the present invention is the performance of BER analogous diagram of the ldpc code decoder of 1/4,1/3,1/2,3/5 for code check in the long frame of DVB-S2 standard;

Fig. 4 is the present invention is the performance of BER analogous diagram of the ldpc code decoder of 2/3,3/4,4/5,5/6 for code check in the long frame of DVB-S2 standard;

Fig. 5 is the present invention is the performance of BER analogous diagram of the ldpc code decoder of 1/5,1/3,3/5 for code check in the short frame of DVB-S2 standard;

Fig. 6 is the present invention is the performance of BER analogous diagram of the ldpc code decoder of 11/15,7/9,37/45 for code check in the short frame of DVB-S2 standard.

Embodiment

Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is described in more detail.

See figures.1.and.2, specific implementation step of the present invention is as follows:

Step 1: adjustment log-likelihood ratio (LLR) information being input to decoder being carried out to order.

The present embodiment, for DVB-X2 standard LDPC code, when the enable signal inputting data is effective, carries out the adjustment of order, obtains LLR information flow a to the LLR information flow be input in decoder.

Step 2: 1 circuit-switched data being input to decoder is converted to the data that 180 tunnels are parallel.

LLR information flow a described in step 1 is converted to 180 parallel circuit-switched data, is stored in first memory RAM1, after frame data finish receiving, by the data conversion storage in first memory RAM1 in second memory RAM2.

Step 3: export the data that 180 tunnels are parallel.

Again input data are deposited in first memory RAM1 when next frame data arrives, simultaneously, the Rate Control information that encoded control module inputs according to decoder, what export second memory RAM2 under corresponding code check reads address information, export the data in second memory RAM2, obtain the LLR information flow b that 180 tunnels are parallel, the LLR information of its corresponding variable node i is L (P _i).

This step and the encoded control module described in following steps, it realizes have employed a larger read only memory ROM to store the decoding parameter of different code check, and control to be selected by address, use different ROM to compared with the method storing decoding parameter with different code check, the method that the present invention proposes make use of FPGA device property, reduce hard-wired resource occupation, improve the maximum functional clock of ldpc decoder.

Step 4: initialization is carried out to variable node.

The Rate Control information that encoded control module inputs according to decoder, export the shift position under corresponding code check and displacement depth information, LLR information flow b is shifted by control data shift module, obtains the initial value L of variable node ⁽⁰⁾(q _ij).

The realization of this step and the displacement of the data shifts module described in following steps, adopts the cyclic shift of conditional parallel mode control realization data, instead of traditional implementation method by multiple adder and Do statement.

Step 5: check-node is upgraded

When decoding enable signal is effective, according to the encoded control parameter of the corresponding code check that encoded control module exports, check-node is upgraded, being implemented as follows of this step:

5a) calculate the absolute value of the LLR information of all variable nodes | L ^(k)(q _ij) |.Wherein, k is the iterations of decoding, and initial value is 0, L ^(k)(q _ii) represent the LLR information that kth time iteration variations per hour node i transmits to check-node j, | L ^(k)(q _{i ' j}) | represent L ^(k)(q _{i ' j}) absolute value;

5b) calculate all minimum values meeting the LLR information of variable node i ' wherein, R _jrepresent the set of all variable nodes be connected with check-node j, R _ji represent the set of all variable nodes be connected with check-node j except variable node i, i ' ∈ R _ji represent i ' be set R _jelement in i, represent to obtain and allly meet variable node i ' ∈ R _ji | L ^(k)(q _{i ' j}) | minimum value;

5c) calculate all products meeting the sign bit of the LLR information of variable node i ' wherein, L ^(k)(q _{i ' j}) represent the LLR information of kth time iteration variations per hour node i ' transmit to check-node, sgn (L ^(k)(q _{i ' j})) represent and ask L ^(k)(q _{i ' j}) symbol, all sgn (L meeting variable node i ' ^(k)(q _{i ' j})) product.

5d) the updated value of calculation check node $L^{\left(k\right)}\left(r_{\mathrm{ji}}\right)=\mathrm{\α}\underset{i^{\′}\∈R_j\backslash i}{\mathrm{\Π}}\mathrm{sgn}\left(L^{\left(k\right)}\left(q_{i^{\′}j}\right)\right)\·\underset{i^{\′}\∈R_j\backslash i}{\min }\left(\right|L^{\left(k\right)}\left(q_{i^{\′}j}\right)\left|\right).$ Wherein, α is modifying factor, L ^(k)(r _ji) be the LLR information of the check-node j that kth time iterates to.

Step 6: the LLR information of check-node is shifted

The Rate Control information that encoded control module inputs according to decoder, exports corresponding code check and moves down the position of position and the depth information of displacement, the LLR information L of the check-node calculated in control data shift module step 5 ^(k)(r _ji) be shifted, for the renewal of variable node.

Step 7: variable node is upgraded.

After the displacement of the check-node LLR information described in step 6 completes, decoding enable signal becomes effectively again, now according to the encoded control parameter that encoded control module exports, upgrades, being implemented as follows of this step to variable node:

7a) calculate the LLR information of all check-node j ' and wherein, C (i) represents the set of all check-nodes be connected with variable node i, C (i) j represent the set of all check-nodes be connected with variable node i except check-node j, j ' ∈ C (i) j represent j ' be set C (i) the element of j, L ^(k)(r _{j ' i}) check-node j ' transmits to variable node i when representing kth time iteration LLR information, represent and ask all L meeting check-node j ' ^(k)(r _{j ' i}) and.

The RAM2 of corresponding code check 7b) exported according to encoded control module reads address information, exports in RAM2 the initial value L (P of the variable node stored _i);

7c) calculate the LLR information of the variable node that kth time iteration obtains wherein L ^(k)(q _ij) represent the LLR information of the variable node i that kth time iteration obtains.

Step 8: variable node is shifted.

The shift position of the corresponding code check exported according to encoded control module and displacement depth information, be shifted the LLR information of the variable node calculated in step 7, for the renewal of check-node in decoding iteration process next time.

Step 9: repeat step 5 ~ 8, carry out decoding iteration process next time.

Step 10: decoding is adjudicated.

When iterations k reaches the maximum iteration time h of setting, calculate the hard decision information of all variable nodes, carry out hard decision and court verdict is carried out buffer memory, being implemented as follows of this step:

10a) according to decoding iteration complete enable signal calculate all check-node LLR information and wherein j ∈ C (i) represents that j is the element in set C (i), represent and solve all L meeting check-node j ^(k)(r _ji) and.

Variable node initial value L (P 10b) stored in Sequential output RAM2 _i).

10c) calculate hard decision information.

When reaching the highest decoding iteration number of times h, according to formula calculate the hard decision information L of all variable nodes ^(h)(q _i).

10d) decoding judgement.

According to step 10c) the hard decision information L that calculates ^(h)(q _i) carry out decoding judgement, if L ^(h)(q _i)>=0, then otherwise therefore, L ^(h)(q _i) sign bit as its decoding judgement export.

10e) by step 10d) in the court verdict that obtains carry out buffer memory, export for decoding.

Step 11: decoding exports.

The order of adjustment discriminative information, exports decode results according to the order corresponding with decoder input sequence.Meanwhile, decoding enable signal becomes effectively;

Step 12: repeat step 3 ~ 11 pair next frame data and carry out decoding.

Embodiment

Effect of the present invention further illustrates by following simulation result:

1. simulated conditions

For the long frame of LDPC code in DVB-S2 standard and short frame, simulated channel adopts awgn channel.The code length N=64800 of long frame, the code length N=16200 of short frame, iterations h are 20 times, and ldpc code decoder structure employing degree of parallelism is the Partly parallel decoding structure of 180, adopts normalization minimum-sum algorithm (NMSA), modifying factor α=0.875.

2. emulate content and result

For the long frame of LDPC code in DVB-S2 standard, under identical decoding algorithm condition, obtain floating number ldpc decoder emulation that MATLAB realizes and ldpc decoder FPGA of the present invention respectively and download the curve that the error rate in two kinds of situations changes with signal to noise ratio, different code check result as shown in Figure 3, Figure 4.Under Fig. 5 and Fig. 6 furthermore present short frame bar part, the emulation of MATLAB floating-point and FPGA of the present invention download test result.

Table 1 is for the ldpc decoder comprehensive resources service condition explanation of DVB-S2 standard

As can be seen from the emulation of table 1 comprehensive resources service condition and Fig. 3, Fig. 4, Fig. 5 and Fig. 6, the simulation curve that the FPGA hardware implementing of ldpc code decoder of the present invention realizes with the MATLAB of ldpc code decoder overlaps substantially, comparatively floating-point arithmetic loss is less than 0.1dB, and the calculating throughput based on 100MHz work clock data reaches as high as 132Mbps.Meanwhile, a series of resource optimization strategies for DVB-X2 standard that the present invention adopts, make the FPGA of algorithm realize the look-up table resource before comparatively optimizing and memory resource has had minimizing by a relatively large margin.Illustrate that the present invention is under the condition of lower decoding complexity, has good error performance.

The above; be only the present invention's preferably embodiment; protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the present invention discloses, the simple change of the technical scheme that can obtain apparently or equivalence are replaced and are all fallen within the scope of protection of the present invention.

Claims (6)

1. an implementation method for part parallel ldpc decoder, is characterized in that,

Comprise the following steps:

1) order adjustment is carried out to the log-likelihood ratio LLR information flow be input in decoder, obtain LLR information flow a;

2) by step 1) described in LLR information flow a be converted to 180 parallel circuit-switched data, be stored in first memory RAM1, after frame data finish receiving, by the data conversion storage in first memory RAM1 in second memory RAM2;

3) again input data are deposited in first memory RAM1 when next frame data arrives, simultaneously, the Rate Control information that encoded control module inputs according to decoder, what export second memory RAM2 under corresponding code check reads address information, export the data in second memory RAM2, obtain LLR information flow b, the LLR information of its corresponding variable node i is L (P _i), p _irepresent the probabilistic information of variable node i;

4) the Rate Control information that encoded control module inputs according to decoder, exports the encoded control information of corresponding code check, and LLR information flow b is shifted by control data shift module, obtains the initial value L of variable node ⁽⁰⁾(q _ij), q _ijrepresent that variable node i passes to the outside probabilities information of check-node j;

5) when decoding enable signal is effective, according to the encoded control parameter of the corresponding code check that encoded control module exports, upgrade check-node, the more new formula of check-node is as follows:

$L^{\left(k\right)}\left(r_{\mathrm{ji}}\right)=\mathrm{\α}\underset{i^{\′}\∈R_j\backslash i}{\mathrm{\Π}}\mathrm{sgn}\left(L^{\left(k\right)}\left(q_{i\′j}\right)\right)\·\underset{i^{\′}\∈R_j\backslash i}{\min }\left(\right|L^{\left(k\right)}\left(q_{i^{\′}j}\right)\left|\right),$

Wherein k is the iterations of decoding, and initial value is 0, α is modifying factor, R _jrepresent the set of all variable nodes be connected with check-node j, R _ji represent the set of all variable nodes be connected with check-node j except variable node i, i ' ∈ R _ji represent i ' be set R _jelement in i, L ^(k)(r _ji) be the LLR information of the check-node j that kth time iteration obtains, r _jirepresent that check-node j passes to the outside probabilities information L of variable node i ^(k)(q _{i ' j}) represent the LLR information of kth time iteration variations per hour node i ' transmit to check-node j, q _{i ' j}represent that variable node i ' passes to the outside probabilities information of check-node j, sgn (L ^(k)(q _{i ' j})) represent and ask L ^(k)(q _{i ' j}) symbol, represent and ask all sgn (L meeting variable node i ' ^(k)(q _{i ' j})) product, | L ^(k)(q _{i ' i}) | represent L ^(k)(q _{i ' j}) absolute value, represent to obtain and allly meet variable node i ' ∈ R _ji | L ^(k)(q _{i ' j}) | minimum value;

6) according to the encoded control parameter that encoded control module exports, usage data shift module is by step 5) in the LLR information of check-node that calculates be shifted, for the renewal of variable node;

7) when step 6) described in the displacement of check-node LLR information complete after, decoding enable signal becomes effectively again, now according to the encoded control parameter that encoded control module exports, upgrade variable node, the more new formula of variable node is as follows:

$L^{\left(k\right)}\left(q_{\mathrm{ij}}\right)=L\left(P_i\right)+\underset{j^{\′}\∈C\left(i\right)\backslash j}{\mathrm{\Σ}}{L}^{\left(k\right)}\left(r_{j^{\′}i}\right),$

Wherein C (i) represents the set of all check-nodes be connected with variable node i, C (i) j represent the set of all check-nodes be connected with variable node i except check-node j, j ' ∈ C (i) j represent j ' be set C (i) the element of j, L ^(k)(q _ij) represent the LLR information of the variable node i that kth time iteration obtains, L ^(k)(r _{j ' i}) check-node j ' transmits to variable node i when representing kth time iteration LLR information, r _{j ' i}represent that check-node j ' passes to the outside probabilities information of variable node i, represent and ask all L meeting check-node j ' ^(k)(r _{j ' i}) and;

8) according to the encoded control parameter that encoded control module exports, usage data shift module is by step 7) in the LLR information of variable node that calculates be shifted, for the renewal of check-node in decoding iteration process next time;

9) iterations k increases by 1, repeats step 5) ~ 8), carry out decoding iteration process next time;

10) when iterations k reaches the maximum iteration time h of setting, calculate the hard decision information of all variable nodes, carry out hard decision and court verdict is carried out buffer memory, its computing formula is as follows:

$L^{\left(h\right)}\left(q_i\right)=L\left(P_i\right)+\underset{j\∈C\left(i\right)}{\mathrm{\Σ}}{L}^{\left(h\right)}\left(r_{\mathrm{ji}}\right)$

Wherein j ∈ C (i) represents that j is the element in set C (i), represent and solve all L meeting check-node j ^(k)(r _ji) and, r _jirepresent that check-node j passes to the outside probabilities information of variable node i;

11) adjust the order of discriminative information, according to the order corresponding with decoder input sequence, decode results is exported; Meanwhile, decoding enable signal becomes effectively;

12) step 3 is repeated) ~ 11) decoding is carried out to next frame data.

2. the implementation method of part parallel ldpc decoder according to claim 1, it is characterized in that, wherein step 3), step 4), step 5), step 6), step 7) and step 8) described in encoded control module, use a larger ROM to store the decoding parameter of different code check, the encoded control parameter that encoded control module exports mainly comprises: the enable signal that the shift position of the shift position of the enable parameter of decoding, data shifts module and the degree of depth of displacement, data shifts module occurs first and data memory module RAM2 read address.

3. the implementation method of part parallel ldpc decoder according to claim 1, it is characterized in that, wherein step 4), step 6) and step 8) described in data shifts module, it realizes the output that have employed conditional parallel mode control data shift module, improves the hard-wired maximum functional clock of ldpc decoder FPGA.

4. the implementation method of part parallel ldpc decoder according to claim 1, is characterized in that, wherein said step 5) in the renewal process of check-node, carry out as follows:

5a) calculate the absolute value of the LLR information of all variable nodes | L ^(k)(q _ij) |;

5b) calculate all minimum values meeting the LLR information of variable node i '

5c) calculate all products meeting the sign bit of the LLR information of variable node i '

5d) the updated value of calculation check node $L^{\left(k\right)}\left(r_{\mathrm{ji}}\right)=\mathrm{\α}\underset{i^{\′}\∈R_j\backslash i}{\mathrm{\Π}}\mathrm{sgn}\left(L^{\left(k\right)}\left(q_{i\′j}\right)\right)\·\underset{i^{\′}\∈R_j\backslash i}{\min }\left(\right|L^{\left(k\right)}\left(q_{i^{\′}j}\right)\left|\right).$

5. the implementation method of part parallel ldpc decoder according to claim 1, is characterized in that, wherein said step 7) in the renewal process of variable node, carry out as follows:

7a) calculate the LLR information of all check-node j ' and

Control information 7b) exported according to encoded control module exports the initial value L (P of the variable node stored in RAM2 _i);

7c) calculate the LLR information of the variable node that kth time iteration obtains

6. the implementation method of part parallel ldpc decoder according to claim 1, is characterized in that, wherein said step 10) in the calculating of hard decision information, carry out as follows:

10a) according to decoding iteration complete enable signal calculate all check-node LLR information and

Variable node initial value L (P 10b) stored in Sequential output RAM2 _i);

10c) calculate the hard decision information of all variable nodes

10d) according to step 10c) the hard decision information L that calculates ^(h)(q _i) sign bit carry out decoding judgement;

10e) by step 10d) in the discriminative information that obtains carry out buffer memory, export for decoding.