CN103152057A - Low density parity check code (LDPC) decoder and decoding method based on double normalization correction factors - Google Patents

Abstract

The invention provides a low density parity check code (LDPC) decoder and a decoding method based on double normalization correction factors. A decoder circuit comprises a information channel data memory module, a variable node extrinsic information data memory module, a detecting operation module based on double normalization correction factors of Lambada 1 and Lambada 2, a detecting node extrinsic information data memory module, a variable operation module and an output module. The decoder utilizes the decoding method of the double normalization correction factors of the Lambada 1 and the Lambada 2, wherein the first correction factor Lambada 1 can conduct normalization correction to minimum values which are calculated and obtained from the detecting operation units, the second correction factor Lambada 2 can conduct normalization correction to the minimum values which are calculated and obtained from the detecting operation units. The double normalization correction factors of the Lambada 1 and the Lambada 2 are obtained by calculating mean values of detecting node operation results of a minimum sum algorithm and a confidence transmission algorithm. The LDPC decoder improves error rate property of the decoder on the premise that circuit complex degree is not changed.

Description

A kind of ldpc decoder and interpretation method based on two normalization modifying factors

Technical field

The present invention relates to a kind of decoder and a kind of interpretation method, relate in particular to a kind of ldpc decoder structure based on two normalization modifying factors and a kind of interpretation method.

Background technology

Along with the renewal, higher requirement of people to communication, the sustained and rapid development of wireless and mobile communication application, study and use of the new technology to improve the availability of frequency spectrum of radio communication, maximally utilise various resources, for tomorrow requirement provides the high capacity communication ability, it is the study hotspot of global radio communication technical field.

LDPC (Low Density Parity Check Code, low density parity check code are called for short " LDPC ") is proposed in 1962 by R.Gallager the earliest.But after this ignored by people for a long time, until 1996 by the people such as Mkay, Neal " discovery " again.The LDPC code is a kind of block code based on Sparse Parity-check Matrix, can provide approximately 8dB or higher coding gain when adopting belief propagation algorithm to carry out decoding, can be used for greatly reducing the transmitted power of wireless device and reduce antenna size.Because the LDPC code has excellent properties near shannon limit, and have advantages of that decoding complexity is low, the decoding throughput is high, extremely be convenient to hardware and realize, this makes it become gradually the focus of research and application.The decoder architecture of two normalization corrections, its hardware implementation complexity is low, the bit error rate performance of decoding is near belief propagation algorithm, has great Practical significance.But existing decoder circuit is complicated, and the error rate is higher.

Summary of the invention

In order to overcome above-mentioned the deficiencies in the prior art, the invention provides a kind of ldpc decoder based on two normalization modifying factors, comprise

The channel data memory module is used for the receive channel data, and channel data is inputed to variable node extrinsic information data memory module and variable computing module;

Variable node extrinsic information data memory module is used for variable node extrinsic information data and variable node bit information data that receive channel data and variable computing module are exported;

The verification computing module, be used for receiving variable node extrinsic information data and variable node information bit data, and export the check-node extrinsic information data to check-node extrinsic information data memory module, described verification computing module carries out parity check with variable node information bit data, and exports the parity check result to output module;

Check-node extrinsic information data memory module, be used for receiving the data of described verification computing module output and the data of described verification computing module output are carried out buffer memory, described check-node extrinsic information data memory module exports data to described variable computing module;

Described variable computing module, be used for receiving the data that described check-node extrinsic information data memory module output data and described channel data memory module are exported, and produce variable node extrinsic information data and variable node bit information data, and export variable node extrinsic information data and variable node bit information data to described variable node extrinsic information data memory module;

Described output module, the bit information data that are used for controlling the output variable node according to parity check result and the iterations of described verification arithmetic element output are to the circuit outside.

Further improvement of the present invention is, described verification computing module comprises a plurality of verification arithmetic elements and doubles the correction arithmetic element of verification arithmetic element, described verification arithmetic element produces minimum value and two outputs of sub-minimum, each verification arithmetic element is connected with 2 described correction arithmetic elements, and described correction arithmetic element is completed respectively the correction computing to described minimum value and described sub-minimum.

Further improvement of the present invention is that first amending unit that wherein is connected in the verification arithmetic element utilizes normalization modifying factor λ ₁The minimum value that calculates in described verification arithmetic element is carried out the normalization correction, and wherein second amending unit utilizes normalization modifying factor λ ₂The sub-minimum that calculates in described verification arithmetic element is carried out the normalization correction, described minimum value and sub-minimum produce the check-node extrinsic information data respectively after the correction of two correction arithmetic elements, described correction arithmetic element is carried out multiplication correction or subtraction correction, or carries out the correction based on multiplication, subtraction.

Further improvement of the present invention is, described channel data memory module is inputted channel data described variable computing module in interative computation, channel data being inputed to described variable node extrinsic information data memory module and described variable computing module for the first time in other interative computations.

Further improvement of the present invention is, described variable node extrinsic information data memory module, variable node extrinsic information data and the variable node bit information data of the channel data of receive channel data memory module output and the output of described variable computing module in interative computation for the first time receive variable node extrinsic information data and the variable node bit information data of described variable computing module output in other interative computations.

Further improvement of the present invention is, described λ ₁, λ ₂Satisfy following formula:

${\mathrm{\λ}}_1=\frac{E\left(\right|z_4\left|\right)}{E\left(\right|z_2\left|\right)}$

${\mathrm{\λ}}_2=\frac{E\left(\right|z_3\left|\right)}{E\left(\right|z_1\left|\right)}$

E|z ₁|, E|z ₂|, E|z ₃| and E|z ₄| for | z ₁|, | z ₂|, | z ₃| and | z ₄| average

Minimum-and algorithm in, the renewal operation table of check-node is shown:

$L\left(r_{\mathrm{ij}}\right)=\left\{\begin{array}{cc}\underset{i\∈V_j\backslash {\mathrm{indx}}_{j1}}{\min }\left\{\right|L\left(q_{\mathrm{ij}}\right)\left|\right\}=\min \_2{\mathrm{nd}}_j=z_1& i={\mathrm{indx}}_{j1}\\ \underset{i\∈V_j\backslash {\mathrm{indx}}_{j1}}{\min }\left\{\right|L\left(q_{\mathrm{ij}}\right)\left|\right\}=\left|L\left(q_{{\mathrm{indx}}_{j1}j}\right)\right|=\min \_1{\mathrm{st}}_j=z_2& i\≠{\mathrm{indx}}_{j1}\end{array}\right.$

In belief propagation algorithm, the renewal operation table of check-node is shown:

$L\left(r_{\mathrm{ji}}\right)\left\{\begin{array}{cc}\underset{i\∈{\mathrm{Vj}\backslash \mathrm{indx}}_{j1}}{\mathrm{\Π}}{a}_{\mathrm{ij}}\·2{\tanh }^{-1}\left(\underset{i\∈{\mathrm{Vj}\backslash \mathrm{indx}}_{j1}}{\mathrm{\Π}}\tanh \left(\frac{\left|L\left(q_{\mathrm{ij}}\right)\right|}{2}\right)\right)=z_3& i={\mathrm{indx}}_{j1}\\ \underset{i^{\′}\≠{\mathrm{indx}}_{j1},i\∈V_j\backslash i^{\′}}{\mathrm{\Π}}{a}_{\mathrm{ij}}\·{2\tanh }^{-1}\left(\underset{i^{\′}\≠{\mathrm{indx}}_{j1},i\∈V_j\backslash i^{\′}}{\mathrm{\Π}}\tanh \left(\frac{\left|L\left(q_{\mathrm{ij}}\right)\right|}{2}\right)\right)=z_4& i\≠{\mathrm{indx}}_{j1}\end{array}\right.$

Definition integer j satisfies 0≤j≤M-1, and integer i satisfies 0≤i≤N-1;

C=[c ₀, c ₁..., c _N-1]: the binary bit sequence that information source is sent;

r _ji(b): work as c _iDuring=b, j the probability that check equations is satisfied, wherein b ∈ { 0,1};

L(r _ji): check-node extrinsic information data, L (r _ji)=ln[r _ji(0)/r _ji(1)];

q _ij(b): when j check equations is satisfied, c _iThe probability of=b;

L(q _ij): variable node extrinsic information data, L (q _ij)=ln[q _ij(0)/q _ij(1)];

a _ij: L (q _ij) symbol;

V _j: the set of the variable node that is connected with j check-node;

V _jI: the set of the variable node that is connected with j check-node, remove variable node i;

Indx _j1: V _jThe position of middle minimum value.

A kind of use is the interpretation method of decoder as mentioned above, comprise buffer memory channel data, interative computation and three steps of data output, it is characterized in that: described interative computation step further comprises verification computing and variable computing, described verification computing comprises according to check matrix calculates minimum value and sub-minimum in correlated variables node extrinsic information data, and the result of described minimum value and sub-minimum is adopted respectively two normalization modifying factor λ ₁And λ ₂After revising, result is carried out buffer memory.

Further improvement of the present invention is, described verification computing module comprises a plurality of verification arithmetic elements and doubles the correction arithmetic element of verification arithmetic element, described verification arithmetic element produces minimum value and two outputs of sub-minimum, each verification arithmetic element is connected with 2 described correction arithmetic elements, described correction arithmetic element is completed respectively the correction computing to described minimum value and described sub-minimum, and first amending unit that wherein is connected in the verification arithmetic element utilizes normalization modifying factor λ ₁The minimum value that calculates in described verification arithmetic element is carried out the normalization correction, and wherein second amending unit utilizes normalization modifying factor λ ₂The sub-minimum that calculates in described verification arithmetic element is carried out the normalization correction.Described minimum value and sub-minimum produce the check-node extrinsic information data respectively after the correction of two correction arithmetic elements,

Further improvement of the present invention is, described channel data memory module is inputted channel data described variable computing module in interative computation, channel data being inputed to described variable node extrinsic information data memory module and described variable computing module for the first time in other interative computations.

Further improvement of the present invention is, described variable node extrinsic information data memory module, variable node extrinsic information data and the variable node bit information data of the channel data of receive channel data memory module output and the output of described variable computing module in interative computation for the first time receive variable node extrinsic information data and the variable node bit information data of described variable computing module output in other interative computations.

Compared to prior art, a kind of ldpc decoder structure and check-node arithmetic element in a kind of interpretation method based on two normalization modifying factors of the present invention adopts two normalization modifying factor λ ₁And λ ₂Minimum value and sub-minimum that computing is produced carry out the normalization correction.Decoder of the present invention is guaranteeing to have improved the bit error rate performance of decoder under the constant prerequisite of circuit complexity.

Description of drawings

Fig. 1 is the ldpc decoder structured flowchart that the present invention is based on two normalization modifying factors.

Fig. 2 is data input step schematic diagram of the present invention.

Fig. 3 is interative computation step schematic diagram of the present invention.

Fig. 4 is verification calculation step schematic diagram of the present invention.

Fig. 5 is variable calculation step schematic diagram of the present invention.

Fig. 6 is data output step schematic diagram of the present invention.

Embodiment

The present invention is further described below in conjunction with description of drawings and embodiment.

See also Fig. 1 and Fig. 2, the invention provides a kind of ldpc decoder based on two normalization modifying factors and a kind of interpretation method.Described ldpc decoder based on two normalization modifying factors comprises channel data memory module 11, variable node extrinsic information data memory module 13, verification computing module 15, check-node extrinsic information data memory module 17, variable computing module 19 and output module 21.

Described channel data memory module 11 is connected in variable node extrinsic information data memory module 13 and variable computing module 19, be used for the receive channel data, and in interative computation, channel data being inputed to described variable node extrinsic information data memory module 13 and described variable computing module 19 for the first time, channel data is inputed to described variable computing module 19 in other interative computations.

The channel data of described variable node extrinsic information data memory module 13 receive channel data memory module 11 outputs in interative computation for the first time and variable node extrinsic information data and the variable node bit information data of described variable computing module 19 outputs receive variable node extrinsic information data and the variable node bit information data of described variable computing module 19 outputs in other interative computations.Described variable node extrinsic information data memory module 13 exports variable node extrinsic information data and variable node bit information data to described verification computing module 15, and described variable node extrinsic information data memory module 13 exports variable node bit information data to described output module 21.

Described channel data is that the binary bits data that receive are 0 and are 1 posterior probability likelihood ratio; Described variable node extrinsic information data is, under the condition that the check equations at the corresponding binary bits of this variable node place is satisfied, the value of this binary bits is 0 and is 1 posterior probability likelihood ratio; Described check-node extrinsic information data is that the binary bits of investigating is 0 and is 1 o'clock, the ratio of the probability that check equations is satisfied; In each iteration, variable node carries out hard decision to the value of corresponding binary bits, and the result of hard decision is called variable node bit information data.

Described verification computing module 15 receives variable node extrinsic information data and the variable node information bit data of described variable computing module 19 outputs, described verification computing module 15 comprises k verification arithmetic element 151 and 2k correction arithmetic element 153, described verification arithmetic element 151 produces minimum value and two outputs of sub-minimum, described verification arithmetic element 151 is connected with 2 described correction arithmetic elements 153, described correction arithmetic element 153 is completed respectively the correction computing to described minimum value and described sub-minimum, and wherein first amending unit utilizes normalization modifying factor λ ₁The minimum value that calculates in described verification arithmetic element 151 is carried out the normalization correction, and wherein second amending unit utilizes normalization modifying factor λ ₂The sub-minimum that calculates in described verification arithmetic element 151 is carried out the normalization correction.Described minimum value and sub-minimum are revised through two respectively and are produced the check-node extrinsic information data after arithmetic element 153 is revised, and described verification computing module 15 exports the check-node extrinsic information data to check-node extrinsic information data memory module 17.Described verification computing module 15 carries out parity check with variable node information bit data, exports the parity check result to output module 21.

Described check-node extrinsic information data memory module 17 receives described verification computing module 15 output data and described verification computing module 15 output data is carried out buffer memory, and described check-node extrinsic information data memory module 17 exports data to described variable computing module 19.

the data that the described variable computing module 19 described check-node extrinsic information data memory module 17 output data of reception and described channel data memory module 11 are exported, described variable computing module 19 computings produce the variable node extrinsic information data, the value of 19 pairs of corresponding binary bits of described variable computing module is carried out hard decision, produce described variable node bit information data, described variable computing module 19 exports the variable node extrinsic information data to described variable node extrinsic information data memory module 13, the bit information data that described output module 21 is controlled the output variable node according to parity check result and the iterations of described verification arithmetic element 151 outputs are outside to circuit.

The present invention has provided a kind of couple of normalization modifying factor λ ₁And λ ₂The generation method, comprise the following steps: at first the computing with check-node in the decoding computing is divided into two parts, wherein first is the corresponding check-node computing when being minimum value of input data, the computing of check-node when second portion is other situation, minimum-and algorithm and belief propagation algorithm in utilize respectively Monte-Carlo Simulation to draw average to described two parts operation result, the average of utilizing first's operation result in belief propagation algorithm with minimum-with algorithm in the ratio calculation of average of first's operation result draw normalization modifying factor λ ₁Numerical value, the average of utilizing second portion operation result in belief propagation algorithm with minimum-and algorithm in the ratio calculation of average of second portion operation result draw normalization modifying factor λ ₂Numerical value.

The parity matrix of supposing the LDPC code is M * N matrix, and definition integer j satisfies 0≤j≤M-1, and integer i satisfies 0≤i≤N-1;

C=[c ₀, c ₁..., c _N-1]: the binary bit sequence that information source is sent;

r _ji(b): work as c _iDuring=b, j the probability that check equations is satisfied, wherein b ∈ { 0,1};

L(r _ji): check-node extrinsic information data, L (r _ji)=ln[r _ji(0)/r _ji(1)];

q _ij(b): when j check equations is satisfied, c _iThe probability of=b;

L(q _ij): variable node extrinsic information data, L (q _ij)=ln[q _ij(0)/q _ij(1)];

a _ij: L (q _ij) symbol;

V _j: the set of the variable node that is connected with j check-node;

V _jI: the set of the variable node that is connected with j check-node, remove variable node i;

Indx _j1: V _jThe position of middle minimum value;

Minimum-and algorithm in, the renewal operation table of check-node is shown:

$L\left(r_{\mathrm{ij}}\right)=\left\{\begin{array}{cc}\underset{i\∈V_j\backslash {\mathrm{indx}}_{j1}}{\min }\left\{\right|L\left(q_{\mathrm{ij}}\right)\left|\right\}=\min \_2{\mathrm{nd}}_j=z_1& i={\mathrm{indx}}_{j1}\\ \underset{i\∈V_j\backslash {\mathrm{indx}}_{j1}}{\min }\left\{\right|L\left(q_{\mathrm{ij}}\right)\left|\right\}=\left|L\left(q_{{\mathrm{indx}}_{j1}j}\right)\right|=\min \_1{\mathrm{st}}_j=z_2& i\≠{\mathrm{indx}}_{j1}\end{array}\right.$

In belief propagation algorithm, the renewal operation table of check-node is shown:

$L\left(r_{\mathrm{ji}}\right)\left\{\begin{array}{cc}\underset{i\∈{\mathrm{Vj}\backslash \mathrm{indx}}_{j1}}{\mathrm{\Π}}{a}_{\mathrm{ij}}\·2{\tanh }^{-1}\left(\underset{i\∈{\mathrm{Vj}\backslash \mathrm{indx}}_{j1}}{\mathrm{\Π}}\tanh \left(\frac{\left|L\left(q_{\mathrm{ij}}\right)\right|}{2}\right)\right)=z_3& i={\mathrm{indx}}_{j1}\\ \underset{i^{\′}\≠{\mathrm{indx}}_{j1},i\∈V_j\backslash i^{\′}}{\mathrm{\Π}}{a}_{\mathrm{ij}}\·{2\tanh }^{-1}\left(\underset{i^{\′}\≠{\mathrm{indx}}_{j1},i\∈V_j\backslash i^{\′}}{\mathrm{\Π}}\tanh \left(\frac{\left|L\left(q_{\mathrm{ij}}\right)\right|}{2}\right)\right)=z_4& i\≠{\mathrm{indx}}_{j1}\end{array}\right.$

Utilize Monte-Carlo Simulation to draw data | z ₁|, | z ₂|, | z ₃| and | z ₄| average E|z ₁|, E|z ₂|, E|z ₃| and E|z ₄|, pass through formula:

${\mathrm{\λ}}_1=\frac{E\left(\right|z_4\left|\right)}{E\left(\right|z_2\left|\right)}$

${\mathrm{\λ}}_2=\frac{E\left(\right|z_3\left|\right)}{E\left(\right|z_1\left|\right)}$

Calculate modifying factor λ ₁And λ ₂Numerical value.

The present invention has provided a kind of interpretation method based on two normalization modifying factors, the LDPC interpretation method of described pair of normalization correction comprises buffer memory channel data, interative computation and three steps of data output, described channel data buffer memory step is completed the caching function to channel data, as shown in Figure 2, the buffer memory step of channel data is mainly completed by channel data memory module 11.

Described interative computation comprises verification computing and variable computing, as shown in Figure 3, the interative computation step is mainly completed by channel data memory module 11, output module 21, verification computing module 15, variable computing module 19, check-node extrinsic information data memory module 17 and variable node extrinsic information data memory module 13, and described interative computation step is mainly by described verification computing and variable computing two parts.

As shown in Figure 4, the verification computing is mainly completed by verification computing module 15, variable node extrinsic information data memory module 13 and check-node extrinsic information data memory module 17.Described verification computing comprises according to check matrix calculates minimum value and sub-minimum in correlated variables node extrinsic information data, and the result of described minimum value and sub-minimum is adopted respectively two normalization modifying factor λ ₁And λ ₂After revising, the check-node extrinsic information data that draws is carried out buffer memory in described check-node extrinsic information data memory module 17.

As shown in Figure 5, the variable computing is mainly completed by variable computing module 19, check-node extrinsic information data memory module 17 and variable node extrinsic information data memory module 13.Described variable computing comprise according to test matrix will be correlated with the check-node extrinsic information data add and after draw the variable node extrinsic information data, simultaneously the value of corresponding binary bits is carried out hard decision, draw variable node bit information data, afterwards the buffer memory in described variable node extrinsic information data memory module 13 with described amount node extrinsic information data and described variable node bit information data.

Described data output step is exported decode results, and as shown in Figure 6, data output is mainly completed by output module 21 and variable node extrinsic information data.

The present invention is a kind of based on two normalization modifying factor λ ₁And λ ₂Ldpc decoder and interpretation method in the check-node arithmetic element adopt two normalization modifying factor λ ₁And λ ₂Minimum value and sub-minimum that computing is produced carry out the normalization correction.Decoder of the present invention is guaranteeing to have improved the bit error rate performance of decoder under the constant prerequisite of circuit complexity.

Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.

Claims (10)

1. the ldpc decoder based on two normalization modifying factors, is characterized in that: comprise

The channel data memory module is used for the receive channel data, and channel data is inputed to variable node extrinsic information data memory module and variable computing module;

Variable node extrinsic information data memory module is used for variable node extrinsic information data and variable node bit information data that receive channel data and variable computing module are exported;

The verification computing module, be used for receiving variable node extrinsic information data and variable node information bit data, and export the check-node extrinsic information data to check-node extrinsic information data memory module, described verification computing module carries out parity check with variable node information bit data, and exports the parity check result to output module;

Check-node extrinsic information data memory module, be used for receiving the data of described verification computing module output and the data of described verification computing module output are carried out buffer memory, described check-node extrinsic information data memory module exports data to described variable computing module;

Described variable computing module, be used for receiving the data that described check-node extrinsic information data memory module output data and described channel data memory module are exported, and produce variable node extrinsic information data and variable node bit information data, and export variable node extrinsic information data and variable node bit information data to described variable node extrinsic information data memory module;

Described output module, the bit information data that are used for controlling the output variable node according to parity check result and the iterations of described verification arithmetic element output are to the circuit outside.

2. according to claim 1 based on the ldpc decoder of two normalization modifying factors, it is characterized in that: described verification computing module comprises a plurality of verification arithmetic elements and doubles the correction arithmetic element of verification arithmetic element, described verification arithmetic element produces minimum value and two outputs of sub-minimum, each verification arithmetic element is connected with 2 described correction arithmetic elements, and described correction arithmetic element is completed respectively the correction computing to described minimum value and described sub-minimum.

3. according to claim 2 based on the ldpc decoder of two normalization modifying factors, it is characterized in that: first amending unit that wherein is connected in the verification arithmetic element utilizes normalization modifying factor λ ₁The minimum value that calculates in described verification arithmetic element is carried out the normalization correction, and wherein second amending unit utilizes normalization modifying factor λ ₂The sub-minimum that calculates in described verification arithmetic element is carried out the normalization correction, described minimum value and sub-minimum produce the check-node extrinsic information data respectively after the correction of two correction arithmetic elements, described correction arithmetic element is carried out multiplication correction or subtraction correction, or carries out the correction based on multiplication, subtraction.

4. according to claim 1 based on the ldpc decoder of two normalization modifying factors, it is characterized in that: described channel data memory module is inputted channel data described variable computing module in interative computation, channel data being inputed to described variable node extrinsic information data memory module and described variable computing module for the first time in other interative computations.

5. according to claim 1 based on the ldpc decoder of two normalization modifying factors, it is characterized in that: described variable node extrinsic information data memory module, variable node extrinsic information data and the variable node bit information data of the channel data of receive channel data memory module output and the output of described variable computing module in interative computation for the first time receive variable node extrinsic information data and the variable node bit information data of described variable computing module output in other interative computations.

6. according to claim 1 based on the ldpc decoder of two normalization modifying factors, it is characterized in that: described λ ₁, λ ₂Satisfy following formula:

E|z ₁|, E|z ₂|, E|z ₃| and E|z ₄| for | z ₁|, | z ₂|, | z ₃| and | z ₄| average

Minimum-and algorithm in, the renewal operation table of check-node is shown:

In belief propagation algorithm, the renewal operation table of check-node is shown:

Definition integer j satisfies 0≤j≤M-1, and integer i satisfies 0≤i≤N-1;

C=[c ₀, c ₁..., c _N-1]: the binary bit sequence that information source is sent;

r _ji(b): work as c _iDuring=b, j the probability that check equations is satisfied, wherein b ∈ { 0,1};

L(r _ji): check-node extrinsic information data, L (r _ji)=ln[r _ji(0)/r _ji(1)];

q _ij(b): when j check equations is satisfied, c _iThe probability of=b;

L(q _ij): variable node extrinsic information data, L (q _ij)=ln[q _ij(0)/q _ij(1)];

a _ij: L (q _ij) symbol;

V _j: the set of the variable node that is connected with j check-node;

V _jI: the set of the variable node that is connected with j check-node, remove variable node i;

Indx _j1: V _jThe position of middle minimum value.

7. one kind is used the interpretation method of decoder as claimed in claim 1, comprise buffer memory channel data, interative computation and three steps of data output, it is characterized in that: described interative computation step further comprises verification computing and variable computing, described verification computing comprises according to check matrix calculates minimum value and sub-minimum in correlated variables node extrinsic information data, and the result of described minimum value and sub-minimum is adopted respectively two normalization modifying factor λ ₁And λ ₂After revising, result is carried out buffer memory.

8. interpretation method according to claim 7, it is characterized in that: described verification computing module comprises a plurality of verification arithmetic elements and doubles the correction arithmetic element of verification arithmetic element, described verification arithmetic element produces minimum value and two outputs of sub-minimum, each verification arithmetic element is connected with 2 described correction arithmetic elements, described correction arithmetic element is completed respectively the correction computing to described minimum value and described sub-minimum, and first amending unit that wherein is connected in the verification arithmetic element utilizes normalization modifying factor λ ₁The minimum value that calculates in described verification arithmetic element is carried out the normalization correction, and wherein second amending unit utilizes normalization modifying factor λ ₂The sub-minimum that calculates in described verification arithmetic element is carried out the normalization correction.Described minimum value and sub-minimum produce the check-node extrinsic information data respectively after the correction of two correction arithmetic elements.

9. interpretation method according to claim 1, it is characterized in that: described channel data memory module is inputted channel data described variable computing module in interative computation, channel data being inputed to described variable node extrinsic information data memory module and described variable computing module for the first time in other interative computations.

10. interpretation method according to claim 1, it is characterized in that: described variable node extrinsic information data memory module, variable node extrinsic information data and the variable node bit information data of the channel data of receive channel data memory module output and the output of described variable computing module in interative computation for the first time receive variable node extrinsic information data and the variable node bit information data of described variable computing module output in other interative computations.

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