CN101854179B - 5bit quantization method applied to LDPC decoding - Google Patents

Abstract

The invention provides a 5bit quantization method applied to LDPC decoding, and relates to a decoder for a communication channel. The method comprises the following steps of: based on an MS-offset algorithm, designing an information quantization expression method in a decoding process of an LDPC decoder, wherein the information quantization expression method is a corresponding conversion method mainly applied between a 5bit non-uniform quantization value and a 6bit uniform quantization value; and performing hardware design corresponding to the conversion method, thus ensuring that quantization decoding performance nearly in accordance with floating point decoding can be realized with few quantization bit number. Because the 5bit non-uniform quantization value is transmitted between a variable point calculation unit and a checkpoint calculation unit, the wiring complexity and the information memory overhead are reduced; and in the variable point calculation unit, the 5bit non-uniform quantization value is converted into the 6bit uniform quantization value and then operation is performed so as to enlarge the expression range of the quantization information and improve the decoding performance.

Description

A kind of 55 bit quantization methods that are applied to LDPC decoding

Technical field

The present invention relates to the decoder of communication channel, especially relate to a kind of LDPC of being primarily aimed at low density parity check code, be applied to 55 bit quantization methods of LDPC decoding.

Background technology

1962; Gallager (R.G.Gallager.Low-Density Parity-Check Codes.IRE Transon.Inform.Theory.1962, (8): 21-28) proposed low density parity check code (LDPC sign indicating number) first, the LDPC sign indicating number allows the parallel work-flow of height; Be applicable to the application of High Data Rate throughput; For example broadband radio multi-media communication and magnetic-memory system still because its decoding algorithm is too complicated, do not obtain enough attention.In these decoding algorithms, the performance of BP sum-product algorithm is relatively good, but the sum-product algorithm that is based on log-likelihood ratio information adopts hyperbolic tangent function as core calculations, and when hardware was realized, complexity was quite high.Therefore seeking a kind of alternate algorithm just seems extremely important, the MS-offset minimum-sum algorithm after for example simplifying, and this algorithm can greatly reduce the complexity of BP sum-product algorithm, and the decoding performance loss is very little.In addition, except the complexity of its main operational unit need reduce, when hardware was realized, the information quantization method for expressing of decode procedure also was the key point of design of encoder.

The summary of MS-offset decoding algorithm step:

Suppose to use y from the value of information that channel receives _iExpression, γ _nY is used in expression _iThe set of the variable point that the channel likelihood information value that calculates, N (m) expression are connected with checkpoint m, N (m) n represent except that variable point n the set of the variable point that is connected with checkpoint m.The set of the checkpoint that M (n) expression is connected with variable point n, M (n) m represent except that checkpoint m the set of the checkpoint that is connected with variable point n.L (r _Mn) expression passes to the value of information of variable point n from checkpoint m, offset is that the MS-offset algorithm approaches the offset that the BP sum-product algorithm will be used, L (q _Mn) expression passes to the value of information of checkpoint m from variable point n.L (q _n) expression information updating after, the posterior information of variable point.Concrete steps are following:

Initial Channel Assignment likelihood information value:

${\mathrm{\γ}}_n=\log \frac{{(1+e^{-2y_i/{\mathrm{\σ}}^2})}^{-1}}{{(1+e^{+2y_i/{\mathrm{\σ}}^2})}^{-1}}=2y_i/{\mathrm{\σ}}^2---\left(1\right)$

σ ²The variance of the additive white Gaussian noise of expression Gaussian channel.

Calculation check point m is to the information of variable point n:

$L\left(r_{\mathrm{mn}}\right)=\max (\underset{n^{\′}\∈N\left(m\right)\backslash n}{\min }\left(\right|L\left(q_{{\mathrm{mn}}^{\′}}\right)\left|\right)-\mathrm{offset},0)---\left(2\right)$

Calculate the information of variable point n to checkpoint m:

$L\left(q_{\mathrm{mn}}\right)={\mathrm{\γ}}_n+\underset{m^{\′}\∈M\left(n\right)\backslash m}{\mathrm{\Σ}}L\left(r_{m^{\′}n}\right)---\left(3\right)$

Calculate the posterior information of variable point at last:

$L\left(q_n\right)={\mathrm{\γ}}_n+\underset{m\∈M\left(n\right)}{\mathrm{\Σ}}L\left(r_{\mathrm{mn}}\right)---\left(4\right)$

Can find out that from above step at the iteration first half, all checkpoints receive external information, upgrade their information r then _Mn, at the latter half of iteration, all variable points receive external information, upgrade their information q then _Mn, calculate the posterior information q of variable point at last _nIf the code word that decoding is come out satisfies all check equations or iterations reaches the maximum that is provided with in advance, then decoding algorithm stops.

From (2), (3), (4) formula can see that the calculating that these 3 formulas are done all is that plus-minus calculates, if replace (1) with following formula:

γ _n＝y _i (5)

The offset that is equivalent in (1) (2) (3) (4) formula and (2) formula multiply by σ ²/ 2, because (2)～(4) formula all is to add reducing, therefore can not influence the judgement effect of formula (4) at all.When therefore we adopt the MS-offset algorithm to decipher, when the Initial Channel Assignment value of information, just directly use the value of information that receives from channel, shown in (5), and need not use formula (1) calculating channel likelihood value.

The quantization method of soft information is extremely important to its design of encoder during LDPC decoding; It is that decoder hardware is realized the key link that institute must consideration; In decode procedure; To the main especially design focus of quantization bit figure place (limited wordlength that is soft information is represented) that soft information is represented, the figure place of the quantization bit of information directly affects decoding performance and hardware resource expense during decoding.In general, in the LDPC decode procedure, adopt less quantization bit, during such as 5 bits or 6 bit quantization information expressing methods, quantize decoding has 0.1～0.2dB with respect to floating-point decoding decoding performance loss.

In general, the quantization means figure place of information is many more, and decoding performance is good more, but the hardware resource expense can increase, and quantization digit is few, and the hardware resource expense reduces, yet with respect to floating-point decoding, it is a lot of to quantize decoding performance meeting variation.Therefore, how when guaranteeing decoding performance, reducing quantization digit again as much as possible, is the key technical problem of ldpc decoder hardware when realizing, also is problem to be solved by this invention.

Uniform quantization is all to take same quantized interval for the signal value of input.Non-uniform quantizing is to confirm quantized interval according to the different intervals of input signal values size.Major part all adopts the uniform quantization method in decoder at present.The inventor finds in the process of the quantification decoding of LDPC sign indicating number; If in decode procedure, combine the uniform quantization of information and non-uniform quantizing, take the conversion of non-uniform quantizing value and uniform quantization value; Not only can reduce hardware memory resource; The wiring complexity reduces chip area, has also guaranteed to quantize decoding performance can't harm with respect to floating-point decoding.

Summary of the invention

When the objective of the invention is to guarantee decoding performance, a kind of 55 bit quantization methods of the LDPC of being applied to decoding are provided.

The present invention is mainly on the basis of MS-offset algorithm; Information quantization method for expressing in the decode procedure of design ldpc decoder; Wherein mainly use the corresponding conversion method between 5 bit non-uniform quantizing values and the 6 bit uniform quantization values; And with conversion method corresponding hardware design, guaranteed with less quantization bit figure place, just can reach and floating-point is deciphered almost consistent quantification decoding performance.

The present invention includes following steps:

1) distribution of the floating-point value of information that receives from channel of statistical decoding device is confirmed quantizing range and quantized interval with this;

2) the floating-point value of information that decoder is received from channel; According to step 1) definite quantizing range and quantized interval; Elder generation's uniform quantization is the value of 6 bits, again by its order of magnitude, adopts different quantized at interval; Convert the uniform quantization value of 6 bits the non-uniform quantizing value of 5 bits to by table 1, pass to the checkpoint computing unit to the non-uniform quantizing value of 5 bits then;

3) the checkpoint computing unit receives the non-uniform quantizing value of several 5 bits, according to calculation check point m to the formula of the information of variable point n (formula (2) in the scape technology of the passing away part):

$L\left(r_{\mathrm{mn}}\right)=\max (\underset{n^{\′}\∈N\left(m\right)\backslash n}{\min }\left(\right|L\left(q_{{\mathrm{mn}}^{\′}}\right)\left|\right)-\mathrm{offset},0),$

After they are finished computing, export the non-uniform quantizing value of 5 bits, pass to variable point computing unit;

4) variable point computing unit receives the non-uniform quantizing value of several 5 bits; By its order of magnitude; Adopt different quantized at interval; Convert the non-uniform quantizing value of 5 bits the uniform quantization value of 6 bits to by table 2, then according to calculating the formula of variable point n to the information of checkpoint m (the technological formula (3) in partly of the scape of passing away):

$L\left(q_{\mathrm{mn}}\right)={\mathrm{\γ}}_n+\underset{m^{\′}\∈M\left(n\right)\backslash m}{\mathrm{\Σ}}L\left(r_{m^{\′}n}\right),$

They are carried out computing, export the uniform quantization value of 6 bits equally, by its order of magnitude, adopt different quantized at interval, convert the uniform quantization value of 6 bits the non-uniform quantizing value of 5 bits to by table 1, pass to the checkpoint computing unit again;

The corresponding 5 bit non-uniform quantizing values of table 16 bit uniform quantization values

6bits	5bits	6bits	5bits	6bits	5bits	6bits	5bits
									0	0	16	12	0	0	-16	-12
1	1	17	12	-1	-1	17	-12

The corresponding 6 bit uniform quantization values of table 25 bit non-uniform quantizing values

5bits	6bits	5bits	6bits
					0	0	0	0
1	1	-1	-1
				2	2	-2	-2
3	3	-3	-3
				4	4	-4	-4
5	5	-5	-5
				6	6	-6	-6
7	7	-7	-7
				8	8	-8	-8
9	10	-9	-10
				10	12	-10	-12
11	14	-11	-14
				12	18	-12	-18
13	22	-13	-22
				14	26	-14	-26
15	30	-15	-30

In step 2)～4) in, the data format of said quantized value can be arranged as follows:

The highest order of quantization bit figure place is represented the symbol of this information; The value of highest order is 1; Be expressed as negatively, be 0 and just be expressed as, remaining figure place is represented the amplitude size of information; All quantized values all adopt complement form to represent, what therefore in ldpc decoder, transmit between each computing unit all is the quantized value of representing with complement form.

In step 2) and step 4) in, saidly convert the uniform quantization value of 6 bits the non-uniform quantizing value of 5 bits to by table 1, (this process) has two kinds of implementations:

1. adopt the LUT look-up table, realize with ROM, with the 6 bit uniform quantization values that the receive INADD as ROM, correspondence finds out the 5 bit non-uniform quantizing values that deposit the ROM the inside.In this implementation; Be to utilize ROM to realize the LUT look-up table equally; Hardware structure diagram is seen Fig. 2, and the V6 among the figure representes the INADD of 6 bit uniform quantization information as ROM, and V5 representes that ROM is according to INADD V6; 5 bit non-uniform quantizing information of the ROM storage of corresponding output, clk representes clock signal.

2. the employing logical circuit is described the conversion of 6 bit uniform quantization values to 5 bit non-uniform quantizing values.The hardware structure diagram of this implementation is seen Fig. 3, and the V6 among the figure representes that the 6 bit uniform quantization information imported, V5 represent through behind the logical circuit; 5 bit non-uniform quantizing information of output; Rest_n representes reset signal, and clk representes clock signal, and the line of overstriking is represented data/address bus.

In step 4), saidly convert the non-uniform quantizing value of 5 bits the uniform quantization value of 6 bits to by table 2, (this process) has two kinds of hardware implementations:

1. adopt the LUT look-up table, realize with ROM, with the 5 bit non-uniform quantizing values that the receive INADD as ROM, correspondence finds out the 6 bit uniform quantization values that deposit the ROM the inside.In this implementation; Utilize ROM to realize the LUT look-up table; Hardware structure diagram is seen Fig. 4, and the V5 among the figure representes the INADD of 5 bit non-uniform quantizing information as ROM, and V6 representes that ROM is according to INADD V5; 6 bit uniform quantization information of the ROM storage of corresponding output, clk representes clock signal.

2. the employing logical circuit is described the conversion of 5 bit non-uniform quantizing values to 6 bit uniform quantization values.The hardware structure diagram of this implementation is seen Fig. 5, and the V5 among the figure representes that the 5 bit non-uniform quantizing information imported, V6 represent through behind the logical circuit; 6 bit uniform quantization information of output; Rest_n representes reset signal, and clk representes clock signal, and the line of overstriking is represented data/address bus.

Because what between variable point computing unit and checkpoint computing unit, transmit is 5 bit non-uniform quantizing values; So wiring complexity and information memory cost all can reduce; And at variable point computing unit; Calculate again after converting the non-uniform quantizing value of 5 bits into the uniform quantization value of 6 bits, enlarged the expression scope of quantitative information, improved decoding performance.

Description of drawings

Fig. 1 is that SNR is 2.2 o'clock, the statistical chart of the value of information that receives from channel.In Fig. 1, a is that BPSK is modulated to 1, and b is that BPSK is modulated to-1; Abscissa is the distribution of channel value, and ordinate is the number of channel value.

Fig. 2 is the LUT realization that 6 bit uniform quantization values convert 5 bit non-uniform quantizing values to.In Fig. 2, V6 is the INADDs of 6 bit uniform quantization information as ROM, V5 be ROM according to INADD V6,5 bit non-uniform quantizing information of the ROM of corresponding output storage, clk is a clock signal.

Fig. 3 is the circuit diagram that 6 bit uniform quantization values convert 5 bit non-uniform quantizing values to.In Fig. 3, V6 is 6 bit uniform quantization information of input, and V5 is through behind the logical circuit, 5 bit non-uniform quantizing information of output, and rest_n is a reset signal, and clk is a clock signal, and the line of overstriking is represented data/address bus.

Fig. 4 is the LUT realization that 5 bit non-uniform quantizing values convert 6 bit uniform quantization values to.In Fig. 4, V5 is the INADDs of 5 bit non-uniform quantizing information as ROM, V6 be ROM according to INADD V5,6 bit uniform quantization information of the ROM of corresponding output storage, clk is a clock signal.

Fig. 5 is the circuit diagram that 5 bit non-uniform quantizing values convert 6 bit uniform quantization values to.In Fig. 5, V5 is 5 bit non-uniform quantizing information of input, and V6 is through behind the logical circuit, 6 bit uniform quantization information of output, and rest_n is a reset signal, and clk is a clock signal, and the line of overstriking is represented data/address bus.

Fig. 6 is a variable point computing unit structure chart.

Fig. 7 is variable point posterior information calculation cellular construction figure.

Fig. 8 is polygon LDPC floating-point decoding and the BER curve chart that quantizes decoding.In Fig. 8, abscissa is signal to noise ratio Eb/No (dB), and ordinate is the error rate (Bit Error Rate).

Embodiment

Below adopt RA Codes (referring to document: Divsalar D, Jin H, McEliece R.Coding theorems forTurbo-like codes [A] .Proc of the 36th Annual Allerton Conference on Communication Control andComputing [C] .Monticello; IL; USA, 1998,9:201-210.) with IRA Codes (referring to document: Jin H; KhandekarA; McEliece R.Irregular repeat-accumulated codes [A] .Proc.2nd Int.Symp.Turbo codes andRelated Topics [C] .Brest, France, 2000; 9:1-8.) a kind of polygon LDPC sign indicating number that composite construction goes out, specify embodiment of the present invention with its decode procedure.

Embodiment

If: an information sequence length is the LDPC sign indicating number of the polygon type of 640 bits, and 640 Bit datas of a frame are x ₀, x ₁..., x ₆₃₉The code check of coding is 0.5, is 1280 through the frame length behind the coding then, uses sequence c ₀, c ₁, c _iC ₁₂₇₉Expression.If adopt the BPSK modulation, the variable point c that behind coding, will transmit _iBeing 1 o'clock, through becoming-1 after the BPSK modulation, is 0 o'clock, then become after modulating through BPSK+1, through awgn channel, be transferred to the recipient.

In the LDPC of this polygon type sign indicating number, the computing unit of the variable point computing unit that the checkpoint computing unit, 3 that exists 2 inputs and 3 to import is imported and the variable point posterior information of 4 inputs.

One, the LDPC decode procedure of polygon type

After the recipient received information from awgn channel, decoder was started working, and establishing the channel information value that decoder receives is γ ₀, γ ₁γ ₁₂₇₉, according to the information that receives from awgn channel, statistics is 2.2 o'clock at SNR, the value of information of 200,000 bits, and statistics is seen Fig. 1.From Fig. 1, can see; The top of figure is that BPSK is modulated to+1 o'clock channel information value distribution situation, and the lower part is the channel information value distribution situation that BPSK was modulated to-1 o'clock, because the symmetry of AWGN; The channel information value that receives roughly is symmetrical distribution, therefore adopts symmetry to quantize to get final product.

In the channel signal to noise ratio is 2.2 o'clock, and through Fig. 1, the inventor observes channel information reception value mostly between the value of being distributed in (3.875 ,+3.875), so being set to of quantizing range (3.875,3.875), and quantized interval is set to 0.125.Sign bit representes with the highest order of quantized value, and 1 expression value is for negative, and 0 expression value is being for just, quantitative information employing complement representation form.

In polygon decoder, two main computing units are arranged, one is the checkpoint computing unit, is divided into two kinds of 2 inputs and 3 inputs.One is the variable point computing unit of 3 inputs.Concrete quantification decoding step is following:

1. initialization unit

The information that receives from channel is γ ₀, γ ₁γ ₁₂₇₉, change into the information even amount with 6 bit uniform quantization value u earlier ₀, u ₁, u _iU ₁₂₇₉, convert the quantized value of this 6 bit into by table 1 the non-uniform quantizing value v of 5 bits again ₀, v ₁, v _iV ₁₂₇₉, pass to each checkpoint computing unit then.

2. checkpoint computing unit:

Here the checkpoint computing unit with 3 inputs is an example.The checkpoint computing unit receives 35 bit non-uniform quantizing values, is expressed as v respectively ₁, v ₂, v ₃, according to formula (2), the offset offset here is set to 1, and the result who obtains representes with v, passes to variable point computing unit then.

Because the minimum value of getting also is the non-uniform quantizing value, therefore when deducting offset, need do following processing:

If 1. the order of magnitude of minimum value is between [0～7], then the absolute value of minimum value deducts offset.

If 2. the order of magnitude of minimum value is between [8～15], then the absolute value of minimum value is constant.

Attention: because the checkpoint computing unit is just got minimum value operation, so operate after need not the 5 bit non-uniform quantizing values that receive are transferred to the uniform quantization value.

3. variable point computing unit:

1) variable point computing unit receives 35 bit non-uniform quantizing values, is expressed as v respectively ₁, v ₂, v ₃, can know that by formula (3) what variable point computing unit carried out is add operation, therefore at first need be the non-uniform quantizing value v of 5 bits that receive ₁, v ₂, v ₃, convert the uniform quantization value u of 6 bits into by table 2 ₁, u ₂, u ₃

2) to the u after the step 1) conversion ₁, u ₂, u ₃Carry out add operation, the result who obtains after the calculating also is the uniform quantization value of representing with 6 bits, representes with u.

3) step 2) the 6 bit uniform quantization value u that obtain, convert the non-uniform quantizing value v of 5 bits into by table 1, pass to the checkpoint computing unit then.

The structure chart of variable point computing unit module is referring to Fig. 6.

4. variable point posterior information calculation unit:

The variable point receives 35 bit non-uniform quantizing values, convert 6 bit uniform quantization values into by table 2 after, add the value of information that the variable point receives from channel then; Result to addition adjudicates again; If the result is greater than 0, then the corresponding transmitted bit of judgement is 0, otherwise then judgement is 1.If the code word that decoding is come out satisfies all check equations or reaches the maximum iteration time that is provided with in advance, then decoding algorithm stops.

The modular structure figure of the variable point posterior information calculation unit of 4 inputs is referring to Fig. 7.

Two, polygon LDPC is the quantification decoding characteristics of example:

Here adopting with polygon LDPC is the quantification decoding scheme of example, has following characteristics:

1) conversion operations of correspondence between 5 bit non-uniform quantizing values that design and the 6 bit uniform quantization values makes the loss of significance and the saturated error loss that quantize decoding drop to minimum, and decoding performance is almost harmless with respect to the floating-point decoding performance.

2) simultaneously at hardware aspect; The hardware spending that conversion between 5 bit non-uniform quantizing values and the 6 bit uniform quantization values is used seldom; And in whole decode procedure, only need use comparison and add operation, quantized value transmits between the various computing module also only needs 5 data wire; Reduce the memory cost of wiring complexity, computation complexity and stored information, also reduced the actual hardware chip area.

Three, quantize the BER curve chart of decoding and floating-point decoding

Referring to Fig. 8, the floating-point decoding performance curve chart of the polygon LDPC of red expression, blue expression quantizes the decoding performance curve chart; Two curves can draw from figure; Adopt the performance of the quantification decoding of inventor's method for designing, decoding is compared with floating-point, does not almost have performance loss.

Claims (4)

1. one kind is applied to 55 bit quantization methods that LDPC deciphers, and it is characterized in that may further comprise the steps:

1) distribution of the floating-point value of information that receives from channel of statistical decoding device is confirmed quantizing range and quantized interval with this;

2) the floating-point value of information that decoder is received from channel; According to step 1) definite quantizing range and quantized interval; Elder generation's uniform quantization is the value of 6 bits, again by its order of magnitude, adopts different quantized at interval; Convert the uniform quantization value of 6 bits the non-uniform quantizing value of 5 bits to by table 1, pass to the checkpoint computing unit to the non-uniform quantizing value of 5 bits then;

Table 1

6bits 5bits 6bits 5bits 6bits 5bits 6bits 5bits 0 0 16 12 0 0 -16 -12 1 1 17 12 -1 -1 17 -12 2 2 18 12 -2 -2 -18 -12 3 3 19 12 -3 -3 -19 -12 4 4 20 13 -4 -4 -20 -13 5 5 21 13 -5 -5 -21 -13 6 6 22 13 -6 -6 -22 -13 7 7 23 13 -7 -7 -23 -13 8 8 24 14 -8 -8 -24 -14 9 8 25 14 -9 -8 -25 -14 10 9 26 14 -10 -9 -26 -14 11 9 27 14 -11 -9 -27 -14 12 10 28 15 -12 -10 -28 -15 13 10 29 15 -13 -10 -29 -15 14 11 30 15 -14 -11 -30 -15 15 11 31 15 -15 -11 -31 -15

3) the checkpoint computing unit receives the non-uniform quantizing value of several 5 bits, according to the formula of calculation check point m to the information of variable point n:

$L\left(r_{\mathrm{mn}}\right)=\max \left(\underset{n^{\′}\∈N\left(m\right)\backslash n}{\min }\left(\right|L\left(q_{m{n}^{\′}}\right)\left|\right)\right)-\mathrm{offset},0),$

After they are finished computing, export the non-uniform quantizing value of 5 bits, pass to variable point computing unit;

Wherein, L (r _Mn) expression passes to the value of information of variable point n from checkpoint m; L (q _Mn) expression passes to the value of information of checkpoint m from variable point n; Offset representes that the MS-offset algorithm approaches the offset that the BP sum-product algorithm will be used; N (m) n represent except that variable point n the set of the variable point that is connected with checkpoint m;

4) variable point computing unit receives the non-uniform quantizing value of several 5 bits, by its order of magnitude, adopts different quantized at interval, the non-uniform quantizing value according to the form below of 5 bits:

5bits 6bits 5bits 6bits 0 0 0 0 1 1 -1 -1 2 2 -2 -2 3 3 -3 -3 4 4 -4 -4 5 5 -5 -5 6 6 -6 -6 7 7 -7 -7 8 8 -8 -8 9 10 -9 -10 10 12 -10 -12 11 14 -11 -14 12 18 -12 -18 13 22 -13 -22 14 26 -14 -26 15 30 -15 -30

Convert the uniform quantization value of 6 bits to, then according to calculating the formula of variable point n to the information of checkpoint m:

$L\left(q_{\mathrm{mn}}\right)={\mathrm{\γ}}_n+\underset{m^{\′}\∈M\left(n\right)\backslash m}{\mathrm{\Σ}}L\left(r_{m^{\′}n}\right),$

Wherein, L (q _Mn) expression passes to the value of information of checkpoint m from variable point n; γ _nY is used in expression _iThe channel likelihood information value that calculates; L (r _Mn) expression passes to the value of information of variable point n from checkpoint m; M (n) m represent except that checkpoint m the set of the checkpoint that is connected with variable point n;

They are carried out computing, export the uniform quantization value of 6 bits equally, by its order of magnitude, adopt different quantized at interval, the uniform quantization value according to the form below of 6 bits:

6bits 5bits 6bits 5bits 6bits 5bits 6bits 5bits 0 0 16 12 0 0 -16 -12 1 1 17 12 -1 -1 17 -12 2 2 18 12 -2 -2 -18 -12 3 3 19 12 -3 -3 -19 -12 4 4 20 13 -4 -4 -20 -13 5 5 21 13 -5 -5 -21 -13 6 6 22 13 -6 -6 -22 -13 7 7 23 13 -7 -7 -23 -13 8 8 24 14 -8 -8 -24 -14 9 8 25 14 -9 -8 -25 -14 10 9 26 14 -10 -9 -26 -14 11 9 27 14 -11 -9 -27 -14 12 10 28 15 -12 -10 -28 -15 13 10 29 15 -13 -10 -29 -15 14 11 30 15 -14 -11 -30 -15 15 11 31 15 -15 -11 -31 -15

Convert the non-uniform quantizing value of 5 bits to, pass to the checkpoint computing unit again.

2. a kind of 55 bit quantization methods that are applied to LDPC decoding as claimed in claim 1 is characterized in that in step 2)～4) in, the data format arrangement of said quantized value is following:

The highest order of quantization bit figure place is represented the symbol of this information; The value of highest order is 1; Be expressed as negatively, be 0 and just be expressed as, remaining figure place is represented the amplitude size of information; All quantized values all adopt complement form to represent, what therefore in ldpc decoder, transmit between each computing unit all is the quantized value of representing with complement form.

3. a kind of 55 bit quantization methods that are applied to LDPC decoding as claimed in claim 1 is characterized in that in step 2) in, the said non-uniform quantizing value that converts the uniform quantization value of 6 bits to by table 15 bits; Be to adopt the LUT look-up table; Realize that with ROM with the 6 bit uniform quantization values that the receive INADD as ROM, correspondence finds out the 5 bit non-uniform quantizing values that deposit the ROM the inside; In this implementation, be to utilize ROM to realize the LUT look-up table equally; Or

Adopt logical circuit, describe of the conversion of 6 bit uniform quantization values to 5 bit non-uniform quantizing values.

4. a kind of 55 bit quantization methods that are applied to LDPC decoding as claimed in claim 1 is characterized in that in step 4), and are said the non-uniform quantizing value according to the form below of 5 bits:

6bits 5bits 6bits 5bits 6bits 5bits 6bits 5bits 0 0 16 12 0 0 -16 -12 1 1 17 12 -1 -1 17 -12 2 2 18 12 -2 -2 -18 -12 3 3 19 12 -3 -3 -19 -12 4 4 20 13 -4 -4 -20 -13 5 5 21 13 -5 -5 -21 -13 6 6 22 13 -6 -6 -22 -13 7 7 23 13 -7 -7 -23 -13 8 8 24 14 -8 -8 -24 -14 9 8 25 14 -9 -8 -25 -14 10 9 26 14 -10 -9 -26 -14 11 9 27 14 -11 -9 -27 -14 12 10 28 15 -12 -10 -28 -15 13 10 29 15 -13 -10 -29 -15 14 11 30 15 -14 -11 -30 -15 15 11 31 15 -15 -11 -31 -15

Converting the uniform quantization value of 6 bits to, is to adopt the LUT look-up table, realizes with ROM; With the 5 bit non-uniform quantizing values that receive INADD as ROM; Correspondence finds out the 6 bit uniform quantization values that deposit the ROM the inside, in this implementation, utilizes ROM to realize the LUT look-up table; Or

Adopt logical circuit, describe of the conversion of 5 bit non-uniform quantizing values to 6 bit uniform quantization values.

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