CN104579362A - System and method for decoding LDPC code of partially-parallel decoding architecture in space communication system - Google Patents

Abstract

The invention relates to a system and a method for decoding an LDPC (low density parity check) code of a partially-parallel decoding architecture in a space communication system. The system structurally comprises an iteration control unit, a channel information memory, a main memory, a variable node processing module, a check node processing module and a judgment result output buffering unit, wherein the main memory is simple in structure and is in one-to-one correspondence to a non-zero submatrix in a check matrix structure diagram; an address processing unit capable of reading data from the main memory is simple in structure and easy to implement. The partially-parallel decoding architecture is provided with a hyper-row plurality of parallel check node processing units and a hyper-column plurality of parallel variable node processing units; a node message updating algorithm is low in implementation complexity and low in resource consumption.

Description

Partially-parallel architecture LDPC code decoding system and method thereof in a kind of space communication system

Technical field

The present invention relates to partially-parallel architecture LDPC code decoding system in a kind of space communication system, belong to parallel decoding technical field.

Background technology

In space communication system, the signal that receiver receives often is subject to the impact such as fading channel and interference noise.To this, space communication system often adopts LDPC (low density parity check code) code with high channel coding gain to improve the reliability of information transmission, the error rate is reduced and approaches shannon limit.At present, LDPC code is by one of recommendation channel coding schemes of communication system of organizing as CCSDS (the Aerospace Data Systems information committee), European DVB (digital video broadcasting) etc.LDPC code commonly uses check matrix or graph model is described, Tanner figure expression be wherein more intuitively, a kind of easily, comprise two node set, variable node (variable node) set and check-node (check node) set.Each variable node corresponds to a code element of code word, and each check-node corresponds to a parity check constraint relation.Connected by limit (edge) between two node set, and node set inside connects without any limit.There is relation one to one with check matrix in Tanner figure, namely variable node is corresponding with the row in check matrix, and capable corresponding with check matrix of check-node, limit is then corresponding with the nonzero element in check matrix.The number on the limit be connected with node in Tanner figure is called the degree (degree) of node, and the degree of node is consistent with the row heavy (column weight) of check matrix.

The decoding algorithm of LDPC code has a lot, and conventional belief propagation (BP) decoding algorithm represents probability messages with log-likelihood ratio (LLR), and its algorithm steps is summarized as follows,

(1) initialization, calculating channel transfer is P to the probability of variable node _i, and the likelihood ratio message data of correspondence is D (P _i), then set each variable node i and be transmitted to the check-node j be adjacent, the span of j is j ∈ M _i, initial information be D ⁽⁰⁾(q _{i → j})=D (P _i), N in formula _jfor the set of the adjacent variable node i of each check-node j.

(2) check-node upgrades, and the message that calculating variable node is transmitted to check-node is D ^(l)(r _{j → i}), N _jfor the variable node set that a jth check-node is adjacent,

$D^{\left(l\right)}\left(r_{j\→i}\right)={2\tanh }^{-1}\left(\underset{i^{\′}\∈N_j\backslash i}{\mathrm{\Π}}\tanh \left(\frac{D^{(l-1)}\left(q_{i^{\′}\→j}\right)}{2}\right)\right)---\left(1\right)$

In formula, i' ∈ N _ji represent set N _jthe set of middle removing i-th point, l represents this iterative decoding of l, and l-1 represents the l-1 time iterative decoding.

(3) variable node upgrades, and during the l time iteration, the message that calculation check node is transmitted to variable node is D ^(l)(q _{i → j}),

$D^{\left(l\right)}\left(q_{i\→j}\right)=D\left(P_i\right)+\underset{j^{\′}\∈M_i\backslash j}{\mathrm{\Σ}}{D}^{\left(l\right)}\left(r_{j^{\′}\→i}\right)---\left(2\right)$

(4) decoding judgement, the hard decision information calculating all variable nodes is D ^(l)(q _{i → j}),

$D^{\left(l\right)}\left(q_{i\→j}\right)=D\left(P_i\right)+\underset{j\∈M_i}{\mathrm{\Σ}}{D}^{\left(l\right)}\left(r_{j\→i}\right)---\left(3\right)$

If D ^(l)(q _i) >0, be then judged to 1, otherwise be 0.Meet adjudicating the sequence obtained in formula, H represents check matrix, represent the transposition of judgement data, or reach maximum iteration time, then terminate decoding, otherwise forward 1 to).

Minimum and (MS) algorithm can be derived from BP decoding algorithm.Its check-node upgrades and can be expressed as

$D^{\left(l\right)}\left(r_{j\→i}\right)=\left(\underset{i^{\′}\∈N_j\backslash i}{\mathrm{\Π}}\mathrm{sgn}\left(\frac{D^{(l-1)}\left(q_{i^{\′}\→j}\right)}{2}\right)\right)\·\underset{i^{\′}\∈N_j\backslash i}{\min }\left(\right|D^{(l-1)}\left(q_{i^{\′}\→j}\right))---\left(4\right)$

In formula, sgn represents that getting sign bit operates.

In addition also have minimum to minimum and normalization that the is correction of (MS) algorithm and and side-play amount minimum-sum algorithm etc., although the above decoding algorithm is through various simplification, the realization of LDPC decoding algorithm often needs very complicated calculating and more resource consumption in digital receiver.So more need simplicity of design, efficiently decoder in broadband spatial communication system.

Summary of the invention

The technical problem that the present invention solves is: overcome prior art deficiency, partially-parallel architecture LDPC code decoding system in a kind of space communication system is provided, for (8192 of code check R=1/2 in CCSDS (the Aerospace Data Systems information committee) system, 4096) LDPC code designs partially-parallel architecture LDPC code interpretation method in a kind of space communication system, the present invention has the simple main storage of distribution, be easy to the address process that realizes and the low node messages updating block of implementation complexity, this design can be applied to the ldpc decoder design of other code checks of CCSDS deep space communication standard neatly.

The technical scheme that the present invention solves is: partially-parallel architecture LDPC code decoding system in a kind of space communication system, comprises iteration control unit, channel information memory, main storage, variable node processing module, code check node processing module, court verdict output buffer cell;

Channel information memory comprises 4 dual port RAMs, the degree of depth of each RAM is L=2048, main storage comprises 15 memory RAM, namely main storage RAM1, RAM2 ..., RAM15, for the side information transmitted between storage of variables node and check-node, the code efficiency that each memory RAM correspondence defines in CCSDS standard is each non-zero submatrices in the check matrix H of the quasi-cyclic LDPC code of R=1/2, each memory RAM degree of depth is L=2048, namely main storage RAM1, RAM2 ..., RAM15 is respectively corresponding as follows:

The submatrix I that RAM1 correspondence super row S1 is corresponding with the H2 that is out of the line _l;

The submatrix I that RAM2 correspondence super row S1 is corresponding with the H3 that is out of the line _l;

The submatrix I that RAM3 correspondence super row S2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM4 correspondence super row S2 is corresponding with the H3 that is out of the line ₅;

The submatrix Π that RAM5 correspondence super row S2 is corresponding with the H3 that is out of the line ₆;

The submatrix I that RAM6 correspondence super row P1 is corresponding with the H1 that is out of the line _l;

The submatrix I that RAM7 correspondence super row P2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM8 correspondence super row P2 is corresponding with the H3 that is out of the line ₇;

The submatrix Π that RAM9 correspondence super row P2 is corresponding with the H3 that is out of the line ₈;

The submatrix I that RAM10 correspondence super row P3 is corresponding with the H1 that is out of the line _l;

The submatrix Π that RAM11 correspondence super row P3 is corresponding with the H1 that is out of the line ₁;

The submatrix Π that RAM12 correspondence super row P3 is corresponding with the H2 that is out of the line ₂;

The submatrix Π that RAM13 correspondence super row P3 is corresponding with the H2 that is out of the line ₃;

The submatrix Π that RAM14 correspondence super row P3 is corresponding with the H2 that is out of the line ₄;

The submatrix I that RAM15 correspondence super row P3 is corresponding with the H3 that is out of the line _l;

The row of check matrix H is divided into 3 to be out of the line being respectively H1, H2, H3, and H1 is that 0-2047 is capable, H2 is that 2048-4095 is capable, H3 is that 4096-6143 is capable; The row of check matrix H are divided into 5 super row S1, S2, P1, P2, P3, S1 is that 0-2047 arranges, S2 is 2048-4095 row, P1 is 4096-6143 row, P2 is 6144-8191 row, P3 is 8192-10239 row, and this matrix trace inequality as shown in Figure 1;

Variable node processing module comprises these 5 variable node processing unit of VNU1, VNU2, VNU3, VNU4 and VNU5, and variable node processing unit is that 5 roads walk abreast;

Check-node address processing module comprises these three code check node processing unit of CNU1, CNU2, CNU3, and CNU1, CNU2, CNU3 are that 3 roads walk abreast;

Channel information memory cell receives and stores these frame likelihood information data current of digital receiver demodulation, and this likelihood information data sequence is stored in 4 RAM of channel information memory cell, one frame likelihood information data are 8192, after this frame receives, channel information memory cell produces one and receives signal and send to iteration control unit, and channel information memory cell receives 8192 data of next frame simultaneously by ping-pong operation;

Iteration control unit sends decoding commencing signal to channel information memory cell after receiving and receiving signal, channel information memory cell receives decoding commencing signal, by the likelihood information data sequence ground parallel output 4 circuit-switched data D_llr in 4 RAM to variable node processing module

4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, this 4 circuit-switched data D_llr is delivered to VNU1 respectively, VNU2, VNU3, VNU4, 0 value is delivered to VNU5, variable node processing module is from the RAM1 main storage simultaneously, RAM2, according to the RAM1 in memory in RAM15, RAM2, the order reading address Addr_VN of RAM15 reads RAM1, RAM2, side information D_a1 in RAM15, if the 1st iteration, the side information D_a1=0 then taken out from main storage, defining by iteration control unit the order reading address Addr_VN is 0, 1, 2, 2047, respectively side information D_a1 is delivered to VNU1 in the following manner, VNU2, VNU3, VNU4, VNU5:

The data of RAM1, RAM2 are sequentially read according to Addr_VN and gives VNU1;

The data of RAM3 ~ RAM5 are sequentially read according to Addr_VN and gives VNU2;

The data of RAM6 are sequentially read according to Addr_VN and gives VNU3;

The data of RAM7 ~ RAM9 are sequentially read according to Addr_VN and gives VNU4;

The data of RAM10 ~ RAM15 are sequentially read according to Addr_VN and gives VNU5;

Calculate the likelihood information upgraded according to D_llr and D_a1, obtain the side information D_e1 after upgrading; By the side information D_e1 after upgrading according to write address Addr_VN write main storage RAM1, RAM2 ..., RAM15, read address Addr_VN identical with write address Addr_VN numerical value, difference is that allocating time is different, generates by iteration control unit, for sequence address 0,1,2 ..., 2047;

What iteration control unit produced check-node address processing module reads address Addr_CN, Addr_CN comprises Addr_CN1, Addr_CN2 ..., Addr_CN15, Addr_CN1, Addr_CN2 ..., Addr_CN15 by step (3) main storage RAM1, RAM2 ..., submatrix that RAM15 is corresponding calculates;

Code check node processing module according to reading address Addr_CN, from main storage RAM1, RAM2 ..., read side information D_e1 in the following manner in RAM15, be designated as side information D_a2, deliver to CNU1, CNU2, CNU3 in check-node address processing module;

Data by RAM10, RAM11 give CNU1 according to Addr_CN10, Addr_CN11 reading;

The data of RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 are read according to Addr_CN1, Addr_CN3, Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 respectively and gives CNU2;

The data of RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 are read according to Addr_CN2, Addr_CN4, Addr_CN5, Addr_CN8, Addr_CN9, Addr_CN15 respectively and gives CNU3;

The likelihood information upgraded is calculated, the side information D_e2 after again being upgraded according to the side information D_a2 obtained;

By the side information D_e2 after renewal according to address Addr_CN1, Addr_CN2 ..., Addr_CN15 write respectively RAM1 in main storage, RAM2 ..., after RAM15, this time iteration settling signal is sent to iteration control unit, read address Addr_CN identical with write address Addr_CN numerical value, difference is that allocating time is different, generates by iteration control unit;

Iteration control unit receives this time iteration settling signal, start next iteration, until reach the maximum iteration time M of this frame of setting, produce decoding termination signal Dec_E, then, the side information D_e1 ' obtained after last iteration being completed is 0 and 1 according to positive and negative judgement, namely D_e1 ' is just, judgement is 1, D_e1 ' is negative, judgement is 0, this court verdict exports buffer cell by court verdict and exports court verdict, this frame coding is complete, carry out the decoding of next frame subsequently, until all frame likelihood information data decodings of digital receiver demodulation complete.

The check matrix of described check matrix H to be the code check defined in CCSDS standard the be quasi-cyclic LDPC code of R=1/2, the code word size N of this quasi-cyclic LDPC code is 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as:

$H=\left[\begin{array}{ccccc}{0}_L& 0_L& I_L& 0_L& I_L\⊕{\mathrm{\Π}}_1\\ I_L& I_L& 0_L& I_L& {\mathrm{\Π}}_2\⊕{\mathrm{\Π}}_3\⊕{\mathrm{\Π}}_4\\ I_L& {\mathrm{\Π}}_5\⊕{\mathrm{\Π}}_6& 0_L& {\mathrm{\Π}}_7\⊕{\mathrm{\Π}}_8& I_L\end{array}\right]$

I in matrix H _lwith 0 _lbe respectively 2048 × 2048 dimension unit matrix and 0 matrixes, Π _k(k=1,2 ..., 8) be 2048 × 2048 dimension displacement battle arrays, this displacement battle array Π _kt capable (t=0,1,2 ..., 2047) the column position π of nonzero element _k(t) be:

In formula, L=2048, mod represent modular arithmetic, represent and 4t/L is rounded downwards, column position π _kfunction # in (t) _kwith value see in CCSDS standard CC SDS 131.1-O-2 show 3-3, table 3-4, there is accurate cycle characteristics.

Described Addr_CN is that the check matrix H of (8192,4096) LDPC code of R=1/2 calculates according to code check in CCSDS standard.

Described D_llr and D_a1 calculates the likelihood information upgraded, and the step obtaining the side information D_e1 after upgrading is as follows:

If n-th, n is 1,2,3,4,5, it is positive integer that variable node processing unit reads m information D_a1, m from main storage, m ' is 1,2 ... m, m ' represent the sequence number of the individual information of m ' in m information, the individual information D_a1 of m ' (m ') the corresponding lastest imformation D_e1 channel likelihood information D_llr that equals to read from channel information memory adds other m-1 information D_a1 outside the individual information D_a1 of removing m ' (m ').

Described D_a2 calculates the likelihood information upgraded, and the step obtaining the side information D_e2 after upgrading is as follows:

(1) p is established, p is 1,2,3, it is positive integer that code check node processing unit reads k information D_a2, k from main storage, k ' is 1,2 ... the sequence number of k, k ' represent kth ' in k information individual information, kth ' individual information D_a2 (k ') sign bit of corresponding lastest imformation D_e2 is operating as: removing kth ' individual lastest imformation D_a2 (k ') outside the XOR of k-1 D_a2 sign bit;

(2) amplitude of k information D_a2 is compared, try to achieve amplitude min value and amplitude sub-minimum, these two values are multiplied by normalization factor α by correction value multiplier, by amplitude min value and kth ' compared with the amplitude of individual information, if identical, then export sub-minimum, if different, then export minimum value, the scope of α is 0 ~ 1;

(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after upgrading is obtained.

Obtain after described last iteration completes equal last iteration for the information D_e1 ' adjudicating output time the channel likelihood information D_llr that reads from channel information memory add m information D_a1's (m) and value.

Partially-parallel architecture LDPC code interpretation method in a kind of space communication system, comprises and divides LDPC check matrix stage and pipeline system Partly parallel decoding stage:

Described division LDPC check matrix stage etch is as follows:

(1) code check defined in CCSDS standard is the quasi-cyclic LDPC code of R=1/2, and the code word size N of this quasi-cyclic LDPC code is 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as

$H=\left[\begin{array}{ccccc}{0}_L& 0_L& I_L& 0_L& I_L\⊕{\mathrm{\Π}}_1\\ I_L& I_L& 0_L& I_L& {\mathrm{\Π}}_2\⊕{\mathrm{\Π}}_3\⊕{\mathrm{\Π}}_4\\ I_L& {\mathrm{\Π}}_5\⊕{\mathrm{\Π}}_6& 0_L& {\mathrm{\Π}}_7\⊕{\mathrm{\Π}}_8& I_L\end{array}\right]$

I in matrix H _lwith 0 _lbe respectively 2048 × 2048 dimension unit matrix and 0 matrixes, Π _k(k=1,2 ..., 8) be 2048 × 2048 dimension displacement battle arrays, this displacement battle array Π _kt capable (t=0,1,2 ..., 2047) the column position π of nonzero element _k(t) be:

In formula, L=2048, mod represent modular arithmetic, represent and 4t/L is rounded downwards, column position π _kfunction # in (t) _kwith value see in CCSDS standard CC SDS 131.1-O-2 show 3-3, table 3-4, there is accurate cycle characteristics;

(2) be divided into 3 to be out of the line the row of the check matrix H of step (1) to be respectively: H1 (0-2047 is capable), H2 (2048-4095 is capable), H3 (4096-6143 is capable); 5 super row are divided into by the row of check matrix H to be respectively S1 (0-2047 row), S2 (2048-4095 row), P1 (4096-6143 row), P2 (6144-8191 row), P3 (8192-10239 row);

(3) data storage of definition needed for decoding comprises: channel information memory, main storage and decoding export buffer unit; Channel information memory is used for buffer memory channel likelihood information, and comprise 4 dual port RAMs, the degree of depth of each RAM is 2048; Main storage comprises 15 memory RAM, namely main storage RAM1, RAM2 ..., RAM15, for the side information transmitted between storage of variables node and check-node, each non-zero submatrices in the corresponding check matrix H of each memory RAM, each memory RAM degree of depth is 2048, namely main storage RAM1, RAM2 ..., RAM15 is respectively corresponding:

The submatrix I that RAM1 correspondence super row S1 is corresponding with the H2 that is out of the line _l;

The submatrix I that RAM2 correspondence super row S1 is corresponding with the H3 that is out of the line _l;

The submatrix I that RAM3 correspondence super row S2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM4 correspondence super row S2 is corresponding with the H3 that is out of the line ₅;

The submatrix Π that RAM5 correspondence super row S2 is corresponding with the H3 that is out of the line ₆;

The submatrix I that RAM6 correspondence super row P1 is corresponding with the H1 that is out of the line _l;

The submatrix I that RAM7 correspondence super row P2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM8 correspondence super row P2 is corresponding with the H3 that is out of the line ₇;

The submatrix Π that RAM9 correspondence super row P2 is corresponding with the H3 that is out of the line ₈;

The submatrix I that RAM10 correspondence super row P3 is corresponding with the H1 that is out of the line _l;

The submatrix Π that RAM11 correspondence super row P3 is corresponding with the H1 that is out of the line ₁;

The submatrix Π that RAM12 correspondence super row P3 is corresponding with the H2 that is out of the line ₂;

The submatrix Π that RAM13 correspondence super row P3 is corresponding with the H2 that is out of the line ₃;

The submatrix Π that RAM14 correspondence super row P3 is corresponding with the H2 that is out of the line ₄;

The submatrix I that RAM15 correspondence super row P3 is corresponding with the H3 that is out of the line _l;

Decoding exports buffer unit for exporting decode results;

Described pipeline system Partly parallel decoding stage etch is as follows:

(4) channel information memory cell receives and stores these frame likelihood information data current of digital receiver demodulation, and this likelihood information data sequence is stored in 4 RAM of channel information memory cell, one frame likelihood information data are 8192, after this frame receives, channel information memory cell produces one and receives signal and send to iteration control unit, and channel information memory cell receives 8192 data of next frame simultaneously by ping-pong operation;

(5) iteration control unit sends decoding commencing signal to channel information memory cell; Channel information memory cell receives decoding commencing signal, by the likelihood information data sequence ground parallel output 4 circuit-switched data D_llr in 4 RAM to variable node processing module;

(6) 4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, variable node processing module comprises VNU1, VNU2, VNU3, these 5 variable node processing unit of VNU4 and VNU5, this 4 circuit-switched data D_llr is delivered to VNU1 respectively, VNU2, VNU3, VNU4, 0 value is delivered to VNU5, variable node processing module is from the RAM1 main storage simultaneously, RAM2, according to the RAM1 in memory in RAM15, RAM2, the order reading address Addr_VN of RAM15 reads RAM1, RAM2, side information D_a1 in RAM15, if the 1st iteration, the side information D_a1=0 then taken out from main storage, defining by iteration control unit the order reading address Addr_VN is 0, 1, 2, 2047, respectively side information D_a1 is delivered to VNU1 in the following manner, VNU2, VNU3, VNU4, VNU5, variable node processing unit is that 5 roads walk abreast:

The data of RAM1, RAM2 are sequentially read according to Addr_VN and gives VNU1;

The data of RAM3 ~ RAM5 are sequentially read according to Addr_VN and gives VNU2;

The data of RAM6 are sequentially read according to Addr_VN and gives VNU3;

The data of RAM7 ~ RAM9 are sequentially read according to Addr_VN and gives VNU4;

The data of RAM10 ~ RAM15 are sequentially read according to Addr_VN and gives VNU5;

(7) calculate the likelihood information upgraded according to D_llr and D_a1 obtained in step (6), obtain the side information D_e1 after upgrading;

(8) by the side information D_e2 after upgrading in step (7) according to write address Addr_VN write main storage RAM1, RAM2 ..., RAM15, read address Addr_VN identical with write address Addr_VN numerical value, difference is that allocating time is different, generate by iteration control unit, for sequence address 0,1,2 ..., 2047;

(9) what iteration control unit produced code check node processing module reads address Addr_CN, Addr_CN comprises Addr_CN1, Addr_CN2 ... Addr_CN15, Addr_CN1, Addr_CN2 ... Addr_CN15 by step (3) main storage RAM1, RAM2 ..., submatrix that RAM15 is corresponding calculates;

Code check node processing module comprises CNU1, CNU2, CNU3, code check node processing module is according to reading address Addr_CN, from main storage RAM1, RAM2 ..., side information D_e1 in RAM15 in the following manner in reading step (8), be designated as side information D_a2, deliver to CNU1, CNU2, the CNU3 in code check node processing module, CNU1, CNU2, CNU3 of code check node processing module are that 3 roads walk abreast;

Data by RAM10, RAM11 give CNU1 according to Addr_CN10, Addr_CN11 reading;

The data of RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 are read according to Addr_CN1, Addr_CN3, Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 respectively and gives CNU2;

The data of RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 are read according to Addr_CN2, Addr_CN4, Addr_CN5, Addr_CN8, Addr_CN9, Addr_CN15 respectively and gives CNU3;

(10) calculate the likelihood information upgraded according to the D_a2 obtained in step (9), obtain the side information D_e2 after upgrading;

(11) by the side information D_e2 after upgrading in step (10) according to address Addr_CN1, Addr_CN2 ... Addr_CN15 write respectively RAM1 in main storage, RAM2 ..., after RAM15, this time iteration settling signal is sent to iteration control unit, read address Addr_CN identical with write address Addr_CN numerical value, difference is that allocating time is different, generates by iteration control unit;

(12) iteration control unit receives this time iteration settling signal of step (11), start next iteration, namely step is repeated according to step (5) ~ step (12), until reach the maximum iteration time M of this frame of setting, produce decoding termination signal Dec_E, then, the D_e1 ' obtained after last iteration being completed is 0 and 1 according to positive and negative judgement, namely D_e1 ' is just, judgement is 1, D_e1 ' is negative, judgement is 0, this court verdict exports buffer cell by court verdict and exports court verdict, this frame coding is complete, return the decoding that step (4) carries out next frame subsequently, until all frame likelihood information data decodings of digital receiver demodulation complete.

Described step (9) and the Addr_CN described in (11) are that the H matrix computations of (8192,4096) LDPC code of R=1/2 obtains according to code check in CCSDS standard.

: in described step (7), D_llr and D_a1 calculates the likelihood information upgraded, and the step obtaining the side information D_e1 after upgrading is as follows:

If n-th, n is 1,2,3,4,5, it is positive integer that variable node processing unit reads m information D_a1, m from main storage, m ' is 1,2 ... m, m ' represent the sequence number of the individual information of m ' in m information, the individual information D_a1 of m ' (m ') the corresponding lastest imformation D_e1 channel likelihood information D_llr that equals to read from channel information memory adds other m-1 information D_a1 outside the individual information D_a1 of removing m ' (m ').

In described step (10), D_a2 calculates the likelihood information upgraded, and the step obtaining the side information D_e2 after upgrading is as follows:

(1) p is established, p is 1,2,3, it is positive integer that code check node processing unit reads k information D_a2, k from main storage, k ' is 1,2 ... the sequence number of k, k ' represent kth ' in k information individual information, kth ' individual information D_a2 (k ') sign bit of corresponding lastest imformation D_e2 is operating as: removing kth ' individual lastest imformation D_a2 (k ') outside the XOR of k-1 D_a2 sign bit;

(2) amplitude of k information D_a2 is compared, try to achieve amplitude min value and amplitude sub-minimum, these two values are multiplied by normalization factor α by correction value multiplier, by amplitude min value and kth ' compared with the amplitude of individual information, if identical, then export sub-minimum, if different, then export minimum value, the scope of α is 0 ~ 1;

(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after upgrading is obtained.

The channel likelihood information D_llr that what in described step (12), last iteration obtained after completing read when equaling last iteration for the information D_e1 ' adjudicating output from channel information memory add m information D_a1's (m) and value.

The present invention's advantage is compared with prior art:

(1) in the present invention for (8192 of code check R=1/2 in CCSDS system, 4096) the check matrix structure chart of LDPC code has the advantages that to be out of the line, to surpass row, devise the simple main storage of structure, with non-zero submatrices one_to_one corresponding in check matrix structure chart; The address processing unit structure reading data from main storage is simple, be easy to realize.

(2) Partly parallel decoding structural design of the present invention several parallel code check node processing unit that is out of the line, a super columns parallel variable node processing unit, the implementation complexity of node messages update algorithm is low, and institute's cost source is few.

(3) decoding performance of the Partly parallel decoding designed by the present invention is good, and coding gain can reach 9dB.Meanwhile, this Partly parallel decoding structure extends to other code efficiency LDPC code words.

Accompanying drawing explanation

Fig. 1 is the check matrix structure chart of LDPC code word in interpretation method of the present invention;

Fig. 2 is the system block diagram of the partially-parallel architecture of interpretation method of the present invention;

Fig. 3 is the schematic diagram of the address Addr_CN that in the structure of interpretation method of the present invention, code check node processing is used;

Fig. 4 is subframe Π in the structure of interpretation method of the present invention ₁the read/write address Addr_CN schematic diagram of corresponding main storage.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail:

As shown in Figure 2, partially-parallel architecture LDPC code decoding system in a kind of space communication system, comprises iteration control unit, channel information memory, main storage, variable node processing module, code check node processing module, court verdict output buffer cell;

Channel information memory comprises 4 dual port RAMs, the degree of depth of each RAM is L=2048, main storage comprises 15 memory RAM, namely main storage RAM1, RAM2 ..., RAM15, for the side information transmitted between storage of variables node and check-node, the code efficiency that each memory RAM correspondence defines in CCSDS standard is each non-zero submatrices in the check matrix H of the quasi-cyclic LDPC code of R=1/2, each memory RAM degree of depth is L=2048, namely main storage RAM1, RAM2 ..., RAM15 is respectively corresponding as follows:

The submatrix I that RAM1 correspondence super row S1 is corresponding with the H2 that is out of the line _l;

The submatrix I that RAM2 correspondence super row S1 is corresponding with the H3 that is out of the line _l;

The submatrix I that RAM3 correspondence super row S2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM4 correspondence super row S2 is corresponding with the H3 that is out of the line ₅;

The submatrix Π that RAM5 correspondence super row S2 is corresponding with the H3 that is out of the line ₆;

The submatrix I that RAM6 correspondence super row P1 is corresponding with the H1 that is out of the line _l;

The submatrix I that RAM7 correspondence super row P2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM8 correspondence super row P2 is corresponding with the H3 that is out of the line ₇;

The submatrix Π that RAM9 correspondence super row P2 is corresponding with the H3 that is out of the line ₈;

The submatrix I that RAM10 correspondence super row P3 is corresponding with the H1 that is out of the line _l;

The submatrix Π that RAM11 correspondence super row P3 is corresponding with the H1 that is out of the line ₁;

The submatrix Π that RAM12 correspondence super row P3 is corresponding with the H2 that is out of the line ₂;

The submatrix Π that RAM13 correspondence super row P3 is corresponding with the H2 that is out of the line ₃;

The submatrix Π that RAM14 correspondence super row P3 is corresponding with the H2 that is out of the line ₄;

The submatrix I that RAM15 correspondence super row P3 is corresponding with the H3 that is out of the line _l;

The row of check matrix H is divided into 3 to be out of the line being respectively H1, H2, H3, and H1 is that 0-2047 is capable, H2 is that 2048-4095 is capable, H3 is that 4096-6143 is capable; The row of check matrix H are divided into 5 super row S1, S2, P1, P2, P3, S1 is that 0-2047 arranges, S2 is 2048-4095 row, P1 is 4096-6143 row, P2 is 6144-8191 row, P3 is 8192-10239 row, and this matrix trace inequality as shown in Figure 1;

Variable node processing module comprises these 5 variable node processing unit of VNU1, VNU2, VNU3, VNU4 and VNU5, and variable node processing unit is that 5 roads walk abreast;

Check-node address processing module comprises these three code check node processing unit of CNU1, CNU2, CNU3, and CNU1, CNU2, CNU3 are that 3 roads walk abreast;

Channel information memory cell receives and stores these frame likelihood information data current of digital receiver demodulation, and this likelihood information data sequence is stored in 4 RAM of channel information memory cell, one frame likelihood information data are 8192, after this frame receives, channel information memory cell produces one and receives signal and send to iteration control unit, and channel information memory cell receives 8192 data of next frame simultaneously by ping-pong operation;

Iteration control unit sends decoding commencing signal to channel information memory cell after receiving and receiving signal, channel information memory cell receives decoding commencing signal, by the likelihood information data sequence ground parallel output 4 circuit-switched data D_llr in 4 RAM to variable node processing module

4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, this 4 circuit-switched data D_llr is delivered to VNU1 respectively, VNU2, VNU3, VNU4, 0 value is delivered to VNU5, variable node processing module is from the RAM1 main storage simultaneously, RAM2, according to the RAM1 in memory in RAM15, RAM2, the order reading address Addr_VN of RAM15 reads RAM1, RAM2, side information D_a1 in RAM15, if the 1st iteration, the side information D_a1=0 then taken out from main storage, defining by iteration control unit the order reading address Addr_VN is 0, 1, 2, 2047, respectively side information D_a1 is delivered to VNU1 in the following manner, VNU2, VNU3, VNU4, VNU5:

The data of RAM1, RAM2 are sequentially read according to Addr_VN and gives VNU1;

The data of RAM3 ~ RAM5 are sequentially read according to Addr_VN and gives VNU2;

The data of RAM6 are sequentially read according to Addr_VN and gives VNU3;

The data of RAM7 ~ RAM9 are sequentially read according to Addr_VN and gives VNU4;

The data of RAM10 ~ RAM15 are sequentially read according to Addr_VN and gives VNU5;

Calculate the likelihood information upgraded according to D_llr and D_a1, obtain the side information D_e1 after upgrading; By the side information D_e1 after upgrading according to write address Addr_VN write main storage RAM1, RAM2 ..., RAM15, read address Addr_VN identical with write address Addr_VN numerical value, difference is that allocating time is different, generates by iteration control unit, for sequence address 0,1,2 ..., 2047;

What iteration control unit produced check-node address processing module reads address Addr_CN, Addr_CN comprises Addr_CN1, Addr_CN2 ..., Addr_CN15, Addr_CN1, Addr_CN2 ..., Addr_CN15 by step (3) main storage RAM1, RAM2 ..., submatrix that RAM15 is corresponding calculates;

Code check node processing module according to reading address Addr_CN, from main storage RAM1, RAM2 ..., read side information D_e1 in the following manner in RAM15, be designated as side information D_a2, deliver to CNU1, CNU2, CNU3 in check-node address processing module;

Data by RAM10, RAM11 give CNU1 according to Addr_CN10, Addr_CN11 reading;

The data of RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 are read according to Addr_CN1, Addr_CN3, Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 respectively and gives CNU2;

The data of RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 are read according to Addr_CN2, Addr_CN4, Addr_CN5, Addr_CN8, Addr_CN9, Addr_CN15 respectively and gives CNU3;

The likelihood information upgraded is calculated, the side information D_e2 after again being upgraded according to the side information D_a2 obtained;

By the side information D_e2 after renewal according to address Addr_CN1, Addr_CN2 ..., Addr_CN15 write respectively RAM1 in main storage, RAM2 ..., after RAM15, this time iteration settling signal is sent to iteration control unit, read address Addr_CN identical with write address Addr_CN numerical value, difference is that allocating time is different, generates by iteration control unit;

Iteration control unit receives this time iteration settling signal, start next iteration, until reach the maximum iteration time M of this frame of setting, produce decoding termination signal Dec_E, then, the side information D_e1 ' obtained after last iteration being completed is 0 and 1 according to positive and negative judgement, namely D_e1 ' is just, judgement is 1, D_e1 ' is negative, judgement is 0, this court verdict exports buffer cell by court verdict and exports court verdict, this frame coding is complete, carry out the decoding of next frame subsequently, until all frame likelihood information data decodings of digital receiver demodulation complete.

The check matrix of described check matrix H to be the code check defined in CCSDS standard the be quasi-cyclic LDPC code of R=1/2, the code word size N of this quasi-cyclic LDPC code is 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as:

$H=\left[\begin{array}{ccccc}{0}_L& 0_L& I_L& 0_L& I_L\⊕{\mathrm{\Π}}_1\\ I_L& I_L& 0_L& I_L& {\mathrm{\Π}}_2\⊕{\mathrm{\Π}}_3\⊕{\mathrm{\Π}}_4\\ I_L& {\mathrm{\Π}}_5\⊕{\mathrm{\Π}}_6& 0_L& {\mathrm{\Π}}_7\⊕{\mathrm{\Π}}_8& I_L\end{array}\right]$

I in matrix H _lwith 0 _lbe respectively 2048 × 2048 dimension unit matrix and 0 matrixes, Π _k(k=1,2 ..., 8) be 2048 × 2048 dimension displacement battle arrays, this displacement battle array Π _kt capable (t=0,1,2 ..., 2047) the column position π of nonzero element _k(t) be:

In formula, L=2048, mod represent modular arithmetic, represent and 4t/L is rounded downwards, column position π _kfunction # in (t) _kwith value see in CCSDS standard CC SDS 131.1-O-2 show 3-3, table 3-4, there is accurate cycle characteristics.

Described Addr_CN is that the check matrix H of (8192,4096) LDPC code of R=1/2 calculates according to code check in CCSDS standard.

Described D_llr and D_a1 calculates the likelihood information upgraded, and the step obtaining the side information D_e1 after upgrading is as follows:

If n-th, n is 1,2,3,4,5, it is positive integer that variable node processing unit reads m information D_a1, m from main storage, m ' is 1,2 ... m, m ' represent the sequence number of the individual information of m ' in m information, the individual information D_a1 of m ' (m ') the corresponding lastest imformation D_e1 channel likelihood information D_llr that equals to read from channel information memory adds other m-1 information D_a1 outside the individual information D_a1 of removing m ' (m ').

Described D_a2 calculates the likelihood information upgraded, and the step obtaining the side information D_e2 after upgrading is as follows:

(1) p is established, p is 1,2,3, it is positive integer that code check node processing unit reads k information D_a2, k from main storage, k ' is 1,2 ... the sequence number of k, k ' represent kth ' in k information individual information, kth ' individual information D_a2 (k ') sign bit of corresponding lastest imformation D_e2 is operating as: removing kth ' individual lastest imformation D_a2 (k ') outside the XOR of k-1 D_a2 sign bit;

(2) amplitude of k information D_a2 is compared, try to achieve amplitude min value and amplitude sub-minimum, these two values are multiplied by normalization factor α by correction value multiplier, by amplitude min value and kth ' compared with the amplitude of individual information, if identical, then export sub-minimum, if different, then export minimum value, the scope of α is 0 ~ 1;

(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after upgrading is obtained.

Obtain after described last iteration completes equal last iteration for the information D_e1 ' adjudicating output time the channel likelihood information D_llr that reads from channel information memory add m information D_a1's (m) and value.

Partially-parallel architecture LDPC code interpretation method in a kind of space communication system, comprises and divides LDPC check matrix stage and pipeline system Partly parallel decoding stage:

Divide LDPC check matrix stage etch as follows:

(1) code check defined in CCSDS standard is the quasi-cyclic LDPC code of R=1/2, and the code word size N of this quasi-cyclic LDPC code is 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as

$H=\left[\begin{array}{ccccc}{0}_L& 0_L& I_L& 0_L& I_L\⊕{\mathrm{\Π}}_1\\ I_L& I_L& 0_L& I_L& {\mathrm{\Π}}_2\⊕{\mathrm{\Π}}_3\⊕{\mathrm{\Π}}_4\\ I_L& {\mathrm{\Π}}_5\⊕{\mathrm{\Π}}_6& 0_L& {\mathrm{\Π}}_7\⊕{\mathrm{\Π}}_8& I_L\end{array}\right]$

I in matrix H _lwith 0 _lbe respectively 2048 × 2048 dimension unit matrix and 0 matrixes, Π _k(k=1,2 ..., 8) be 2048 × 2048 dimension displacement battle arrays, this displacement battle array Π _kt capable (t=0,1,2 ..., 2047) the column position π of nonzero element _k(t) be:

In formula, L=2048, mod represent modular arithmetic, represent and 4t/L is rounded downwards, column position π _kfunction # in (t) _kwith value see in CCSDS standard CC SDS 131.1-O-2 show 3-3, table 3-4, there is accurate cycle characteristics;

(2) be divided into 3 to be out of the line the row of the check matrix H of step (1) to be respectively: H1 (0-2047 is capable), H2 (2048-4095 is capable), H3 (4096-6143 is capable); Be divided into by the row of check matrix H 5 super row to be respectively S1 (0-2047 row), S2 (2048-4095 row), P1 (4096-6143 row), P2 (6144-8191 row), P3 (8192-10239 row), this matrix trace inequality as shown in Figure 1;

(3) data storage of definition needed for decoding comprises: channel information memory, main storage and decoding export buffer unit; Channel information memory is used for buffer memory channel likelihood information, and comprise 4 dual port RAMs, the degree of depth of each RAM is 2048; Main storage comprises 15 memory RAM, namely main storage RAM1, RAM2 ..., RAM15, for the side information transmitted between storage of variables node and check-node, each non-zero submatrices in the corresponding check matrix H of each memory RAM, each memory RAM degree of depth is 2048, namely main storage RAM1, RAM2 ..., RAM15 is respectively corresponding:

The submatrix I that RAM1 correspondence super row S1 is corresponding with the H2 that is out of the line _l;

The submatrix I that RAM2 correspondence super row S1 is corresponding with the H3 that is out of the line _l;

The submatrix I that RAM3 correspondence super row S2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM4 correspondence super row S2 is corresponding with the H3 that is out of the line ₅;

The submatrix Π that RAM5 correspondence super row S2 is corresponding with the H3 that is out of the line ₆;

The submatrix I that RAM6 correspondence super row P1 is corresponding with the H1 that is out of the line _l;

The submatrix I that RAM7 correspondence super row P2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM8 correspondence super row P2 is corresponding with the H3 that is out of the line ₇;

The submatrix Π that RAM9 correspondence super row P2 is corresponding with the H3 that is out of the line ₈;

The submatrix I that RAM10 correspondence super row P3 is corresponding with the H1 that is out of the line _l;

The submatrix Π that RAM11 correspondence super row P3 is corresponding with the H1 that is out of the line ₁;

The submatrix Π that RAM12 correspondence super row P3 is corresponding with the H2 that is out of the line ₂;

The submatrix Π that RAM13 correspondence super row P3 is corresponding with the H2 that is out of the line ₃;

The submatrix Π that RAM14 correspondence super row P3 is corresponding with the H2 that is out of the line ₄;

The submatrix I that RAM15 correspondence super row P3 is corresponding with the H3 that is out of the line _l;

Decoding exports buffer unit for exporting decode results;

Pipeline system Partly parallel decoding stage etch is as follows:

(4) channel information memory cell receives and stores these frame likelihood information data current of digital receiver demodulation, and this likelihood information data sequence is stored in 4 RAM of channel information memory cell, one frame likelihood information data are 8192, after this frame receives, channel information memory cell produces one and receives signal and send to iteration control unit, and channel information memory cell receives 8192 data of next frame simultaneously by ping-pong operation;

(5) iteration control unit sends decoding commencing signal to channel information memory cell; Channel information memory cell receives decoding commencing signal, by the likelihood information data sequence ground parallel output 4 circuit-switched data D_llr in 4 RAM to variable node processing module;

(6) 4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, variable node processing module comprises VNU1, VNU2, VNU3, these 5 variable node processing unit of VNU4 and VNU5, this 4 circuit-switched data D_llr is delivered to VNU1 respectively, VNU2, VNU3, VNU4, 0 value is delivered to VNU5, variable node processing module is from the RAM1 main storage simultaneously, RAM2, according to the RAM1 in memory in RAM15, RAM2, the order reading address Addr_VN of RAM15 reads RAM1, RAM2, side information D_a1 in RAM15, if the 1st iteration, the side information D_a1=0 then taken out from main storage, defining by iteration control unit the order reading address Addr_VN is 0, 1, 2, 2047, respectively side information D_a1 is delivered to VNU1 in the following manner, VNU2, VNU3, VNU4, VNU5, variable node processing unit is that 5 roads walk abreast:

The data of RAM1, RAM2 are sequentially read according to Addr_VN and gives VNU1;

The data of RAM3 ~ RAM5 are sequentially read according to Addr_VN and gives VNU2;

The data of RAM6 are sequentially read according to Addr_VN and gives VNU3;

The data of RAM7 ~ RAM9 are sequentially read according to Addr_VN and gives VNU4;

The data of RAM10 ~ RAM15 are sequentially read according to Addr_VN and gives VNU5;

(7) calculate the likelihood information upgraded according to D_llr and D_a1 obtained in step (6), obtain the side information D_e1 after upgrading;

(8) by the side information D_e2 after upgrading in step (7) according to write address Addr_VN write main storage RAM1, RAM2 ..., RAM15, read address Addr_VN identical with write address Addr_VN numerical value, difference is that allocating time is different, generate by iteration control unit, for sequence address 0,1,2 ..., 2047;

(9) what iteration control unit produced code check node processing module reads address Addr_CN, Addr_CN comprises Addr_CN1, Addr_CN2 ... Addr_CN15, Addr_CN1, Addr_CN2 ... Addr_CN15 by step (3) main storage RAM1, RAM2 ..., submatrix that RAM15 is corresponding calculates;

Code check node processing module comprises CNU1, CNU2, CNU3, code check node processing module is according to reading address Addr_CN, from main storage RAM1, RAM2 ..., side information D_e1 in RAM15 in the following manner in reading step (8), be designated as side information D_a2, deliver to CNU1, CNU2, the CNU3 in code check node processing module, CNU1, CNU2, CNU3 of code check node processing module are that 3 roads walk abreast;

Data by RAM10, RAM11 give CNU1 according to Addr_CN10, Addr_CN11 reading;

The data of RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 are read according to Addr_CN1, Addr_CN3, Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 respectively and gives CNU2;

The data of RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 are read according to Addr_CN2, Addr_CN4, Addr_CN5, Addr_CN8, Addr_CN9, Addr_CN15 respectively and gives CNU3;

(10) calculate the likelihood information upgraded according to the D_a2 obtained in step (9), obtain the side information D_e2 after upgrading;

(11) by the side information D_e2 after upgrading in step (10) according to address Addr_CN1, Addr_CN2 ... Addr_CN15 write respectively RAM1 in main storage, RAM2 ..., after RAM15, this time iteration settling signal is sent to iteration control unit, read address Addr_CN identical with write address Addr_CN numerical value, difference is that allocating time is different, generates by iteration control unit;

(12) iteration control unit receives this time iteration settling signal of step (11), start next iteration, namely step is repeated according to step (5) ~ step (12), until reach the maximum iteration time M of this frame of setting, produce decoding termination signal Dec_E, then, the D_e1 ' obtained after last iteration being completed is 0 and 1 according to positive and negative judgement, namely D_e1 ' is just, judgement is 1, D_e1 ' is negative, judgement is 0, this court verdict exports buffer cell by court verdict and exports court verdict, this frame coding is complete, return the decoding that step (4) carries out next frame subsequently, until all frame likelihood information data decodings of digital receiver demodulation complete.

Step (9) and the Addr_CN described in (11) are that the H matrix computations of (8192,4096) LDPC code of R=1/2 obtains according to code check in CCSDS standard.Such as with super, submatrix I corresponding to P3 is arranged for the H1 that is out of the line _l, Π ₁be respectively as shown in Figure 4.So the value of address Addr_CN is 1644,1645 ..., 2047,1536,1537 ..., 1643,0,1 ..., 1535.In like manner can obtain other address, all address Addr_CN as shown in Figure 3.

In step (7), D_llr and D_a1 calculates the likelihood information upgraded, and the step obtaining the side information D_e1 after upgrading is as follows:

If n-th, n is 1,2,3,4,5, it is positive integer that variable node processing unit reads m information D_a1, m from main storage, m ' is 1,2 ... m, m ' represent the sequence number of the individual information of m ' in m information, the individual information D_a1 of m ' (m ') the corresponding lastest imformation D_e1 channel likelihood information D_llr that equals to read from channel information memory adds other m-1 information D_a1 outside the individual information D_a1 of removing m ' (m ').

Such as, during for n=2, corresponding VNU2 unit, reads 1 channel likelihood information D_llr, reads m=3 information D_a1 from the RAM3 ~ RAM5 of main storage from channel information memory.Lastest imformation D_e1=D_llr+D_a1 (the 2)+D_a1 (3) that so a m '=1 information D_a1 (1) is corresponding; Lastest imformation D_e1=D_llr+D_a1 (the 1)+D_a1 (3) that a m '=2 information D_a1 (2) are corresponding; Lastest imformation D_e1=D_llr+D_a1 (the 1)+D_a1 (2) that a m '=3 information D_a1 (3) are corresponding;

The channel likelihood information D_llr that what in step (12), last iteration obtained after completing read when equaling last iteration for the information D_e1 ' adjudicating output from channel information memory add m information D_a1's (m) and value.Such as, during for n=2, corresponding VNU2 unit, reads 1 channel likelihood information D_llr, reads m=3 information D_a1 from the RAM3 ~ RAM5 of main storage from channel information memory.So D_e1 '=D_llr+D_a1 (1)+D_a1 (2)+D_a1 (3), in implementation structure, here combined by the lastest imformation D_e1 computational item corresponding with the individual information D_a1 of m ', only first need calculate D_e1 ' and then deduct D_a1 (m ') thus overall reduction implementation complexity.

Lastest imformation the D_e1=D_e1 '-D_a1 (1) that so a m '=1 information D_a1 (1) is corresponding; Lastest imformation the D_e1=D_e1 '-D_a1 (2) that a m '=2 information D_a1 (2) are corresponding; Lastest imformation the D_e1=D_e1 '-D_a1 (3) that a m '=3 information D_a1 (3) are corresponding;

In step (10), D_a2 calculates the likelihood information upgraded, the step obtaining the side information D_e2 after upgrading is as follows: (1) establishes p, p is 1,2,3, code check node processing unit reads k information D_a2 from main storage, k is positive integer, k ' is 1,2 ... k, the sign bit of the lastest imformation D_e2 that k ' represents the kth in k information the sequence number of the individual information ', kth ' individual information D_a2 (k ') is corresponding is operating as: removing kth ' individual lastest imformation D_a2 (k ') outside the XOR of k-1 D_a2 sign bit.(2) amplitude of k information D_a2 is compared, try to achieve amplitude min value and amplitude sub-minimum, these two values are multiplied by normalization factor α by correction value multiplier, by amplitude min value and kth ' compared with the amplitude of individual information, if identical, then export sub-minimum, if different, then export minimum value, the scope of α is 0 ~ 1.(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after upgrading is obtained.Such as, for p=3, corresponding CNU3 unit, k=6 data D_a2, so kth from RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 of main storage read ' individual information D_a2 (k ') corresponding lastest imformation D_e2 computational methods are:

The relatively size of k=6 data D_a2, obtain minimum value D_a2 (min1) and sub-minimum D_a2 (min2), so for kth '=1 information D_a2 (k ') sign bit sgn (1 ')=XOR { sgn [D_a2 (2)] of corresponding lastest imformation D_e2, sgn [D_a2 (3)], sgn [D_a2 (4)], sgn [D_a2 (5)], sgn [D_a2 (6)] }, if so D_a2 (1)=D_a2 (min1), D_e2=sgn (1 ') × D_a2 (min2), otherwise D_e2=sgn (1 ') × D_a2 (min1), for kth '=2 information D_a2 (k ') sign bit sgn (2 ')=XOR { sgn [D_a2 (1)] of corresponding lastest imformation D_e2, sgn [D_a2 (3)], sgn [D_a2 (4)], sgn [D_a2 (5)], sgn [D_a2 (6)] }, if so D_a2 (2)=D_a2 (min1), D_e2=sgn (1 ') × D_a2 (min2), otherwise D_e2=sgn (1 ') × D_a2 (min1), for kth '=3,4,5,6 in like manner can to obtain.

Embodiment:

Modem platform carries out upper plate test, FPGA model is xc6slx150, use ISE13.4 and ModelSim6.5g developing instrument, completed the design of quasi-cyclic LDPC (8192,4096) code decoder by Verilog HDL hardware description language.

When data rate is 4Mbps, modulation system is BPSK, and when selecting 1/2 code check (8192,4096) LDPC code, system test result is: when decoding iteration number of times maximum is set to M=45, corresponding BER=1-10 ^-7demodulation threshold be 2.2dB, corresponding coding gain is 9dB.

The resource requirement of this decoder is as follows: register number: 2221, LUT number: 2119; 18k memory RAM: 29;

Non-elaborated part of the present invention belongs to techniques well known.

Claims (10)

1. a partially-parallel architecture LDPC code decoding system in space communication system, is characterized in that: comprise iteration control unit, channel information memory, main storage, variable node processing module, code check node processing module, court verdict output buffer cell;

Channel information memory comprises 4 dual port RAMs, the degree of depth of each RAM is L=2048, main storage comprises 15 memory RAM, namely main storage RAM1, RAM2 ..., RAM15, for the side information transmitted between storage of variables node and check-node, the code efficiency that each memory RAM correspondence defines in CCSDS standard is each non-zero submatrices in the check matrix H of the quasi-cyclic LDPC code of R=1/2, each memory RAM degree of depth is L=2048, namely main storage RAM1, RAM2 ..., RAM15 is respectively corresponding as follows:

The submatrix I that RAM1 correspondence super row S1 is corresponding with the H2 that is out of the line _l;

The submatrix I that RAM2 correspondence super row S1 is corresponding with the H3 that is out of the line _l;

The submatrix I that RAM3 correspondence super row S2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM4 correspondence super row S2 is corresponding with the H3 that is out of the line ₅;

The submatrix Π that RAM5 correspondence super row S2 is corresponding with the H3 that is out of the line ₆;

The submatrix I that RAM6 correspondence super row P1 is corresponding with the H1 that is out of the line _l;

The submatrix I that RAM7 correspondence super row P2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM8 correspondence super row P2 is corresponding with the H3 that is out of the line ₇;

The submatrix Π that RAM9 correspondence super row P2 is corresponding with the H3 that is out of the line ₈;

The submatrix I that RAM10 correspondence super row P3 is corresponding with the H1 that is out of the line _l;

The submatrix Π that RAM11 correspondence super row P3 is corresponding with the H1 that is out of the line ₁;

The submatrix Π that RAM12 correspondence super row P3 is corresponding with the H2 that is out of the line ₂;

The submatrix Π that RAM13 correspondence super row P3 is corresponding with the H2 that is out of the line ₃;

The submatrix Π that RAM14 correspondence super row P3 is corresponding with the H2 that is out of the line ₄;

The submatrix I that RAM15 correspondence super row P3 is corresponding with the H3 that is out of the line _l;

The row of check matrix H is divided into 3 to be out of the line being respectively H1, H2, H3, and H1 is that 0-2047 is capable, H2 is that 2048-4095 is capable, H3 is that 4096-6143 is capable; The row of check matrix H are divided into 5 super row S1, S2, P1, P2, P3, S1 is 0-2047 row, S2 is 2048-4095 row, P1 is 4096-6143 row, P2 is 6144-8191 row, P3 is 8192-10239 row;

Variable node processing module comprises these 5 variable node processing unit of VNU1, VNU2, VNU3, VNU4 and VNU5, and variable node processing unit is that 5 roads walk abreast;

Check-node address processing module comprises these three code check node processing unit of CNU1, CNU2, CNU3, and CNU1, CNU2, CNU3 are that 3 roads walk abreast;

Channel information memory cell receives and stores these frame likelihood information data current of digital receiver demodulation, and this likelihood information data sequence is stored in 4 RAM of channel information memory cell, one frame likelihood information data are 8192, after this frame receives, channel information memory cell produces one and receives signal and send to iteration control unit, and channel information memory cell receives 8192 data of next frame simultaneously by ping-pong operation;

Iteration control unit sends decoding commencing signal to channel information memory cell after receiving and receiving signal, channel information memory cell receives decoding commencing signal, by the likelihood information data sequence ground parallel output 4 circuit-switched data D_llr in 4 RAM to variable node processing module

4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, this 4 circuit-switched data D_llr is delivered to VNU1 respectively, VNU2, VNU3, VNU4, 0 value is delivered to VNU5, variable node processing module is from the RAM1 main storage simultaneously, RAM2, according to the RAM1 in memory in RAM15, RAM2, the order reading address Addr_VN of RAM15 reads RAM1, RAM2, side information D_a1 in RAM15, if the 1st iteration, the side information D_a1=0 then taken out from main storage, defining by iteration control unit the order reading address Addr_VN is 0, 1, 2, 2047, respectively side information D_a1 is delivered to VNU1 in the following manner, VNU2, VNU3, VNU4, VNU5:

The data of RAM1, RAM2 are sequentially read according to Addr_VN and gives VNU1;

The data of RAM3 ~ RAM5 are sequentially read according to Addr_VN and gives VNU2;

The data of RAM6 are sequentially read according to Addr_VN and gives VNU3;

The data of RAM7 ~ RAM9 are sequentially read according to Addr_VN and gives VNU4;

The data of RAM10 ~ RAM15 are sequentially read according to Addr_VN and gives VNU5;

Calculate the likelihood information upgraded according to D_llr and D_a1, obtain the side information D_e1 after upgrading; By the side information D_e1 after upgrading according to write address Addr_VN write main storage RAM1, RAM2 ..., RAM15, read address Addr_VN identical with write address Addr_VN numerical value, difference is that allocating time is different, generates by iteration control unit, for sequence address 0,1,2 ..., 2047;

What iteration control unit produced check-node address processing module reads address Addr_CN, Addr_CN comprises Addr_CN1, Addr_CN2 ..., Addr_CN15, Addr_CN1, Addr_CN2 ..., Addr_CN15 by step (3) main storage RAM1, RAM2 ..., submatrix that RAM15 is corresponding calculates;

Code check node processing module according to reading address Addr_CN, from main storage RAM1, RAM2 ..., read side information D_e1 in the following manner in RAM15, be designated as side information D_a2, deliver to CNU1, CNU2, CNU3 in check-node address processing module;

Data by RAM10, RAM11 give CNU1 according to Addr_CN10, Addr_CN11 reading;

The data of RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 are read according to Addr_CN1, Addr_CN3, Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 respectively and gives CNU2;

The data of RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 are read according to Addr_CN2, Addr_CN4, Addr_CN5, Addr_CN8, Addr_CN9, Addr_CN15 respectively and gives CNU3;

The likelihood information upgraded is calculated, the side information D_e2 after again being upgraded according to the side information D_a2 obtained;

By the side information D_e2 after renewal according to address Addr_CN1, Addr_CN2 ..., Addr_CN15 write respectively RAM1 in main storage, RAM2 ..., after RAM15, this time iteration settling signal is sent to iteration control unit, read address Addr_CN identical with write address Addr_CN numerical value, difference is that allocating time is different, generates by iteration control unit;

Iteration control unit receives this time iteration settling signal, start next iteration, until reach the maximum iteration time M of this frame of setting, produce decoding termination signal Dec_E, then, the side information D_e1 ' obtained after last iteration being completed is 0 and 1 according to positive and negative judgement, namely D_e1 ' is just, judgement is 1, D_e1 ' is negative, judgement is 0, this court verdict exports buffer cell by court verdict and exports court verdict, this frame coding is complete, carry out the decoding of next frame subsequently, until all frame likelihood information data decodings of digital receiver demodulation complete.

2. partially-parallel architecture LDPC code decoding system in a kind of space communication system according to claim 1, it is characterized in that: the check matrix of described check matrix H to be the code check defined in CCSDS standard the be quasi-cyclic LDPC code of R=1/2, the code word size N of this quasi-cyclic LDPC code is 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as:

$H=\left[\begin{array}{ccccc}{0}_L& 0_L& I_L& 0_L& I_L\⊕{\mathrm{\Π}}_1\\ I_L& I_L& 0_L& I_L& {\mathrm{\Π}}_2\⊕{\mathrm{\Π}}_3\⊕{\mathrm{\Π}}_4\\ I_L& {\mathrm{\Π}}_5\⊕{\mathrm{\Π}}_6& 0_L& {\mathrm{\Π}}_7\⊕{\mathrm{\Π}}_8& I_L\end{array}\right]$

I in matrix H _lwith 0 _lbe respectively 2048 × 2048 dimension unit matrix and 0 matrixes, Π _k(k=1,2 ..., 8) be 2048 × 2048 dimension displacement battle arrays, this displacement battle array Π _kt capable (t=0,1,2 ..., 2047) the column position π of nonzero element _k(t) be:

In formula, L=2048, mod represent modular arithmetic, represent and 4t/L is rounded downwards, θ _kwith for column position π _kfunction in (t).

3. partially-parallel architecture LDPC code decoding system in a kind of space communication system according to claim 2, it is characterized in that: described Addr_CN is that the check matrix H of (8192,4096) LDPC code of R=1/2 calculates according to code check in CCSDS standard.

4. partially-parallel architecture LDPC code decoding system in a kind of space communication system according to claim 1, is characterized in that: described D_llr and D_a1 calculates the likelihood information upgraded, and the step obtaining the side information D_e1 after upgrading is as follows:

If n-th, n is 1,2,3,4,5, it is positive integer that variable node processing unit reads m information D_a1, m from main storage, m ' is 1,2 ... m, m ' represent the sequence number of the individual information of m ' in m information, the individual information D_a1 of m ' (m ') the corresponding lastest imformation D_e1 channel likelihood information D_llr that equals to read from channel information memory adds other m-1 information D_a1 outside the individual information D_a1 of removing m ' (m ').

5. partially-parallel architecture LDPC code decoding system in a kind of space communication system according to claim 1, is characterized in that: described D_a2 calculates the likelihood information upgraded, and the step obtaining the side information D_e2 after upgrading is as follows:

(1) p is established, p is 1,2,3, it is positive integer that code check node processing unit reads k information D_a2, k from main storage, k ' is 1,2 ... the sequence number of k, k ' represent kth ' in k information individual information, kth ' individual information D_a2 (k ') sign bit of corresponding lastest imformation D_e2 is operating as: removing kth ' individual lastest imformation D_a2 (k ') outside the XOR of k-1 D_a2 sign bit;

(2) amplitude of k information D_a2 is compared, try to achieve amplitude min value and amplitude sub-minimum, these two values are multiplied by normalization factor α by correction value multiplier, by amplitude min value and kth ' compared with the amplitude of individual information, if identical, then export sub-minimum, if different, then export minimum value, the scope of α is 0 ~ 1;

(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after upgrading is obtained.

6. partially-parallel architecture LDPC code decoding system in a kind of space communication system according to claim 1, is characterized in that: obtain after described last iteration completes equal last iteration for the information D_e1 ' adjudicating output time the channel likelihood information D_llr that reads from channel information memory add m information D_a1's (m) and value.

7. a partially-parallel architecture LDPC code interpretation method in space communication system, is characterized in that: comprise and divide LDPC check matrix stage and pipeline system Partly parallel decoding stage:

Described division LDPC check matrix stage etch is as follows:

(1) code check defined in CCSDS standard is the quasi-cyclic LDPC code of R=1/2, and the code word size N of this quasi-cyclic LDPC code is 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as

$H=\left[\begin{array}{ccccc}{0}_L& 0_L& I_L& 0_L& I_L\⊕{\mathrm{\Π}}_1\\ I_L& I_L& 0_L& I_L& {\mathrm{\Π}}_2\⊕{\mathrm{\Π}}_3\⊕{\mathrm{\Π}}_4\\ I_L& {\mathrm{\Π}}_5\⊕{\mathrm{\Π}}_6& 0_L& {\mathrm{\Π}}_7\⊕{\mathrm{\Π}}_8& I_L\end{array}\right]$

I in matrix H _lwith 0 _lbe respectively 2048 × 2048 dimension unit matrix and 0 matrixes, Π _k(k=1,2 ..., 8) be 2048 × 2048 dimension displacement battle arrays, this displacement battle array Π _kt capable (t=0,1,2 ..., 2047) the column position π of nonzero element _k(t) be:

In formula, L=2048, mod represent modular arithmetic, represent and 4t/L is rounded downwards, θ _kwith for column position π _kfunction in (t);

(2) be divided into 3 to be out of the line the row of the check matrix H of step (1) to be respectively: H1 (0-2047 is capable), H2 (2048-4095 is capable), H3 (4096-6143 is capable); 5 super row are divided into by the row of check matrix H to be respectively S1 (0-2047 row), S2 (2048-4095 row), P1 (4096-6143 row), P2 (6144-8191 row), P3 (8192-10239 row);

(3) data storage of definition needed for decoding comprises: channel information memory, main storage and decoding export buffer unit; Channel information memory is used for buffer memory channel likelihood information, and comprise 4 dual port RAMs, the degree of depth of each RAM is 2048; Main storage comprises 15 memory RAM, namely main storage RAM1, RAM2 ..., RAM15, for the side information transmitted between storage of variables node and check-node, each non-zero submatrices in the corresponding check matrix H of each memory RAM, each memory RAM degree of depth is 2048, namely main storage RAM1, RAM2 ..., RAM15 is respectively corresponding:

The submatrix I that RAM1 correspondence super row S1 is corresponding with the H2 that is out of the line _l;

The submatrix I that RAM2 correspondence super row S1 is corresponding with the H3 that is out of the line _l;

The submatrix I that RAM3 correspondence super row S2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM4 correspondence super row S2 is corresponding with the H3 that is out of the line ₅;

The submatrix Π that RAM5 correspondence super row S2 is corresponding with the H3 that is out of the line ₆;

The submatrix I that RAM6 correspondence super row P1 is corresponding with the H1 that is out of the line _l;

The submatrix I that RAM7 correspondence super row P2 is corresponding with the H2 that is out of the line _l;

The submatrix Π that RAM8 correspondence super row P2 is corresponding with the H3 that is out of the line ₇;

The submatrix Π that RAM9 correspondence super row P2 is corresponding with the H3 that is out of the line ₈;

The submatrix I that RAM10 correspondence super row P3 is corresponding with the H1 that is out of the line _l;

The submatrix Π that RAM11 correspondence super row P3 is corresponding with the H1 that is out of the line ₁;

The submatrix Π that RAM12 correspondence super row P3 is corresponding with the H2 that is out of the line ₂;

The submatrix Π that RAM13 correspondence super row P3 is corresponding with the H2 that is out of the line ₃;

The submatrix Π that RAM14 correspondence super row P3 is corresponding with the H2 that is out of the line ₄;

The submatrix I that RAM15 correspondence super row P3 is corresponding with the H3 that is out of the line _l;

Decoding exports buffer unit for exporting decode results;

Described pipeline system Partly parallel decoding stage etch is as follows:

(4) channel information memory cell receives and stores these frame likelihood information data current of digital receiver demodulation, and this likelihood information data sequence is stored in 4 RAM of channel information memory cell, one frame likelihood information data are 8192, after this frame receives, channel information memory cell produces one and receives signal and send to iteration control unit, and channel information memory cell receives 8192 data of next frame simultaneously by ping-pong operation;

(5) iteration control unit sends decoding commencing signal to channel information memory cell; Channel information memory cell receives decoding commencing signal, by the likelihood information data sequence ground parallel output 4 circuit-switched data D_llr in 4 RAM to variable node processing module;

(6) 4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, variable node processing module comprises VNU1, VNU2, VNU3, these 5 variable node processing unit of VNU4 and VNU5, this 4 circuit-switched data D_llr is delivered to VNU1 respectively, VNU2, VNU3, VNU4, 0 value is delivered to VNU5, variable node processing module is from the RAM1 main storage simultaneously, RAM2, according to the RAM1 in memory in RAM15, RAM2, the order reading address Addr_VN of RAM15 reads RAM1, RAM2, side information D_a1 in RAM15, if the 1st iteration, the side information D_a1=0 then taken out from main storage, defining by iteration control unit the order reading address Addr_VN is 0, 1, 2, 2047, respectively side information D_a1 is delivered to VNU1 in the following manner, VNU2, VNU3, VNU4, VNU5, variable node processing unit is that 5 roads walk abreast:

The data of RAM1, RAM2 are sequentially read according to Addr_VN and gives VNU1;

The data of RAM3 ~ RAM5 are sequentially read according to Addr_VN and gives VNU2;

The data of RAM6 are sequentially read according to Addr_VN and gives VNU3;

The data of RAM7 ~ RAM9 are sequentially read according to Addr_VN and gives VNU4;

The data of RAM10 ~ RAM15 are sequentially read according to Addr_VN and gives VNU5;

(7) calculate the likelihood information upgraded according to D_llr and D_a1 obtained in step (6), obtain the side information D_e1 after upgrading;

(8) by the side information D_e2 after upgrading in step (7) according to write address Addr_VN write main storage RAM1, RAM2 ..., RAM15, read address Addr_VN identical with write address Addr_VN numerical value, difference is that allocating time is different, generate by iteration control unit, for sequence address 0,1,2 ..., 2047;

(9) what iteration control unit produced code check node processing module reads address Addr_CN, Addr_CN comprises Addr_CN1, Addr_CN2 ... Addr_CN15, Addr_CN1, Addr_CN2 ... Addr_CN15 by step (3) main storage RAM1, RAM2 ..., submatrix that RAM15 is corresponding calculates;

Code check node processing module comprises CNU1, CNU2, CNU3, code check node processing module is according to reading address Addr_CN, from main storage RAM1, RAM2 ..., side information D_e1 in RAM15 in the following manner in reading step (8), be designated as side information D_a2, deliver to CNU1, CNU2, the CNU3 in code check node processing module, CNU1, CNU2, CNU3 of code check node processing module are that 3 roads walk abreast;

Data by RAM10, RAM11 give CNU1 according to Addr_CN10, Addr_CN11 reading;

The data of RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 are read according to Addr_CN1, Addr_CN3, Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 respectively and gives CNU2;

The data of RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 are read according to Addr_CN2, Addr_CN4, Addr_CN5, Addr_CN8, Addr_CN9, Addr_CN15 respectively and gives CNU3;

(10) calculate the likelihood information upgraded according to the D_a2 obtained in step (9), obtain the side information D_e2 after upgrading;

(11) by the side information D_e2 after upgrading in step (10) according to address Addr_CN1, Addr_CN2 ... Addr_CN15 write respectively RAM1 in main storage, RAM2 ..., after RAM15, this time iteration settling signal is sent to iteration control unit, read address Addr_CN identical with write address Addr_CN numerical value, difference is that allocating time is different, generates by iteration control unit;

(12) iteration control unit receives this time iteration settling signal of step (11), start next iteration, namely step is repeated according to step (5) ~ step (12), until reach the maximum iteration time M of this frame of setting, produce decoding termination signal Dec_E, then, the D_e1 ' obtained after last iteration being completed is 0 and 1 according to positive and negative judgement, namely D_e1 ' is just, judgement is 1, D_e1 ' is negative, judgement is 0, this court verdict exports buffer cell by court verdict and exports court verdict, this frame coding is complete, return the decoding that step (4) carries out next frame subsequently, until all frame likelihood information data decodings of digital receiver demodulation complete.

8. partially-parallel architecture LDPC code interpretation method in a kind of space communication system according to claim 7, it is characterized in that: step (9) and the Addr_CN described in (11) are that the H matrix computations of (8192,4096) LDPC code of R=1/2 obtains according to code check in CCSDS standard.

9. partially-parallel architecture LDPC code interpretation method in a kind of space communication system according to claim 7, it is characterized in that: in described step (7), D_llr and D_a1 calculates the likelihood information upgraded, the step obtaining the side information D_e1 after upgrading is as follows:

If n-th, n is 1,2,3,4,5, it is positive integer that variable node processing unit reads m information D_a1, m from main storage, m ' is 1,2 ... m, m ' represent the sequence number of the individual information of m ' in m information, the individual information D_a1 of m ' (m ') the corresponding lastest imformation D_e1 channel likelihood information D_llr that equals to read from channel information memory adds other m-1 information D_a1 outside the individual information D_a1 of removing m ' (m ').

10. partially-parallel architecture LDPC code interpretation method in a kind of space communication system according to claim 7, is characterized in that: in described step (10), D_a2 calculates the likelihood information upgraded, and the step obtaining the side information D_e2 after upgrading is as follows:

(1) p is established, p is 1,2,3, it is positive integer that code check node processing unit reads k information D_a2, k from main storage, k ' is 1,2 ... the sequence number of k, k ' represent kth ' in k information individual information, kth ' individual information D_a2 (k ') sign bit of corresponding lastest imformation D_e2 is operating as: removing kth ' individual lastest imformation D_a2 (k ') outside the XOR of k-1 D_a2 sign bit;

(2) amplitude of k information D_a2 is compared, try to achieve amplitude min value and amplitude sub-minimum, these two values are multiplied by normalization factor α by correction value multiplier, by amplitude min value and kth ' compared with the amplitude of individual information, if identical, then export sub-minimum, if different, then export minimum value, the scope of α is 0 ~ 1;

(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after upgrading is obtained.