CN110278000A - LDPC code parallel decoding FPGA based on DVB-S2 standard realizes framework and interpretation method - Google Patents
LDPC code parallel decoding FPGA based on DVB-S2 standard realizes framework and interpretation method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1191—Codes on graphs other than LDPC codes
- H03M13/1194—Repeat-accumulate [RA] codes
- H03M13/1197—Irregular repeat-accumulate [IRA] codes
Abstract
The invention discloses a kind of, and the LDPC code parallel decoding FPGA based on DVB-S2 standard realizes framework and interpretation method, mainly includes serioparallel exchange module, input buffer module, variable node update module, de-interleaver module, nodal cache module and check-node update module.Based on the quasi- circulation feature of DVB-S2 standard IRA-LDPC code, the results of intermediate calculations in parallel decoding interweaves between only being arranged and 2-dimensional interleaving can be realized in column cyclic shifts, and two dimension operation is reduced to two one-dimensional operations.
Description
Technical field
The invention belongs to generation information technology fields, especially FPGA technology.
Background technique
Use irregular accumulation (IRA) loe-density parity-check code (LDPC) code that repeats as channel coding side in DVB-S2 standard
On the one hand case can promote coding gain using IRA-LDPC, another aspect code can be used multidiameter delay decoding, be promoted when decoding
The handling capacity of system.The decoding algorithm for general of LDPC is confidence spread (BP) algorithm, is a kind of probability decoding algorithm of iteration.
BP decoding algorithm includes that variable node is updated with check-node two key links of update, two links in Parallel Decoding Algorithm
Between results of intermediate calculations need to carry out 2-dimensional interleaving.
Currently existing scheme is in terms of storage capacity and delay process, and there is also many problems.
Summary of the invention
Goal of the invention: providing a kind of LDPC code parallel decoding FPGA realization framework based on DVB-S2 standard, existing to solve
There is the above problem existing for technology.
A kind of technical solution: LDPC code parallel decoding FPGA realization framework based on DVB-S2 standard, comprising:
Serioparallel exchange module carries out parallel memorizing control for inputting to serial decoding, and previous systems code is distinguished in order
Parallel memorizing into N number of input-buffer, behind check code serially store into N number of input-buffer respectively in order；
Input buffer module is made of, single-input single-output N number of SAM Stand Alone Memory, storage decoding input, each memory
Storage depth be code length divided by N；
Variable node update module is made of N number of independent variable node updates module, and variable node is updated every time from corresponding
A data are read in input-buffer, read multiple data by Iy_c control word from nodal cache, are updated and are advised by variable node
After then updating, then store into nodal cache by Iy_c control word；
De-interleaver module is made of positive interleaver and inverse interleaver, between the storage address to realize nodal cache data
The cyclic shifts to interweave with N number of data；
Positive interleaver realize nodal cache data by intertexture and column cyclic shifts between the column of It_c control word rule, and it is defeated
It is updated out to variable node；Data are moved by the interior circulation of column of the inverse rule of It_c control word after inverse interleaver realization variable node updates
Interweave between position and column, and exports to nodal cache；
Nodal cache module is made of, two-output impulse generator N number of SAM Stand Alone Memory, and all memories are all simultaneously by identical
Address is read or storing data, and the intermediate data after the corresponding storage road N check-node update, storage depth is in check matrix
Each the sum of all rows weight by row block；
Check-node update module is made of N number of independent check-node update module, and check-node is updated every time from node
Read multiple data by Ix_c control word in caching, after check-node update Policy Updates, then by Ix_c control word store to
In nodal cache；
Ix_c is that check-node updates control word, is check matrix each by the set of every every trade weight in row block, Iy_c
Control word is updated for variable node, is set of the check matrix by first column weight of every piece in column block, It_c is interleaver control
Word, including interleaver between the column after reading N circuit-switched data on interweave the column of nodal cache access address control word and appropriate address
Cyclic shifts control word, N are predetermined value.
Based on the interpretation method of framework described in claim 1, include the following steps:
(1) it initializes, nodal cache zero setting, check-node, which updates, is loaded into Ix_c control word, variable node update loading Iy_
C control word and interleaver are loaded into It_c control word；
(2) decoding input, when detection decoding input enables effective, counter is started counting；When previous systems code, counter
Chip selection signal divided by N remainder as N number of input-buffer, counter are rounded divided by N and are used as each input-buffer address signal；Afterwards
When the check code of face, counter is used as each input-buffer address signal after deviating divided by Q remainder adding system code storage address, counts
Device is rounded divided by Q and is used as N number of input-buffer chip selection signal；After entire code word end of input, start to decode, wherein variable node is more
The update of new and check-node is carried out in order is once known as a decoding iteration, and decoding continuous for high speed needs to design table tennis
The caching of pang buffer structure progress decoding input data；
(3) variable node updates, and it is that input-buffer storage depth and Iy_c are controlled that variable node, which updates the number executed,
The storage depth of word, the node number that variable node updates every time are determined by Iy_c control word；
More new technological process are as follows: variable node update module sends out variable node update times control word, a side in order first
Corresponding input-buffer is read in face, on the other hand reads Iy_c control word, obtains this number for updating variable node；Next is read
The Iy_c control word taken out is sent into positive interleaver, according to It_c control word numerical value, obtains the group node caching of this update
Read address and corresponding Control of circular bit shift word；Then it reads the slow class value of N circuit node simultaneously by address and is recycled
Displacement is finally sent into each variable node update module by road and is updated operation；Updated data are sent into inverse interleaver, root
After carrying out inverse cyclic shift according to It_c control word, address is read according still further to It_c and is stored back in nodal cache；
(4) check-node updates: after variable node updates, carrying out check-node update, check-node update times are Ix_
C control word storage depth, the node number that check-node updates every time are determined by Ix_c control word；
More new technological process are as follows: check-node update module sends out check-node update times control word in order first, reads
Ix_c control word obtains this number for updating check-node；Secondly the Ix_c control word read out is added up in sequence
It is converted into a group node buffer read address；Then a class value of N circuit node caching is read by address, is finally sent by road each
Check-node update module carries out operation；Reading address of the updated data by weight of Iy_c control word is stored back to nodal cache
In；
(5) decoding output, when the decoding iteration number of check-node more reaches maximum decoding iteration number, executes decoding
Output, and nodal cache is reset；
More new technological process are as follows: read nodal cache and input-buffer according to variable node more new technological process, it is defeated to be sent into each decoding
Module carries out operation out, and by the road N output decoding hard decision data；Simultaneously according to variable node more new technological process zero deposit node
In caching, realizes and reset.
In a further embodiment, the interleaver control word design is specific as follows:
Setting k first as information bit length, m is verification bit length, and n is code length, then n=m+k, Q=(n-k)/N is defined,
If IRA-LDPC code check matrix is H, then it is a sparse matrix that check matrix left-half size, which is m × k, and right half part is big
It is small for m × m be a full rank lower triangular matrix, be is added to constitute with the unit diagonal matrix of line down by unit diagonal matrix, general
Check matrix is divided into N × n/N block by every Q row, every N column, then check matrix left-half submatrix is right for circulation between every piece up and down
Shifting relationship；
When interleaver control word designs, first check matrix right half part exchange by column；Then to each column block,
Check bit coding is carried out according to the sequence being connected between block, block after antecedent, each check bit coding is made of left and right two parts:
Left-hand component represents row number, and from 1 to N, the serial number of each check bit of right part representative, serial number is by column block from left to right suitable
Sequence superposition；First row block number data finally is read by row, after carrying out ascending order arrangement to the right-hand component of number, that is, completes to hand over
The design of device control word is knitted, wherein the data directory after sequence is the control word that interweaves between arranging, the left-hand component of number is circulation in column
Shift control word.
The utility model has the advantages that
1. proposing to update (VPR), interleaver (It), section by serioparallel exchange (S2P), input-buffer (RAM_L), variable node
Point cache (RAM_P) and check-node update the LDPC code high-speed parallel based on DVB-S2 standard of the composition such as six parts (SPR)
Decoder architecture.This structure can realize the pipelining that variable node updates and check-node updates, the i.e. reading of node updates
Take, interweave, calculating, it is inverse interweave and storage while carrying out, improve the handling capacity of ldpc decoder.
2. propose using by column number, by the interleaver control word design method of row storage, this method according to block after antecedent,
The sequence being connected between block carries out check bit coding, and each check bit coding is made of left and right two parts: left-hand component represents
Row number, the serial number of each check bit of right part representative.First row block number data is read by row, to the right portion of number
Divide after carrying out ascending order arrangement, i.e. the design of completion interleaver control word.
Detailed description of the invention
Fig. 1 is decoder architecture schematic diagram.
Fig. 2 is check matrix exemplary diagram.
Fig. 3 is the check matrix after column exchange.
Fig. 4 is the check matrix after coding.
Specific embodiment
As shown in Figure 1, the IRA-LDPC code parallel decoding FPGA implementation method master based on DVB-S2 standard designed herein
To include following components: serioparallel exchange (S2P), input-buffer (RAM_L), variable node update (VPR), interleaver
(It), nodal cache (RAM_P) and check-node update the composition such as six parts (SPR).
(1) serioparallel exchange (S2P).Serial decoding is inputted and carries out parallel memorizing control, previous systems code is distinguished in order
Parallel memorizing into 360 input-buffers (RAM_L), behind check code serially stored respectively in order to 360 input-buffers
(RAM_L) in.
(2) input-buffer (RAM_L).It is made of 360 SAM Stand Alone Memories (RAM), single-input single-output, storage decoding is defeated
Enter (likelihood ratio), the storage depth of each memory is code length divided by 360.
(3) variable node updates (VPR).It is made of 360 independent variable node updates (VPR) modules, variable node is every
Secondary update reads a data from corresponding input-buffer (RAM_L), reads from nodal cache (RAM_P) by Iy_c control word
Multiple data store after variable node update (VPR) Policy Updates, then by Iy_c control word into nodal cache (RAM_P).
(4) interleaver (It).It is made of, realizes nodal cache (RAM_P) positive interleaver (It1) and inverse interleaver (It2)
(column) cyclic shifts to interweave between the storage address (column) of data with 360 data.Positive interleaver (It1) realizes nodal cache
(RAM_P) data are by intertexture and column cyclic shifts between the column of It_c control word rule, and export to variable node and update
(VPR)；Inverse interleaver (It2) realization variable node updates (VPR), and data are moved by the interior circulation of column of the inverse rule of It_c control word afterwards
Interweave between position and column, and exports to nodal cache (RAM_P).
(5) nodal cache (RAM_P).It is made of 360 SAM Stand Alone Memories, two-output impulse generator, all memories are all same
When read by identical address or storing data, 360 road check-nodes of corresponding storage update the intermediate data after (SPR), storage
Depth is in check matrix each by the sum of all rows weight of row block.
(6) check-node updates (SPR).It updates (SPR) module by 360 independent check-nodes to form, check-node is every
Secondary update reads multiple data by Ix_c control word from nodal cache (RAM_P), updates (SPR) Policy Updates by check-node
Afterwards, then by Ix_c control word it stores into nodal cache (RAM_P).
(7) Ix_c, Iy_c and It_c control word.Ix_c is that check-node updates (SPR) control word, is that check matrix is each
By the set of every every trade weight in row block, it is check matrix by every in column block that Iy_c, which is that variable node updates (VPR) control word,
The set of first column weight of block.It_c is interleaver control word, including interleaver between the column of the access address nodal cache (RAM_P)
Column cyclic shifts control word after reading 360 circuit-switched datas in intertexture control word and appropriate address.
2, process is decoded
Mainly there are five parts to form for the decoding process of decoder herein: initialization, decoding input, variable node are more
Newly, check-node updates and decoding exports.
(1) it initializes.Nodal cache (RAM_P) zero setting, check-node update (SPR) and are loaded into Ix_c control word, variable section
Point updates (VPR) and is loaded into Iy_c control word and interleaver (It) loading It_c control word.
(2) decoding input.When detection decoding input enables effective, counter is started counting.When previous systems code, counter
Chip selection signal divided by 360 remainders as 360 input-buffers (RAM_L), counter are rounded slow as each input divided by 360
Deposit (RAM_L) address signal；Below when check code, counter is used as each after deviating divided by Q remainder adding system code storage address
Input-buffer (RAM_L) address signal, counter are rounded divided by Q and are used as 360 input-buffer (RAM_L) chip selection signals.Entirely
After code word end of input, start to decode, wherein variable node updates and check-node update is carried out primary referred to as one in order
Secondary decoding iteration.Decoding continuous for high speed, needs to design the caching that ping-pang cache structure carries out decoding input data.
(3) variable node updates.It is input-buffer (RAM_L) storage depth that variable node, which updates the number that (VPR) is executed,
It is also the storage depth of Iy_c control word, the node number that variable node updates every time is determined by Iy_c control word.More new technological process
Are as follows: variable node update (VPR) module sends out variable node update times control word in order first, on the one hand reads corresponding defeated
Enter caching (RAM_L), on the other hand read Iy_c control word, obtains this number for updating variable node；Next reads out
The Iy_c control word come is sent into positive interleaver (It1), according to It_c control word numerical value, obtains the group node caching of this update
(RAM_P) address and corresponding Control of circular bit shift word are read；Then 360 circuit nodes caching (RAM_P) is read simultaneously by address
A class value and carry out cyclic shift, be finally sent into each variable node update module by road and be updated operation.It is updated
Data are sent into inverse interleaver (It2), after carrying out inverse cyclic shift according to It_c control word, read address according still further to It_c and are stored back to section
In point cache (RAM_P).
(4) check-node updates: after variable node updates (VPR), carrying out check-node update (SPR).Check-node is more
New number is Ix_c control word storage depth, and the node number that check-node updates every time is determined by Ix_c control word.Update stream
Journey are as follows: check-node update (SPR) module first sends out check-node update times control word in order, reads Ix_c control
Word obtains this number for updating check-node；Secondly the Ix_c control word read out is added up in sequence and is converted into one
Group node caches (RAM_P) and reads address；Then the class value that 360 circuit nodes caching (RAM_P) is read by address, finally presses road
It is sent into each check-node and updates the progress operation of (SPR) module.Reading of the updated data by weight of Iy_c control word
Location is stored back in nodal cache (RAM_P).
(5) decoding output.When the decoding iteration number that check-node updates (SPR) reaches maximum decoding iteration number,
Decoding output is executed, and nodal cache (RAM_P) is reset.More new technological process are as follows: update (VPR) process according to variable node and read
Nodal cache (RAM_P) and input-buffer (RAM_L) are sent into each decoding output module and carry out operation, and the output of 360 tunnel Bing An is translated
Code hard decision data.(VPR) process is updated in zero deposit nodal cache (RAM_P) according to variable node simultaneously, is realized and is reset.
3, interleaver control word designs
Setting k first as information bit (systematic code) length, m is check bit (check code) length, and n is code length, then n=m+k,
It defines Q=(n-k)/360.If IRA-LDPC code check matrix is H, then it is one dilute that check matrix left-half size, which is m × k,
Matrix is dredged, it is the unit by unit diagonal matrix and line down that right half part size, which is that m × m is a full rank lower triangular matrix,
Diagonal matrix, which is added, to be constituted.Check matrix is divided into 360 × n/360 block by every Q row (row block), every 360 column (column block), then verifies square
Battle array left-half submatrix is up and down ring shift right relationship between every piece.When interleaver control word designs, first to the check matrix right side
Half part exchange by column；Then to each column block, check bit volume is carried out according to the sequence being connected between block, block after antecedent
Code, each check bit coding are made of left and right two parts: left-hand component represents row number, and from 1 to 360, right part representative is every
The serial number of a check bit, serial number press the laminated structure of column block from left to right；First row block number data finally is read by row,
After carrying out ascending order arrangement to the right-hand component of number, i.e. completion interleaver control word design, wherein the data directory after sequence is
Interweave control word between column, and the left-hand component of number is column cyclic shifts control word.
As shown in Figures 2 to 4, in order to indicate convenient, the letter for meeting the IRA-LDPC code of DVB-S2 standard rule is devised
It is as follows to change check matrix H, wherein k=16, n=32, m=16, carries out 4 road parallel decodings, then Q=4.
Step 1: check matrix right half part exchange by column.
Step 2: carrying out check bit coding according to the sequence being connected between block, block after antecedent to each column block.
Step 3: reading first row block number data by row.
First row block number data of table F-1 and its index
Step 4: the right-hand component to number carries out ascending order arrangement.
Table F-2 interleaver control word
The first row data are the data directory after sequence in upper table, and interweave control word between as arranging, and the second row data are to compile
Number left-hand component, as column cyclic shifts control word.
Based on the quasi- circulation feature of DVB-S2 standard IRA-LDPC code, the results of intermediate calculations in parallel decoding only needs
Interweave between being arranged and 2-dimensional interleaving can be realized in column cyclic shifts, two dimension operation is reduced to two one-dimensional operations.
The preferred embodiment of the present invention has been described above in detail, still, during present invention is not limited to the embodiments described above
Detail a variety of equivalents can be carried out to technical solution of the present invention within the scope of the technical concept of the present invention, this
A little equivalents all belong to the scope of protection of the present invention.
Claims (3)
1. a kind of LDPC code parallel decoding FPGA based on DVB-S2 standard realizes framework characterized by comprising
Serioparallel exchange module carries out parallel memorizing control for inputting to serial decoding, and previous systems code is parallel respectively in order
Store into N number of input-buffer, behind check code serially store into N number of input-buffer respectively in order；
Input buffer module is made of, single-input single-output N number of SAM Stand Alone Memory, and storage decoding input, each memory is deposited
Storing up depth is code length divided by N；
Variable node update module is made of N number of independent variable node updates module, and variable node is updated every time from corresponding input
A data are read in caching, read multiple data by Iy_c control word from nodal cache, update rule more by variable node
After new, then store into nodal cache by Iy_c control word；
De-interleaver module is made of positive interleaver and inverse interleaver, interweaves between the storage address to realize nodal cache data
With the cyclic shifts of N number of data；
Positive interleaver realization nodal cache data are exported extremely by intertexture and column cyclic shifts between the column of It_c control word rule
Variable node updates；Inverse interleaver realize data after variable node updates by the column cyclic shifts of the inverse rule of It_c control word and
Interweave between column, and exports to nodal cache；
Nodal cache module is made of, two-output impulse generator N number of SAM Stand Alone Memory, and all memories all press identical address simultaneously
It reads or storing data, the intermediate data after the corresponding storage road N check-node update, storage depth is each in check matrix
By the sum of all rows weight of row block；
Check-node update module is made of N number of independent check-node update module, and check-node is updated every time from nodal cache
In by Ix_c control word read multiple data, store after check-node update Policy Updates, then by Ix_c control word to node
In caching；
Ix_c is that check-node updates control word, is check matrix each by the set of every every trade weight in row block, Iy_c is to become
Node updates control word is measured, is set of the check matrix by first column weight of every piece in column block, It_c is interleaver control word, packet
Include interleaver between on interweave the column of nodal cache access address control word and appropriate address read N circuit-switched data after column in follow
Ring shift control word, N are predetermined value.
2. the interpretation method based on framework described in claim 1, which comprises the steps of:
(1) it initializes, nodal cache zero setting, check-node, which updates, is loaded into Ix_c control word, variable node update loading Iy_c control
Word and interleaver processed are loaded into It_c control word；
(2) decoding input, when detection decoding input enables effective, counter is started counting；When previous systems code, counter divided by
Chip selection signal of the N remainder as N number of input-buffer, counter are rounded divided by N and are used as each input-buffer address signal；School below
When testing yard, counter is used as each input-buffer address signal after deviating divided by Q remainder adding system code storage address, and counter removes
It is rounded using Q as N number of input-buffer chip selection signal；After entire code word end of input, start to decode, wherein variable node update and
Check-node update is carried out in order is once known as a decoding iteration, and it is slow to need to design table tennis for decoding continuous for high speed
Deposit the caching that structure carries out decoding input data；
(3) variable node updates, and it is input-buffer storage depth and Iy_c control word that variable node, which updates the number executed,
Storage depth, the node number that variable node updates every time are determined by Iy_c control word；
More new technological process are as follows: variable node update module sends out variable node update times control word in order first, on the one hand reads
Corresponding input-buffer is taken, Iy_c control word is on the other hand read, obtains this number for updating variable node；Next reads out
The Iy_c control word come is sent into positive interleaver, and according to It_c control word numerical value, the group node caching for obtaining this update is read
Address and corresponding Control of circular bit shift word；Then it reads the slow class value of N circuit node simultaneously by address and carries out cyclic shift,
Each variable node update module finally, which is sent into, by road is updated operation；Updated data are sent into inverse interleaver, according to It_
After c control word carries out inverse cyclic shift, address is read according still further to It_c and is stored back in nodal cache；
(4) check-node updates: after variable node updates, carrying out check-node update, check-node update times are Ix_c control
Word storage depth processed, the node number that check-node updates every time are determined by Ix_c control word；
More new technological process are as follows: check-node update module sends out check-node update times control word in order first, reads Ix_c
Control word obtains this number for updating check-node；Secondly the Ix_c control word read out is added up in sequence and is converted
At a group node buffer read address；Then the class value that N circuit node caching is read by address, is finally sent into each verification by road
Node updates module carries out operation；Reading address of the updated data by weight of Iy_c control word is stored back in nodal cache；
(5) it is defeated to execute decoding when the decoding iteration number of check-node more reaches maximum decoding iteration number for decoding output
Out, and to nodal cache it resets；
More new technological process are as follows: read nodal cache and input-buffer according to variable node more new technological process, be sent into each decoding and export mould
Block carries out operation, and by the road N output decoding hard decision data；Simultaneously according to variable node more new technological process zero deposit nodal cache
In, it realizes and resets.
3. interpretation method according to claim 2, which is characterized in that the interleaver control word design is specific as follows:
Setting k first as information bit length, m is verification bit length, and n is code length, then n=m+k, Q=(n-k)/N is defined, if
IRA-LDPC code check matrix is H, then it is a sparse matrix, right half part size that check matrix left-half size, which is m × k,
It is a full rank lower triangular matrix for m × m, is to be added to constitute with the unit diagonal matrix of line down by unit diagonal matrix, high-ranking officers
It tests matrix and is divided into N × n/N block by every Q row, every N column, then check matrix left-half submatrix is ring shift right between every piece up and down
Relationship；
When interleaver control word designs, first check matrix right half part exchange by column；Then to each column block, according to
The sequence being connected between block, block after antecedent carries out check bit coding, and each check bit coding is made of left and right two parts: the left side
Part represents row number, and from 1 to N, the serial number of each check bit of right part representative, serial number is folded by the sequence of column block from left to right
Add；First row block number data finally is read by row, after carrying out ascending order arrangement to the right-hand component of number, that is, completes interleaver
Control word design, wherein the data directory after sequence is the control word that interweaves between arranging, the left-hand component of number is column cyclic shifts
Control word.
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| CN112272029A (en) * | 2020-10-22 | 2021-01-26 | 西安空间无线电技术研究所 | LDPC decoder implementation method based on DVB-S2 standard |
| CN112367085A (en) * | 2020-10-30 | 2021-02-12 | 中科院计算技术研究所南京移动通信与计算创新研究院 | Quasi-cyclic LDPC code decoding method, decoder, terminal and medium |
| CN113992212A (en) * | 2021-12-27 | 2022-01-28 | 成都星联芯通科技有限公司 | Data interleaving method and FPGA |
| CN117081608A (en) * | 2023-08-30 | 2023-11-17 | 白盒子(上海)微电子科技有限公司 | NR LDPC coding and decoding cyclic shift realizing device |
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| CN113992212A (en) * | 2021-12-27 | 2022-01-28 | 成都星联芯通科技有限公司 | Data interleaving method and FPGA |
| CN113992212B (en) * | 2021-12-27 | 2022-03-22 | 成都星联芯通科技有限公司 | Data interleaving method and FPGA |
| CN117081608A (en) * | 2023-08-30 | 2023-11-17 | 白盒子(上海)微电子科技有限公司 | NR LDPC coding and decoding cyclic shift realizing device |
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