CN106972864A - Quasi-cyclic LDPC encoder based on check matrix in deep space communication - Google Patents

Abstract

The invention provides the quasi-cyclic LDPC encoder based on check matrix in a kind of deep space communication, the encoder includes a kind of backward iterative circuit and 1 vector and the multiplier of high-density matrix.Vector and the multiplier of high-density matrix realize vector and the multiplying of high-density matrix, and backward iterative circuit realizes backward interative computation.Whole cataloged procedure is divided into 3 level production lines, and the first order and the third level use same type of backward iterative circuit, and the second level uses vector and the multiplier of high-density matrix.1/2 code check quasi-cyclic LDPC encoder has the advantages that simple in construction, cost is low, handling capacity is big in the deep space communication system that the present invention is provided.

Description

Quasi-cyclic LDPC encoder based on check matrix in deep space communication

Technical field

The present invention relates to field of channel coding, the QC- based on check matrix in more particularly to a kind of deep space communication system LDPC encoder.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The life of QC-LDPC codes All it is the array being made up of circular matrix into matrix G and check matrix H, the characteristics of with Circulant Block, therefore is referred to as QC-LDPC Code.The first trip of circular matrix is the result of footline ring shift right 1, and remaining each row is all the knot of its lastrow ring shift right 1 Really, therefore, circular matrix is characterized by its first trip completely.Generally, the first trip of circular matrix is referred to as its generator polynomial.

Deep space communication standard uses the QC-LDPC codes of system form, and its generator matrix G left-half is a unit square Battle array, right half part is by e × c b × b rank circular matrixes G_i,j(0≤i<e,e≤j<T, t=e+c) constitute array, following institute Show：

Wherein, I is b × b rank unit matrixs, and 0 is b × b rank full null matrix.G continuous b rows and b row are known respectively as block Row and block row.From formula (1), G has e blocks row and t blocks row.Deep space communication standard employs a kind of QC- of code check η=1/2 LDPC code, for the code, t=20, e=8, c=12, b=2048.

The existing solution of 1/2 code check QC-LDPC encoders is based on c I type shift LD in deep space communication standard Device adds the serial encoder of accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) circuit.By The serial encoder that c SRAA-I circuit is constituted, completes coding within e × b clock cycle.The program needs 2 × c × b Register, c × b two inputs and door and c × b two input XOR gate, in addition it is also necessary to e × c × b bits ROM storage circular matrixes Generator polynomial.The program has two shortcomings：One is to need a large amount of memories, causes circuit cost high；Two be serial input Information bit, coding rate is slow.

The content of the invention

The existing implementation of 1/2 code check QC-LDPC encoders has that cost is high, coding rate is slow in deep space communication system Shortcoming, for these technical problems, the invention provides a kind of QC-LDPC encoders based on check matrix.

As shown in Fig. 2 the QC-LDPC encoders based on check matrix are mainly made up of 2 parts in deep space communication system：Afterwards To iterative circuit and vector and the multiplier of high-density matrix.3 steps of cataloged procedure point are completed：1st step, uses backward iterative circuit Calculate vector p_yAnd x；2nd step, vector p is verified using vector and the multiplier calculating section of high-density matrix_x；3rd step, is used Backward iterative circuit calculating section verification vector p_y, so as to obtain verifying vectorial p=(p_x,p_y)。

The QC-LDPC coder structures that the present invention is provided are simple, can be under conditions of coding rate is significantly improved, and reduction is deposited Reservoir, so as to reduce cost, improves handling capacity.

Advantage on the present invention can be further understood with method by following detailed description and accompanying drawings.

Brief description of the drawings

Fig. 1 is the structural representation of near lower triangular check matrix after ranks are exchanged；

Fig. 2 is the QC-LDPC cataloged procedures based on check matrix；

Fig. 3 is backward iterative circuit；

Fig. 4 is the functional block diagram of ring shift left accumulator RLA circuits；

Fig. 5 is a kind of vector and the multiplier of high-density matrix being made up of u RLA circuit；

Fig. 6 summarizes the hardware resource and processing time needed for each coding step of encoder and whole cataloged procedure.

Embodiment

Presently preferred embodiments of the present invention is elaborated below in conjunction with the accompanying drawings, so that advantages and features of the invention can be more It is easy to be readily appreciated by one skilled in the art, apparent is clearly defined so as to be made to protection scope of the present invention.

The row weight and row heavy phase of circular matrix are same, are denoted as w.If w=0, then the circular matrix is full null matrix.If W=1, then the circular matrix is replaceable, referred to as permutation matrix, and it can be by some positions of unit matrix I ring shift rights Obtain.The check matrix H of QC-LDPC codes is by c × t b × b rank circular matrixes H_i,k(1≤i≤c, 1≤k≤t, t=e+c) The following array constituted：

Under normal circumstances, any circular matrix in check matrix H is either full null matrix (w=0) or is displacement square Battle array (w=1).Make circular matrix H_i,kFirst trip g_i,kIt is its generator polynomial.Because H is sparse, g_i,kOnly 1 ' 1 ', even without ' 1 '.

Corresponding H preceding e blocks row are information vector a, and corresponding rear c blocks row are verification vector p.Using b bits as one section, letter Breath vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e)；Verification vector p is divided into c sections, i.e. p=(p₁,p₂,…,p_c)。

Enter every trade to check matrix H to exchange and row swap operation, be converted near lower triangular shape H_ALT, such as Fig. 1 institutes Show.In Fig. 1, the unit of all matrixes is all b bits rather than 1 bit.A is by (c-u) × e b × b rank circular matrix structure Into B is made up of (c-u) × u b × b rank circular matrix, and T is made up of the individual b × b ranks circular matrixes of (c-u) × (c-u), C To be made up of u × e b × b rank circular matrix, D is made up of u × u b × b rank circular matrix, E be by u × (c-u) individual b × B ranks circular matrix is constituted.T is lower triangular matrix, and u reflects check matrix H_ALTWith the degree of closeness of lower triangular matrix.In Fig. 1 In, matrix A and C corresponding informances vector a, matrix B part verification vector p corresponding with D_x, matrix T and E then correspond to remaining school Test vectorial p_y.P=(p_x,p_y).Above-mentioned matrix and vector meet following relation：

p_x ^T=Φ (ET^-1Aa^T+Ca^T) (3)

p_y ^T=T^-1(Aa^T+Bp_x ^T) (4)

Wherein, Φ=(ET^-1B+D)^-1, subscript^TWith^-1Transposition is represented respectively and inverse.It is well known that circular matrix it is inverse, multiply Product and be still circular matrix.Therefore, Φ is also the array being made up of circular matrix.Although matrix E, T, B and D are sparse Matrix, but Φ is no longer sparse but highdensity under normal circumstances.

Make q^T=T^–1Aa^T, x^T=Eq^T+Ca^TAnd p_x ^T=Φ x^T(or p_x=x Φ^T).So, formula (3) and (4) can be changed into：

With

[A B T][a p_x p_y]^T=0 (6)

Because two matrixes in formula (5) and (6) are all lower triangular matrix as T, x and formula (6) in formula (5) In p_yThe calculation of backward iteration can all be used.

If p_x=0, then p_y ^T=T^–1Aa^T=q^T, and formula (5) is rewritable is

Wherein,

V=[a p_x p_y x] (8)

If that is, p_xIt is initialized as complete zero, then x can also be calculated by formula (7).Reset matrix X diagonal Upper all unit matrixs, can be obtained

Contrast (10) and Fig. 1 are visible, and H ' is fewer than H nonzero circle matrixes.

Deployable formula (7) is such as next group of equation：

Obviously, formula (6) is A part for formula (11), therefore, formula (7) also can be used to calculate p_y。

From the above discussion, a kind of QC-LDPC cataloged procedures based on three class pipeline can be provided, as shown in Figure 2.Φ is related to And vector and the multiplication of high-density matrix, and X is related to backward iterative calculation.The second level uses vector and the multiplication of high-density matrix Device realizes p_x=x Φ^T.Because X is lower triangular matrix, same type of backward iteration electricity can be used in the first order and the third level Road calculates x and p respectively_y.In the first order, p_xIt is initialized to complete zero, p_yActually q；In the third level, p_xAnd p_yIt is respective reality Actual value, and x need not be calculated.

Make v=(v₁,v₂,…,v_t+u), wherein, each section of v_kAll it is v continuous b bits composition, 1≤k≤t+u.By formula (7) understood with Fig. 1, [p_yX]=(v_t–c+u+1,v_t–c+u+2,…,v_t+u).With v_t–c+u+i=v_i′Exemplified by, wherein, i '=t-c+u+i, 1≤i≤c, t-c+u+1≤i '≤t+u.For given QC-LDPC codes, i ' changes synchronous with i.Because lower triangular matrix X is Derived from from H, so H_i,i′=I, and work as k>During i ', H_i,k=0.From formula (7), X i-th piece of row and v^TProduct meet

Nonzero circle matrix H_i,kRing shift right digit relative to b × b rank unit matrixs is s_i,k, wherein, 0≤s_i,k<B, Assuming that have N number of nonzero circle matrix in H ' i-th piece of row, their block row number be respectively k1, k2 ..., kN, and 1≤k1<k2 <…<kN<i′.So, formula (12) is changed into

In other words

Wherein, subscript^rs(s)With^ls(s)Represent respectively to matrix (or vector) ring shift right or ring shift left s.

If v_i′Calculated successively by formula (14) according to i ' ascending orders, then p_yIt can be calculated paragraph by paragraph with x.The backward iteration mistake Journey circuit can be realized as shown in Figure 3.The backward iterative circuit is by 1 barrel shifter, 3 accumulators, 2 delayers, 2 Individual comparator, 1 multiplexer, 1 piece of read-only storage (ROM) and 1 piece of random access storage device (RAM) composition.In figure 3, bucket Shape shift unit uses bipartite structure and streamline mechanism, and inherent delay is τ clock cycle, wherein, τ={ log₂B } represent that τ is Not less than log₂B smallest positive integral.Barrel shifter is to some positions of b bit number ring shift lefts, and accumulator 1 is to barrel shift The output of device is added up.As shown in figure 3, all nonzero circle matrixes, i.e. H in H '_1,k1、H_1,k2、…、H_1,kN、H_2,k1、 H_2,k2、…、H_i,kN、H_i+1,k1、…、H_c,kNBlock row number and carry digit block-by-block row be stored in ROM.Generally, H_i,kNSubscript KN is more than H_i+1,k1Subscript k1.Therefore, when the source address k changes that ROM is exported are small, destination address i ' and block line number i in formula (14) Should Jia 1 simultaneously.At the same time, the content of accumulator 1, i.e. destination operand v_i′It is written into RAM, is then cleared, to count Calculate next destination operand.Delayer 1 is delayed 1 clock cycle, and it coordinates with comparator 1 judges whether k diminishes.Delayer 2 τ clock cycle of delay were to compensate for the inherent delay of barrel shifter.Accumulator 3 produces destination address i '.RAM according to The source address k output source operands v of ROM outputs_k, destination operand v_i′Write destination address i '.

Theoretically, in formula (14), source address k is necessarily less than destination address i '.In fact, because delayer 2 prolongs When τ clock cycle, it is possible that k >=i '.When this happens, the v of RAM outputs_kIt is invalid, because v_i′ Do not calculate also, let alone v_k.As k >=i ', ROM pause output new datas, and the number of feeding barrel shifter is not v_k But 0.According to the output of comparator 2, accumulator 2 produces ROM address, and multiplexer is from v_kWith 0 in alternative give barrel-shaped shifting Position device.

In the third level, if B preceding R blocks row are complete zero, then p_yPreceding R sections without calculating because these sections The p that exactly equal to first order is calculated_yPreceding R sections.Again because in the third level x need not be calculated, thus the third level without using H ' preceding R blocks row and rear u blocks row.Assuming that in H ' and its middle (c-R-u) block row has α and β nonzero circle matrix respectively. Due to there is path delay, x and p is calculated in first and the third level_yThe total time lower limit spent is (τ of alpha+beta+2) the individual clock cycle. For 1/2 code check QC-LDPC codes in deep space communication system, α and β are 32 and 28 respectively.

If only considering the resource consumption of the chief component such as ROM, RAM, barrel shifter and accumulator 1 in Fig. 3, that The backward iterative circuit needs τ b triggers, b two input XOR gates, the RAM and ({ log of (t+u) b bits₂t}+ {log₂B }) ROM of β bits.

Vector p is calculated using backward iterative circuit_yAnd the step of x is as follows：

1st step, resets accumulator 1 and accumulator 2, and initialization accumulator 3 is i '=t-c+u+1；

2nd step, the address that ROM is produced according to accumulator 2 exports source address k and carry digit s_i,k；

3rd step, RAM exports source operand v according to source address k_k, comparator 2 judge source address k whether be less than destination address I ', if k<I ', then the output of comparator 21, otherwise, and the output of comparator 20, delayer 1 coordinates with comparator 1 judges whether k diminishes, If diminishing, the output of comparator 11, otherwise, the output of comparator 10, the comparator 1 of 3 pairs of τ clock cycle of delay of accumulator are exported Added up, produce destination address i '；

4th step, according to the output of comparator 2, accumulator 2 produces ROM addresses, and multiplexer is from v_kWith 0 in alternative give Barrel shifter, if the output of comparator 2 is 1, accumulator 2 is incremented by ROM addresses, and multiplexer is v_kGive barrel shifter, Otherwise, the holding ROM of accumulator 2 addresses are constant, and multiplexer gives barrel shifter 0；

5th step, output ring shift left s of the barrel shifter to multiplexer_i,kPosition, output of the accumulator 1 to barrel shifter Added up, when delayer 2 is output as 1, the content of accumulator 1 is destination operand v_i′, v_i′It is written into RAM mesh Address i ' in, at the same time, accumulator 1 is cleared, to calculate next destination operand；

6th step, repeat step 2~5, until [p_yX]=(v_t–c+u+1,v_t–c+u+2,…,v_t+u) be stored in paragraph by paragraph in RAM.

By formula (7), Fig. 1 and v=(v₁,v₂,…,v_t+u) understand, p_x=(v_t–c+1,v_t–c+2,…,v_t–c+u) and x=(v_t+1, v_t+2,…,v_t+u)。p_x ^T=Φ x^TIt is equivalent to p_x=x Φ^T.Make x=(x₁,x₂,…,x_u×b).Define u bit vectors s_n=(x_n, x_n+b,…,x_n+(u-1)×b), wherein 1≤n≤b.Make Φ_j(1≤j≤u) is by Φ^TJth block row in the generation of all circular matrixes U × b rank matrixes that multinomial is constituted.Then have

v_t-c+j=(... ((0+s₁Φ_j)^ls(1)+s₂Φ_j)^ls(1)+…+s_bΦ_j)^ls(1) (15)

A kind of ring shift left accumulator (Rotate-Left-Accumulator, RLA) circuit can obtain by formula (15), such as Shown in Fig. 4.The index of look-up table is u bit vectors s_n, look-up table L_jIt is previously stored variable u bit vectors and fixed Φ_j's Be possible to product, therefore need 2^uThe read-only storage (Read-Only Memory, ROM) of b bits.B bit registers R₁, R₂,…,R_uIt is respectively used to buffer the array section v of vector x_t+1,v_t+2,…,v_t+u, b bit registers R_u+jFor storing p_xVerification Section v_t–c+j.1 RLA circuit counting vector v_t–c+jNeed b clock cycle.

For deep space communication system, p is calculated simultaneously using u=4 RLA circuit_x=(v_t–c+1,v_t–c+2,…,v_t–c+u) be A kind of reasonable plan, vector and the multiplier of high-density matrix as shown in Figure 5.Vector and the multiplier of high-density matrix are by u Individual look-up table L₁,L₂,…,L_u, 2u b bit registers R_2,1,R_2,2,…,R_2,2uWith the u input XOR gate X of b positions two_2,1, X_2,2,…,X_2,uComposition.Look-up table L₁,L₂,…,L_uVariable u bit vectors and fixed matrix Φ are stored respectively₁,Φ₂,…, Φ_uBe possible to product, register R_2,1,R_2,2,…,R_2,uIt is respectively used to buffer the array section v of vector x_t+1,v_t+2,…, v_t+u, register R_2,u+1,R_2,u+2,…,R_2,2uIt is respectively used to store p_xVerification section v_t–c+1,v_t–c+2,…,v_t–c+u.U RLA electricity Road need to use ub two input XOR gate, 2^uThe ROM of ub bits and 2ub register.U RLA circuit countings vector p_xNeed b The individual clock cycle.Vector p is calculated using vector and the multiplier of high-density matrix_xThe step of it is as follows：

1st step, resets register R_2,u+1,R_2,u+2,…,R_2,2u, input vector section v_t+1,v_t+2,…,v_t+u, they are distinguished It is stored in register R_2,1,R_2,2,…,R_2,uIn；

2nd step, register R_2,1,R_2,2,…,R_2,uRing shift left 1 time, XOR gate X simultaneously_2,1,X_2,2,…,X_2,uIt is right respectively Look-up table L₁,L₂,…,L_uOutput and register R_2,u+1,R_2,u+2,…,R_2,2uContent carry out XOR, XOR result circulated Move to left and be stored back to register R after 1 time respectively_2,u+1,R_2,u+2,…,R_2,2u；

3rd step, repeats the 2nd step b-1 times, after the completion of, register R_2,u+1,R_2,u+2,…,R_2,2uThe content of storage is school respectively Test a section v_t–c+1,v_t–c+2,…,v_t–c+u, they constitute part verification vector p_x。

The invention provides a kind of QC-LDPC coding methods based on check matrix, it is adaptable in deep space communication system 1/2 code check QC-LDPC codes, its coding step is described as follows：

1st step, vector p is calculated using backward iterative circuit_yAnd x；

2nd step, vector p is verified using vector and the multiplier calculating section of high-density matrix_x；

3rd step, vector p is verified using backward iterative circuit calculating section_y, so as to obtain verifying vectorial p=(p_x,p_y)。

When Fig. 6 summarizes hardware resource consumption and the processing needed for each coding step of encoder and whole cataloged procedure Between.

It is not difficult to find out from Fig. 6, when streamline is full of, whole cataloged procedure about needs max (α+τ, b, β+τ)=2048 altogether Clock cycle, much smaller than the e × b=16404 clock cycle needed for the serial encoding method based on c SRAA-I circuit.

The existing solution of 1/2 code check QC-LDPC encoders needs e × c × b=196608 ratios in deep space communication standard Special ROM, and the present invention needs ({ log₂t}+{log₂b})(α+β)+2^uUb=131584 bits ROM.

As fully visible, compared with traditional serial SRAA methods, it is excellent that the present invention has that coding rate is fast, memory consumption is few etc. Point.

One of the foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, Any those skilled in the art disclosed herein technical scope in, the change that can be expected without creative work Change or replace, should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with claims The protection domain limited is defined.

Claims (4)

1. the quasi-cyclic LDPC encoder based on check matrix in a kind of deep space communication, the verification of 1/2 code check quasi-cyclic LDPC code Matrix H is the array being made up of c × t b × b rank circular matrix, wherein, c=12, t=20, b=2048, e=t-c=8, school Test matrix H and near lower triangular shape be transformed into by ranks exchange, 6 submatrixs can be divided into,A be by (c-u) × e b × b ranks circular matrix is constituted, and B is made up of (c-u) × u b × b rank circular matrix, and lower triangular matrix T is It is made up of the individual b × b ranks circular matrixes of (c-u) × (c-u), C is made up of u × e b × b rank circular matrix, and D is by u × u b × b ranks circular matrix is constituted, and E is made up of the individual b × b ranks circular matrixes of u × (c-u), wherein, u=4, Φ=(ET^-1B+D)^-1 It is to be made up of u × u b × b rank circular matrix, Φ_jIt is by Φ^TJth block row in all circular matrix generator polynomials constitute U × b rank matrixes, wherein, subscript^TWith^-1Transposition and inverse, 1≤j≤u are represented respectively,Fewer than H non-zeros Circular matrix, is by c × t b × b rank circular matrixes H_i,kConstitute, wherein, I is unit matrix, and 0 is full null matrix, 1≤i≤ C, 1≤k≤t, i '=t-c+u+i, t-c+u+1≤i '≤t+u, nonzero circle matrix H_i,kRelative to b × b rank unit matrixs Ring shift right digit is s_i,k, wherein, 0≤s_i,k<B, A and C corresponding informance vector a, matrix B part verification vector corresponding with D p_x, matrix T and E then correspond to remaining verification vector p_y, verification vector p=(p_x,p_y), Xv^T=0, wherein,V=[a p_x p_yX], using b bits as one section, vector v is divided into t+u sections, i.e. v=(v₁,v₂,…, v_t+u), then p_x=(v_t–c+1,v_t–c+2,…,v_t–c+u), p_y=(v_t–c+u+1,v_t–c+u+2,…,v_t+u), x=(v_t+1,v_t+2,…, v_t+u), it is characterised in that the encoder is included with lower component：

Backward iterative circuit, by 1 barrel shifter, 3 accumulators, 2 delayers, 2 comparators, 1 multiplexer, 1 piece All nonzero circle matrixes, i.e. H in ROM and 1 block RAM composition, H '_1,k1、H_1,k2、…、H_1,kN、H_2,k1、H_2,k2、…、H_c,kNBlock It is stored in ROM, for calculating vectorial p row number and carry digit block-by-block row_yAnd x, wherein, 1≤k1<k2<…<kN<i′；

Vector and the multiplier of high-density matrix, by u look-up table L₁,L₂,…,L_u, 2u b bit registers R_2,1,R_2,2,…, R_2,2uWith the u input XOR gate X of b positions two_2,1,X_2,2,…,X_2,uComposition, for calculating section verification vector p_x, look-up table L₁, L₂,…,L_uVariable u bit vectors and fixed matrix Φ are stored respectively₁,Φ₂,…,Φ_uBe possible to product.

2. the quasi-cyclic LDPC encoder based on check matrix, its feature in a kind of deep space communication according to claim 1 It is, the backward iterative circuit calculates vector p_yAnd the step of x is as follows：

1st step, resets accumulator 1 and accumulator 2, and initialization accumulator 3 is i '=t-c+u+1,；

2nd step, the address that ROM is produced according to accumulator 2 exports source address k and carry digit s_i,k；

3rd step, RAM exports source operand v according to source address k_k, comparator 2 judge source address k whether be less than destination address i ', if k<I ', then the output of comparator 21, otherwise, and the output of comparator 20, delayer 1 coordinates with comparator 1 judges whether k diminishes, if becoming Small, then the output of comparator 11, otherwise, the output of comparator 10, the output of comparator 1 of 3 pairs of τ clock cycle of delay of accumulator are carried out It is cumulative, destination address i ' is produced, wherein, τ={ log₂B } represent that τ is no less than log₂B smallest positive integral, barrel shifter is consolidated It is τ clock cycle to have delay；

4th step, according to the output of comparator 2, accumulator 2 produces ROM addresses, and multiplexer is from v_kWith 0 in alternative give barrel-shaped shifting Position device, if the output of comparator 2 is 1, accumulator 2 is incremented by ROM addresses, and multiplexer is v_kBarrel shifter is given, otherwise, is tired out Plus the holding ROM of device 2 addresses are constant, multiplexer gives barrel shifter 0；

5th step, output ring shift left s of the barrel shifter to multiplexer_i,kPosition, output of the accumulator 1 to barrel shifter is carried out Cumulative, when delayer 2 is output as 1, the content of accumulator 1 is destination operand v_i′, v_i′It is written into RAM destination In the i ' of location, at the same time, accumulator 1 is cleared, to calculate next destination operand；

6th step, repeat step 2~5, until [p_yX]=(v_t–c+u+1,v_t–c+u+2,…,v_t+u) be stored in paragraph by paragraph in RAM.

3. the quasi-cyclic LDPC encoder based on check matrix, its feature in a kind of deep space communication according to claim 1 It is, the vector and the multiplier of high-density matrix calculate vector p_xThe step of it is as follows：

1st step, resets register R_2,u+1,R_2,u+2,…,R_2,2u, input vector section v_t+1,v_t+2,…,v_t+u, they are stored in respectively Register R_2,1,R_2,2,…,R_2,uIn；

2nd step, register R_2,1,R_2,2,…,R_2,uRing shift left 1 time, XOR gate X simultaneously_2,1,X_2,2,…,X_2,uRespectively to searching Table L₁,L₂,…,L_uOutput and register R_2,u+1,R_2,u+2,…,R_2,2uContent carry out XOR, XOR result is by ring shift left 1 Register R is stored back to after secondary respectively_2,u+1,R_2,u+2,…,R_2,2u；

3rd step, repeats the 2nd step b-1 times, after the completion of, register R_2,u+1,R_2,u+2,…,R_2,2uThe content of storage is verification section respectively v_t–c+1,v_t–c+2,…,v_t–c+u, they constitute part verification vector p_x。

4. the quasi-cyclic LDPC coding method based on check matrix in a kind of deep space communication, the school of 1/2 code check quasi-cyclic LDPC code It is the array being made up of c × t b × b rank circular matrix to test matrix H, wherein, c=12, t=20, b=2048, e=t-c=8, Check matrix H is exchanged by ranks and is transformed near lower triangular shape, can be divided into 6 submatrixs,A is It is made up of (c-u) × e b × b rank circular matrix, B is made up of (c-u) × u b × b rank circular matrix, lower triangular matrix T It is to be made up of the individual b × b ranks circular matrixes of (c-u) × (c-u), C is made up of u × e b × b rank circular matrix, and D is by u × u Individual b × b ranks circular matrix is constituted, and E is made up of the individual b × b ranks circular matrixes of u × (c-u), wherein, u=4, Φ=(ET^-1B+ D)^-1It is to be made up of u × u b × b rank circular matrix, Φ_jIt is by Φ^TJth block row in all circular matrix generator polynomial structures Into u × b rank matrixes, wherein, subscript^TWith^-1Transposition and inverse, 1≤j≤u are represented respectively,It is fewer than H Nonzero circle matrix, is by c × t b × b rank circular matrixes H_i,kConstitute, wherein, I is unit matrix, and 0 is full null matrix, 1≤ I≤c, 1≤k≤t, i '=t-c+u+i, t-c+u+1≤i '≤t+u, nonzero circle matrix H_i,kRelative to b × b rank unit matrixs Ring shift right digit be s_i,k, wherein, 0≤s_i,k<B, A and C corresponding informance vector a, a matrix B part corresponding with D verify to Measure p_x, matrix T and E then correspond to remaining verification vector p_y, verification vector p=(p_x,p_y), Xv^T=0, wherein,V=[a p_x p_yX], using b bits as one section, vector v is divided into t+u sections, i.e. v=(v₁,v₂,…, v_t+u), then p_x=(v_t–c+1,v_t–c+2,…,v_t–c+u), p_y=(v_t–c+u+1,v_t–c+u+2,…,v_t+u), x=(v_t+1,v_t+2,…, v_t+u), it is characterised in that the coding method comprises the following steps：

1st step, vector p is calculated using backward iterative circuit_yAnd x；

2nd step, vector p is verified using vector and the multiplier calculating section of high-density matrix_x；

3rd step, vector p is verified using backward iterative circuit calculating section_y, so as to obtain verifying vectorial p=(p_x,p_y)。