CN102857238A - LDPC (Low Density Parity Check) encoder and encoding method based on summation array in deep space communication - Google Patents

Abstract

The invention relates to a scheme of solving parallel encoding of nine QC-LDPC (Quasi-Cyclic-Low Density Parity Check) codes in a CCSDS (Consultative Committee for Space Data Systems) deep space communication system, which is characterized in that a parallel encoder of the QC-LDPC codes in the system is mainly composed of four parts of a register, a summation array, a selecting expander and a b-digit 2-input exclusive-or gate. The QC-LDPC parallel encoder provided by the invention is compatible with a multi-code rate, and resource requirements can be effectively reduced in the condition that the encoding speed is kept unchanged. The QC-LDPC parallel encoder has the advantages of simple control, less resource consumption, little power consumption, low cost and the like.

Description

Based on LDPC encoder and coding method in the deep space communication of sum array

Technical field

The present invention relates to the deep space data communication field, particularly the Parallel Implementation method of QC-LDPC code coder in a kind of CCSDS deep space communication system.

Background technology

Because the various distortions that exist in transmission channel and noise can produce transmitted signal and disturb, the situation that digital signal produces error code can appear in receiving terminal inevitably.In order to reduce the error rate, need to adopt channel coding technology.

Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with its excellent properties that approaches the Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.

The SRAA method is to utilize generator matrix G to encode.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G _{I, j}(1≤i≤a, the array that 1≤j≤t) consists of, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with the verification vector is high-density matrix.Suppose that a is not prime number, can be broken down into that a=ux(u≤x), wherein, u is not equal to 1, x and is not equal to a.So, the parallel SRAA method in u road is finished first encoding needs bx+t clock cycle, needs (uc+t) b register, ucb two input and door and ucb two input XOR gate.In addition, also need the first trip of acb bit ROM storage circular matrix.

CCSDS deep space communication system recommendation 9 kinds of QC-LDPC codes, wherein code check η is divided into 1/2,2/3 and 4/5 3 kind, square formation exponent number b is divided into 32,64,128,256,512,1024 and 2,048 seven kinds.As shown in Figure 1, η and b have 9 kinds of effectively combinations (η, b): (4/5,32), (2/3,64), (1/2,128), (4/5,128), (2/3,256), (1/2,512), (4/5,512), (2/3,1024) and (1/2,2048), corresponding 9 kinds of QC-LDPC codes.For all QC-LDPC codes, c=12 is all arranged, the greatest common divisor of all a is u=8.Fig. 2 has provided parameter a, t and the x under the different code check η.

The existing solution of QC-LDPC high spped coding is to adopt the parallel SRAA method in u=8 road in the CCSDS deep space communication system, and 9 kinds of required scramble times of QC-LDPC code are respectively 172,156,148,556,540,532,2092,2076 and 2068 clock cycle.Logical resource needs 237568 registers, 196608 two inputs and door and 196608 two input XOR gate, and this is to be determined by parameter corresponding to (η, b)=(1/2,2048).In addition, 9 kinds of QC-LDPC codes need 774,144 bit ROM to store the first trip of circular matrix altogether.When adopting hardware to realize, need more memory and register, will certainly cause equipment cost high, power consumption is large.

Summary of the invention

The large shortcoming of resources requirement that exists in the existing implementation for CCSDS deep space communication system multiple QC-LDPC code high spped coding, the invention provides a kind of parallel encoding method based on sum array, can keep reducing resource requirement under the constant prerequisite of coding rate.

As shown in Figure 3, the parallel encoder of multiple QC-LDPC code mainly is comprised of 4 parts in the CCSDS deep space communication system: register, sum array, selection expander and b position two input XOR gate.Whole cataloged procedure divided for 4 steps finished: in the 1st step, input message vector s is saved to register R ₁～R _a, zero clearing register R _A+1～R _t, and for selecting expander M _l(code check η and square formation exponent number b that the configuration of 1≤l≤c) is appropriate; The 2nd step, register R ₁～R _aSerial moves to left 1 time, is the parallel input vector (s of sum array _{1, k}, s _{2, k}..., s _{U, k}) (1≤k≤bx), all select the control end input ρ of expanders=[(k-1)/b]+1(symbol [(k-1)/b] expression to be not more than the maximum integer of (k-1)/b), all are selected expander to select respectively a part from the output of sum array and are extended to b, jointly consist of vector (s _{1, k}, s _{2, k}..., s _{U, k}) with the product of sub-block first trip matrix F ρ corresponding to effective combination (η, b), XOR gate A are inputted in b position two _l(1≤l≤c) is with l section b bit and the register R of product _A+lThe results added that the serial ring shift left is 1 time, and deposit back register R _A+lIn the 3rd step, take 1 for step-length increases progressively the value that changes k, repeat the 2nd and go on foot bx time; The 4th step, parallel output code word v=(s, p).

The compatible multi code Rate of Chinese character of QC-LDPC parallel encoder provided by the invention can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thereby reach the purpose that reduces hardware cost and power consumption.

Can be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.

Description of drawings

Fig. 1 has provided effective combination (η, b) of code check η and square formation exponent number b;

Fig. 2 has provided parameter a, t and the x under the different code check η;

Fig. 3 is the parallel encoder overall structure of compatible 9 kinds of QC-LDPC codes in the CCSDS deep space communication system;

Fig. 4 is the formation schematic diagram of sum array;

Fig. 5 has provided the quantity of various many input XOR gate;

Fig. 6 has compared the parallel SRAA method in traditional u road and resource consumption of the present invention.

Embodiment

The invention will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.

The QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H all are the arrays that is made of circular matrix, has segmentation circulation characteristics, therefore be called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of one of lastrow (first trip is footline) ring shift right; From the angle of row, each row of circular matrix all are that previous column (first is terminal column) circulation moves down one result.The set that the row vector of circular matrix consists of is identical with the set of column vector formation, therefore, circular matrix fully can by it first trip or first characterize.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G _{I, j}(1≤i≤a, the array that 1≤j≤t) consists of:

G(or H) the capable and b of continuous b row be called as respectively the capable and piece row of piece.Suppose g _{I, j}(1≤i≤a, a+1≤j≤t) is circular matrix G _{I, j}First trip, can define in the following manner so a * bc rank piece first trip matrix F:

F is that the first trip by all circular matrixes in the c piece row behind the generator matrix G consists of, and can be considered to be comprised of bc a dimensional vector.Suppose that a is not prime number, can be broken down into that a=ux(u≤x), wherein, u is not equal to 1, x and is not equal to a.So, (1≤ρ≤x) row has consisted of a u * bc rank matrix to the u (ρ-1) of piece first trip matrix F+1 ~ u ρ, is referred to as sub-block first trip matrix, is denoted as F _ρF _ρCan be considered and consisted of by bc u dimensional vector.

For CCSDS deep space communication system, the corresponding code word v=(s, p) of generator matrix G, that the front a piece row of G are corresponding is information vector s, that rear c piece row are corresponding is verification vector p.Take the b bit as one section, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a); Verification vector p is divided into the c section, i.e. p=(p ₁, p ₂..., p _c).For the segment information of the i(1≤i≤a) vector s _i, s is arranged _i=(s _{I, 1}, s _{I, 2}..., s _{I, b}).As shown in Figure 1, CCSDS deep space communication system has adopted 9 kinds of QC-LDPC codes, and wherein code check η is divided into 1/2,2/3 and 4/5 3 kind, and square formation exponent number b is divided into 32,64,128,256,512,1024 and 2,048 seven kinds.η and b have 9 kinds of effectively combinations (η, b): (4/5,32), (2/3,64), (1/2,128), (4/5,128), (2/3,256), (1/2,512), (4/5,512), (2/3,1024) and (1/2,2048).For all QC-LDPC codes, c=12 is all arranged, the greatest common divisor of all a is u=8.Fig. 2 has provided parameter a, t and the x under the different code check η.

Characteristics by formula (1), (2) and circular matrix, Fig. 3 has provided the parallel encoder that is applicable to 9 kinds of QC-LDPC codes in the CCSDS deep space communication system, and it mainly is comprised of register, sum array, selection expander and b position four kinds of functional modules of two input XOR gate.

Register R ₁～R _aBe used for cache information vector s=(s ₁, s ₂..., s _a), register R _A+1～R _tBe used for calculating and storage verification vector p=(p ₁, p ₂..., p _c).

Sum array is to the u position information bit s of parallel input _{1, k}, s _{2, k}..., s _{U, k}(1≤k≤bx) sue for peace particularly, is therefrom to choose the individual different element of m(1≤m≤u) to carry out mould 2 and add.By permutation and combination knowledge as can be known, exhaustively obtain 2 ^u-1=255 different summation expression formula.255 summation expression formulas can be realized with the XOR gate of input more than 255.The input number scope of many input XOR gate is 1 ~ 8, and when only having an input, single input XOR gate is actually direct-connected line.To sum up, sum array has u=8 input and 255 outputs, and its inside is comprised of the XOR gate of input more than 255, as shown in Figure 4.Fig. 5 has provided the quantity of various many input XOR gate, and they are equivalent to 769 two input XOR gate altogether.

Select expander M _l(1≤l≤c) is controlled by code check η, square formation exponent number b and sub-block first trip matrix F _ρSubscript ρ (1≤ρ≤x).ρ and vector (s _{1, k}, s _{2, k}..., s _{U, k}) (pass of 1≤k≤bx) is that ρ=[(k-1)/b]+1(symbol [(k-1)/b] expression is not more than the maximum integer of (k-1)/b).Select expander M _lOn the basis of sum array operation result, finish vector (s according to code check η and square formation exponent number b _{1, k}, s _{2, k}..., s _{U, k}) (1≤k≤bx) and sub-block first trip matrix F _ρ(the parallel multiplication of 1≤ρ≤x).Select expander M _lFrom the output of sum array, select a part and be extended to b, to consist of vector (s _{1, k}, s _{2, k}..., s _{U, k}) and sub-block first trip matrix F _ρThe l section b bit of product, selection mode depend on the sub-block first trip matrix F that effective combination (η, b) is corresponding fully _ρBc column vector.

B position two input XOR gate A _l(1≤l≤c) with vector (s _{1, k}, s _{2, k}..., s _{U, k}) (1≤k≤bx) and sub-block first trip matrix F _ρThe l section b bit of product is added to register R _A+lIn.

The invention provides a kind of parallel encoding method of variable bit rate QC-LDPC code, in conjunction with the parallel encoder (as shown in Figure 3) of multiple QC-LDPC code in the CCSDS deep space communication system, its coding step is described below:

In the 1st step, input message vector s is saved to register R ₁～R _a, zero clearing register R _A+1～R _t, and for selecting expander M _l(code check η and square formation exponent number b that the configuration of 1≤l≤c) is appropriate;

The 2nd step, register R ₁～R _aSerial moves to left 1 time, is the parallel input vector (s of sum array _{1, k}, s _{2, k}..., s _{U, k}) (1≤k≤bx), the control end input ρ of all selection expanders=[(k-1)/b]+1, all selection expanders are selected respectively a part and are extended to b individual from the output of sum array, common formation vector (s _{1, k}, s _{2, k}..., s _{U, k}) sub-block first trip matrix F corresponding with effective combination (η, b) _ρProduct, b position two input XOR gate A _l(1≤l≤c) is with l section b bit and the register R of product _A+lThe results added that the serial ring shift left is 1 time, and deposit back register R _A+l

The 3rd step take 1 for step-length increases progressively the value that changes k, repeated the 2nd and goes on foot bx time, after finishing, and register R ₁～R _aThat store is information vector s=(s ₁, s ₂..., s _a), register R _A+1～R _tThat store is verification vector p=(p ₁, p ₂..., p _c);

The 4th step, parallel output code word v=(s, p).

Be not difficult to find out from above step, whole cataloged procedure needs bx+t clock cycle altogether, and this and the parallel SRAA method in traditional u road are identical.

Fig. 6 has compared the parallel SRAA method in traditional u road and resource consumption of the present invention.Note, will select the basic selected cell of expander to be considered as one two input and door here.Can know from Fig. 6 and to see, compare with parallel SRAA method, advantage of the present invention is to need not memory, used less register, XOR gate and with door, the amount of expending is respectively 17%, 13% and 13% of parallel SRAA method.

As fully visible, compare with the parallel SRAA method in traditional u road, the present invention has kept coding rate, has that control is simple, resource consumption is few, power consumption is little, low cost and other advantages.

Above-described embodiment is more preferably embodiment of the present invention, and the common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacement all should be included in protection scope of the present invention.

Claims (5)

1. parallel encoder that is suitable for 9 kinds of QC-LDPC codes that CCSDS deep space communication system adopts, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G _{I, j}The array that consists of, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, 3 kinds of different code check η are respectively 1/2,2/3,4/5,7 kinds of square formation exponent number b are respectively 32,64,128,256,512,1024,2048,9 kinds are effectively made up (η, b) is respectively (4/5,32), (2/3,64), (1/2,128), (4/5,128), (2/3,256), (1/2,512), (4/5,512), (2/3,1024) and (1/2,2048), for these 9 kinds of QC-LDPC codes, c=12 is all arranged, and 3 kinds of parameter a corresponding to different code checks are respectively 8,16,32,3 kinds of parametric t corresponding to different code checks are respectively 20,28,44, the greatest common divisor of 3 kinds of a is u=8, a=ux, 3 kinds of parameter x corresponding to different code checks are respectively 1,2,4, the corresponding code word v=of generator matrix G (s, p), that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p, take the b bit as one section, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), i segment information vector s _i=(s _{I, 1}, s _{I, 2}..., s _{I, b}), verification vector p is divided into the c section, i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described encoder comprises following parts:

Register R ₁～R _t, register R ₁～R _aBe used for cache information vector s=(s ₁, s ₂..., s _a), register R _A+1～R _tBe used for calculating and storage verification vector p=(p ₁, p ₂..., p _c);

Sum array is to the u position information bit s of parallel input _{1, k}, s _{2, k}..., s _{U, k}Make up summation, wherein, 1≤k≤bx;

Select expander M ₁～M _c, on the basis of sum array operation result, finish vector (s according to code check η and square formation exponent number b _{1, k}, s _{2, k}..., s _{U, k}) and sub-block first trip matrix F _ρParallel multiplication, wherein, 1≤ρ≤x, ρ=[(k-1)/b]+1, symbol [(k-1)/b] expression is not more than the maximum integer of (k-1)/b;

B position two input XOR gate A ₁～A _c, A _lWith vector (s _{1, k}, s _{2, k}..., s _{U, k}) and sub-block first trip matrix F _ρThe l section b bit of product is added to register R _A+lIn, wherein, 1≤l≤c.

2. parallel encoder as claimed in claim 1 is characterized in that, described sub-block first trip matrix F _ρBy the u of the u (ρ-1) of piece first trip matrix F+capable formation of 1 ~ u ρ * bc rank matrix, and piece first trip matrix F to be first trip by all circular matrixes in the c piece row behind the generator matrix G consist of.

3. parallel encoder as claimed in claim 1 is characterized in that, described sum array has u input and 255 outputs, and sum array is to the u position information bit s of parallel input _{1, k}, s _{2, k}..., s _{U, k}Make up summation, all sub-block first trip matrixes have 255 different non-zero column vectors, they and vector (s _{1, k}, s _{2, k}..., s _{U, k}) corresponding 255 the summation expression formulas of inner product, these summation expression formulas are realized with inputting XOR gate 255 more.

4. parallel encoder as claimed in claim 1 is characterized in that, described selection expander M _lAccording to code check η, square formation exponent number b and sub-block first trip matrix F _ρSubscript ρ from the output of sum array, select a part and be extended to b, to consist of vector (s _{1, k}, s _{2, k}..., s _{U, k}) and sub-block first trip matrix F _ρThe l section b bit of product, selection mode depend on the sub-block first trip matrix F that effective combination (η, b) is corresponding fully _ρBc column vector.

5. parallel encoding method that is suitable for 9 kinds of QC-LDPC codes that CCSDS deep space communication system adopts, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G _{I, j}The array that consists of, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, 3 kinds of different code check η are respectively 1/2,2/3,4/5,7 kinds of square formation exponent number b are respectively 32,64,128,256,512,1024,2048,9 kinds are effectively made up (η, b) is respectively (4/5,32), (2/3,64), (1/2,128), (4/5,128), (2/3,256), (1/2,512), (4/5,512), (2/3,1024) and (1/2,2048), for these 9 kinds of QC-LDPC codes, c=12 is all arranged, and 3 kinds of parameter a corresponding to different code checks are respectively 8,16,32,3 kinds of parametric t corresponding to different code checks are respectively 20,28,44, the greatest common divisor of 3 kinds of a is u=8, a=ux, 3 kinds of parameter x corresponding to different code checks are respectively 1,2,4, the corresponding code word v=of generator matrix G (s, p), that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p, take the b bit as one section, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), i segment information vector s _i=(s _{I, 1}, s _{I, 2}..., s _{I, b}), verification vector p is divided into the c section, i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described coding method may further comprise the steps:

In the 1st step, input message vector s is saved to register R ₁～R _a, zero clearing register R _A+1～R _t, and for selecting appropriate code check η and the square formation exponent number b of expander configuration;

The 2nd step, register R ₁～R _aSerial moves to left 1 time, is the parallel input vector (s of sum array _{1, k}, s _{2, k}..., s _{U, k}), the control end input ρ of all selection expanders=[(k-1)/b]+1, all selection expanders are selected respectively a part and are extended to b individual from the output of sum array, common formation vector (s _{1, k}, s _{2, k}..., s _{U, k}) sub-block first trip matrix F corresponding with effective combination (η, b) _ρProduct, b position two input XOR gate A _lL section b bit and register R with product _A+lThe results added that the serial ring shift left is 1 time, and deposit back register R _A+l

The 3rd step take 1 for step-length increases progressively the value that changes k, repeated the 2nd and goes on foot bx time, after finishing, and register R ₁～R _aThat store is information vector s=(s ₁, s ₂..., s _a), register R _A+1～R _tThat store is verification vector p=(p ₁, p ₂..., p _c);

The 4th step, parallel output code word v=(s, p).

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