CN102932009A - Lookup-table based method for parallel encoding of QC-LDPC (quasi-cyclic low-density parity-check) codes in DTMB system - Google Patents
Lookup-table based method for parallel encoding of QC-LDPC (quasi-cyclic low-density parity-check) codes in DTMB system Download PDFInfo
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Abstract
The invention relates to a solution to parallel encoding of the QC-LDPC (quasi-cyclic low-density parity-check) codes with three different code rates in a DTMB (Digital Terrestrial Multimedia Broadcasting) system. The solution is characterized in that a parallel QC-LDPC code encoder of the system mainly comprises four parts including a register, lookup tables, a bc-bit two-input exclusive-or gate and a b-bit two-input exclusive-or gate. The parallel QC-LDPC code encoder provided by the invention is compatible with multiple code rates, can fully use the functions of the lookup tables in the FPGA (field programmable gate array) logic resources to reduce the resource demand effectively under the condition of keeping the encoding speed unchanged, and has the advantages of being easy to control, consuming few resources and power, being low in cost, etc.
Description
Technical field
The present invention relates to the Digital Terrestrial Television Broadcast field, particularly the Parallel Implementation method of QC-LDPC code coder in a kind of DTMB system.
Background technology
Because the various distortions that exist in transmission channel and noise can produce transmitted signal and disturb, the situation that digital signal produces error code can appear in receiving terminal inevitably.In order to reduce the error rate, need to adopt channel coding technology.
Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with its excellent properties that approaches the Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.
The SRAA method is to utilize generator matrix G to encode.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, j(1≤i≤a, the array that 1≤j≤t) consists of, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with the verification vector is high-density matrix.The parallel SRAA method in a road is finished first encoding needs b+t clock cycle, needs (ac+t) b register, acb two input and door and acb two input XOR gate.
The DTMB standard has adopted the QC-LDPC code of 3 kinds of different code checks.For these 3 kinds of QC-LDPC codes, t=59 and b=127 are all arranged, one of common divisor of 3 kinds of a is u=6.Fig. 1 has provided parameter a and the c under the different code check η.
The existing solution of QC-LDPC high spped coding is to adopt the parallel SRAA method in a road in the DTMB system, and the parallel encoder of realizing 3 kinds of QC-LDPC codes needs 301371 registers, 278892 two inputs and door and 278892 two input XOR gate altogether.When adopting FPGA to realize, need more logical resource, will certainly cause equipment cost high, power consumption is large.
Summary of the invention
The large shortcoming of resources requirement that exists in the existing implementation for the multi code Rate of Chinese character QC-LDPC of DTMB system code high spped coding, the invention provides a kind of parallel encoding method based on look-up table, take full advantage of the look-up table function in the fpga logic resource, can keep effectively reducing resource requirement under the constant prerequisite of coding rate.
As shown in Figure 2, the parallel encoder of multi code Rate of Chinese character QC-LDPC code mainly is comprised of 4 parts in the DTMB system: register, look-up table, bc position two input XOR gate and b position two input XOR gate.Whole cataloged procedure divided for 4 steps finished: in the 1st step, input message vector s is saved to register R
C+1~R
t, zero clearing register R
1~R
cThe 2nd step, register R
C+1~R
tSerial moves to left 1 time, look-up table L
1~L
xDifference input vector h
1~ h
xWith output vector v
1~ v
x, bc position two input XOR gate B
1~B
X-1To vector v
1~ v
xSummation obtains vector v
X+1, b position two input XOR gate A
l(1≤l≤c) with vector v
X+1L section b bit and register R
lThe results added that the serial ring shift left is 1 time, and deposit back register R
lIn the 3rd step, repeat the 2nd and go on foot b time; The 4th step, parallel output code word (p, s).
The compatible multi code Rate of Chinese character of QC-LDPC parallel encoder provided by the invention can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thereby reach the purpose that reduces hardware cost and power consumption.
Can be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 has provided parameter a, c and the x under the different code check η;
Fig. 2 is the parallel encoder overall structure of compatible 3 kinds of code check QC-LDPC codes in the DTMB standard;
Fig. 3 has compared the parallel SRAA method in traditional a road and resource consumption of the present invention.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
The QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H all are the arrays that is made of circular matrix, has segmentation circulation characteristics, so be called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of one of lastrow (first trip is footline) ring shift right; From the angle of row, each row of circular matrix all are that previous column (first is terminal column) circulation moves down one result.The set that the row vector of circular matrix consists of is identical with the set of column vector formation, therefore, circular matrix fully can by it first trip or first characterize.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, j(1≤i≤a, the array that 1≤j≤t) consists of:
G(or H) the capable and b of continuous b row be called as respectively the capable and piece row of piece.Suppose g
I, j(1≤i≤a, 1≤j≤c) is circular matrix G
I, jFirst trip, can define in the following manner so a * bc rank piece first trip matrix F:
F is that the first trip by all circular matrixes in the c piece row before the generator matrix G consists of, and can be considered to be comprised of bc a dimensional vector.Suppose that a is not prime number, can be broken down into a=ux, wherein, u and x are all non-1 positive integer.So, the u (m-1) of piece first trip matrix F+1 ~ um(1≤m≤x) row has consisted of a u * bc rank matrix, is referred to as sub-block first trip matrix, is denoted as F
mF
mCan be considered and consisted of by bc u dimensional vector.
For the DTMB standard, the corresponding code word (p, s) of generator matrix G, that the front c piece row of G are corresponding is verification vector p, that rear a piece row are corresponding is information vector s.Take the b bit as one section, verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c); Information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a).For the segment information of the i(1≤i≤a) vector s
i, s is arranged
i=(s
I, 1, s
I, 2..., s
I, b).The DTMB standard has adopted the QC-LDPC code of 3 kinds of different code checks, and t=59 and b=127 are all arranged, and one of common divisor of 3 kinds of a is u=6.Fig. 1 has provided parameter a, c and the x under the different code check η.
Characteristics by formula (1), (2) and circular matrix, Fig. 2 has provided the parallel encoder that is applicable to 3 kinds of code check QC-LDPC codes in the DTMB standard, and it mainly is comprised of register, look-up table, bc position two input XOR gate and b position four kinds of functional modules of two input XOR gate.
Register R
1~R
cBe used for calculating and storage verification vector p=(p
1, p
2..., p
c), register R
C+1~R
tBe used for cache information vector s=(s
1, s
2..., s
a).
Look-up table L
1~L
xThe input of u position and the output of bc position are all arranged, finish respectively different u position information bits and sub-block first trip matrix F
1~ F
xProduct.The u position information bit s of parallel input
Mu-u+1, k, s
Mu-u+2, k..., s
Mu, k(1≤m≤x, 1≤k≤b) consist of vectorial h
m={ s
Mu-u+1, k, s
Mu-u+2, k..., s
Mu, k.Look-up table L
mInput be h
m, each road output is h
mWith sub-block first trip matrix F
mThe product of respective column, total output has consisted of vector v
mIf the unit of substantially searching of look-up table is considered as one two input and door, need so altogether xcb two inputs and door.
Bc position two input XOR gate B
1~B
X-1With vector v
1~ v
xBe added together, obtain vector v
X+1In fact, v
X+1In each element be the vector { h
1, h
2..., h
xWith the product of piece first trip matrix F respective column, v
X+1Vector { h
1, h
2..., h
xWith the product of piece first trip matrix F.
B position two input XOR gate A
l(1≤l≤c) with vector v
X+1Continuous b bit be added to register R
lIn.
Two input XOR gate sums of all bc position two input XOR gate and b position two input XOR gate are xcb.
The invention provides a kind of QC-LDPC parallel encoding method based on look-up table, in conjunction with the parallel encoder (as shown in Figure 2) of multi code Rate of Chinese character QC-LDPC code in the DTMB system, its coding step is described below:
In the 1st step, input message vector s is saved to register R
C+1~R
t, zero clearing register R
1~R
c
The 2nd step, register R
C+1~R
tSerial moves to left 1 time, look-up table L
1~L
xDifference input vector h
1~ h
xWith output vector v
1~ v
x, bc position two input XOR gate B
1~B
X-1To vector v
1~ v
xSummation obtains vector v
X+1, b position two input XOR gate A
l(1≤l≤c) with vector v
X+1L section b bit and register R
lThe results added that the serial ring shift left is 1 time, and deposit back register R
l
The 3rd step repeated the 2nd and goes on foot b time, after finishing, and register R
1~R
cThat store is verification vector p=(p
1, p
2..., p
c), register R
C+1~R
tThat store is information vector s=(s
1, s
2..., s
a);
The 4th step, parallel output code word (p, s).
Be not difficult to find out that from above step whole cataloged procedure needs b+t clock cycle altogether, this and the parallel SRAA method in traditional a road are identical.
Fig. 3 has compared the parallel SRAA method in traditional a road and resource consumption of the present invention.Notice that the unit of substantially searching with look-up table is considered as one two input and door here.Can know from Fig. 3 and to see, compare with the parallel SRAA method in a road, the present invention used less register, XOR gate and with door, the amount of expending is respectively 7%, 17% and 17% of the parallel SRAA method in a road.
As fully visible, compare with the parallel SRAA method in traditional a road, the present invention has kept coding rate, can take full advantage of the look-up table function in the fpga logic resource, has that control is simple, resource consumption is few, power consumption is little, low cost and other advantages.
Above-described embodiment is more preferably embodiment of the present invention, and the common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacement all should be included in protection scope of the present invention.
Claims (4)
1. parallel encoder that is suitable for 3 kinds of different code check QC-LDPC codes that the DTMB system adopts, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, jThe array that consists of, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, 3 kinds of different code check η are respectively 0.4,0.6,0.8, for these 3 kinds different code check QC-LDPC codes, t=59 and b=127 are all arranged, and 3 kinds of parameter a corresponding to different code checks are respectively 24,36,48,3 kinds of parameter c corresponding to different code checks are respectively 35,23,11, one of common divisor of 3 kinds of a is u=6, a=ux, 3 kinds of parameter x corresponding to different code checks are respectively 4,6,8, the corresponding code word (p of generator matrix G, s), that the front c piece row of G are corresponding is verification vector p, and that rear a piece row are corresponding is information vector s, take the b bit as one section, verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c), information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), i segment information vector s
i=(s
I, 1, s
I, 2..., s
I, b), it is characterized in that described encoder comprises following parts:
Register R
1~R
t, register R
1~R
cBe used for calculating and storage verification vector p=(p
1, p
2..., p
c), register R
C+1~R
tBe used for cache information vector s=(s
1, s
2..., s
a);
Look-up table L
1~L
x, the vectorial h that the input u position information bit that walks abreast respectively consists of
m={ s
Mu-u+1, k, s
Mu-u+2, k..., s
Mu, k, parallel output bc bit vector v
m, wherein, 1≤m≤x, 1≤k≤b;
Bc position two input XOR gate B
1~B
X-1, with vector v
1~ v
xBe added together, obtain vector v
X+1
B position two input XOR gate A
1~A
c, A
lWith vector v
X+1The continuous b bit of l section be added to register R
lIn, wherein, 1≤l≤c.
2. parallel encoder as claimed in claim 1 is characterized in that, described look-up table L
1~L
xFinish respectively different u position information bits and sub-block first trip matrix F
1~ F
xProduct, look-up table L
mInput be h
m, each road output is h
mWith sub-block first trip matrix F
mThe product of respective column, total output has consisted of vector v
m
3. parallel encoder as claimed in claim 1 is characterized in that, described vector v
X+1In each element be the vector { h
1, h
2..., h
xWith the product of piece first trip matrix F respective column, v
X+1Vector { h
1, h
2..., h
xWith the product of piece first trip matrix F.
4. parallel encoding method that is suitable for 3 kinds of different code check QC-LDPC codes that the DTMB system adopts, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, jThe array that consists of, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, 3 kinds of different code check η are respectively 0.4,0.6,0.8, for these 3 kinds different code check QC-LDPC codes, t=59 and b=127 are all arranged, and 3 kinds of parameter a corresponding to different code checks are respectively 24,36,48,3 kinds of parameter c corresponding to different code checks are respectively 35,23,11, one of common divisor of 3 kinds of a is u=6, a=ux, 3 kinds of parameter x corresponding to different code checks are respectively 4,6,8, the corresponding code word (p of generator matrix G, s), that the front c piece row of G are corresponding is verification vector p, and that rear a piece row are corresponding is information vector s, take the b bit as one section, verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c), information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), i segment information vector s
i=(s
I, 1, s
I, 2..., s
I, b), it is characterized in that described coding method may further comprise the steps:
In the 1st step, input message vector s is saved to register R
C+1~R
t, zero clearing register R
1~R
c
The 2nd step, register R
C+1~R
tSerial moves to left 1 time, look-up table L
1~L
xDifference input vector h
1~ h
xWith output vector v
1~ v
x, bc position two input XOR gate B
1~B
X-1To vector v
1~ v
xSummation obtains vector v
X+1, b position two input XOR gate A
lWith vector v
X+1L section b bit and register R
lThe results added that the serial ring shift left is 1 time, and deposit back register R
l, wherein, 1≤l≤c;
The 3rd step repeated the 2nd and goes on foot b time, after finishing, and register R
1~R
cThat store is verification vector p=(p
1, p
2..., p
c), register R
C+1~R
tThat store is information vector s=(s
1, s
2..., s
a);
The 4th step, parallel output code word (p, s).
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CN104539297B (en) * | 2015-01-30 | 2018-06-19 | 荣成市鼎通电子信息科技有限公司 | High speed QC-LDPC encoders based on four level production lines in DTMB |
CN104539297A (en) * | 2015-01-30 | 2015-04-22 | 荣成市鼎通电子信息科技有限公司 | Four-stage production line-based high-speed QC-LDPC coder in DTMB |
CN104993834A (en) * | 2015-06-20 | 2015-10-21 | 荣成市鼎通电子信息科技有限公司 | QC-LDPC parallel encoder in WPAN based on lookup tables |
CN104980170A (en) * | 2015-06-20 | 2015-10-14 | 荣成市鼎通电子信息科技有限公司 | QC-LDPC parallel encoder, based on look-up table, in CDR |
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