CN104539297B - High speed QC-LDPC encoders based on four level production lines in DTMB - Google Patents

Abstract

The present invention provides the high speed QC LDPC encoders based on four level production lines in a kind of DTMB, the encoder include after the multiplier of 1 sparse matrix and vector, 1 I type to iterative circuit, 1 high-density matrix with after the multiplier of vector and 1 II type to iterative circuit.Sparse matrix realizes the multiplying of sparse matrix and vector with vectorial multiplier, and high-density matrix realizes high-density matrix and the multiplying of vector with vectorial multiplier, backward interative computation is all realized to iterative circuit after I types and II types.Entire cataloged procedure is divided into 4 level production lines.4/5 code check high speed QC LDPC encoders have many advantages, such as that simple in structure, at low cost, handling capacity is big in DTMB systems provided by the invention.

Description

High speed QC-LDPC encoders based on four level production lines in DTMB

Technical field

The present invention relates to field of channel coding, the high speed QC- based on four level production lines in more particularly to a kind of DTMB systems LDPC encoder.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The life of QC-LDPC codes All it is the array being made of circular matrix into matrix G and check matrix H, there is stages cycle, therefore be referred to as QC-LDPC Code.The first trip of circular matrix is footline ring shift right 1 as a result, remaining each row is all the knot of its lastrow ring shift right 1 Fruit, therefore, circular matrix are characterized completely by its first trip.In general, the first trip of circular matrix is referred to as its generator polynomial.

DTMB standards use the QC-LDPC codes of system form, and the left-half of generator matrix G is a unit matrix, Right half part is by e × c b × b rank circular matrixes G_i,j(0≤i<e,e≤j<T, t=e+c) form array, it is as follows：

Wherein, I is b × b rank unit matrixs, and 0 is b × b rank full null matrix.Continuous b rows and the b row of G are known respectively as block Row and block row.By formula (1) it is found that G has e blocks row and t blocks row.DTMB standards employ a kind of QC-LDPC codes of code check η=4/5, For the code, t=59, e=48, c=11, b=127.

The existing solution of 4/5 code check QC-LDPC encoders is added based on 11 I type shift registers in DTMB standards The serial encoder of accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) circuit.By 11 The serial encoder that SRAA-I circuits are formed completes coding within 6096 clock cycle.2794 registers of program needs, 1397 two inputs and door and 1397 two input XOR gates, it is also necessary to which the generation of 67056 bit ROM storage circular matrixes is multinomial Formula.There are two shortcomings for the program：First, needing a large amount of memories, lead to circuit cost height；Second is that serial input information bit, is compiled Code speed is slow.

Invention content

The existing implementation of 4/5 code check QC-LDPC encoders is lacked there are of high cost, coding rate is slow in DTMB systems Point, for these technical problems, the present invention provides a kind of high speed QC-LDPC encoders based on four level production lines.

As shown in Fig. 2, the high speed QC-LDPC encoders based on four level production lines are mainly made of 4 parts in DTMB systems： To iteration after iterative circuit, high-density matrix and the multiplier of vector and II types after the multiplier of sparse matrix and vector, I types Circuit.4 steps of cataloged procedure point are completed：1st step calculates vector f and w using the multiplier of sparse matrix and vector；2nd step, makes With after I types vector q and x is calculated to iterative circuit；3rd step is verified using high-density matrix and the multiplier calculating section of vector Vectorial p_x；4th step obtains part verification vector p using vector y, y is calculated to iterative circuit after II types with vector q exclusive or_y, so as to It obtains verifying vectorial p=(p_x,p_y)。

4/5 code check high speed QC-LDPC coder structures are simple in DTMB systems provided by the invention, can be compiled significantly improving Under conditions of code speed, memory is reduced, so as to reduce cost, improves handling capacity.

Advantage about the present invention can be further understood with method by following detailed description and accompanying drawings.

Description of the drawings

Fig. 1 is the structure diagram of near lower triangular check matrix after ranks exchange；

Fig. 2 is the QC-LDPC cataloged procedures based on four level production lines；

Fig. 3 is the functional block diagram of ring shift left accumulator RLA circuits；

Fig. 4 is the multiplier by a kind of high-density matrix that 1 RLA circuit is formed and vector；

Fig. 5 is the multiplier of sparse matrix and vector；

Fig. 6 gives sparse matrix and the connection relation of each multi input XOR gate and register in the multiplier of vector；

Fig. 7 is to iterative circuit after I types；

Fig. 8 gives the block position and its ring shift right digit in matrix Q where nonzero circle matrix；

Fig. 9 is to iterative circuit after II types；

Figure 10 gives the block position and its ring shift right digit in matrix Y where nonzero circle matrix；

Figure 11 summarizes each coding step of encoder and the hardware resource needed for entire cataloged procedure and processing time.

Specific embodiment

Presently preferred embodiments of the present invention is elaborated below in conjunction with the accompanying drawings, so that advantages and features of the invention can be more It is easy to be readily appreciated by one skilled in the art, apparent is explicitly defined so as to be made to protection scope of the present invention.

The row weight and row heavy phase of circular matrix are same, are denoted as w.If w=0, then the circular matrix is full null matrix.If W=1, then the circular matrix is replaceable, referred to as permutation matrix, it can be by several positions of unit matrix I ring shift rights It obtains.The check matrix H of QC-LDPC codes is by c × t b × b rank circular matrixes H_j,k(1≤j≤c, 1≤k≤t, t=e+c) The following array formed：

Under normal conditions, any circular matrix in check matrix H is either full null matrix (w=0) or is displacement square Battle array (w=1).Enable circular matrix H_j,kFirst trip g_j,k=(g_j,k,1,g_j,k,2,…,g_j,k,b) it is its generator polynomial, wherein g_j,k,m =0 or 1 (1≤m≤b).Because H is sparse, g_j,kOnly 1 ' 1 ', even without ' 1 '.

For the QC-LDPC codes of 4/5 code check in DTMB systems, corresponding preceding 48 pieces of row of H are information vector a, latter 11 pieces It is verification vector p to arrange corresponding.Using 127 bits as one section, information vector a is divided into 48 sections, i.e. a=(a₁,a₂,…,a₄₈)； Verification vector p is divided into 11 sections, i.e. p=(p₁,p₂,…,p₁₁)。

To check matrix H into every trade exchange and row swap operation, it is converted near lower triangular shape H_ALT, such as Fig. 1 institutes Show.The process that ranks exchange is as follows：1st step is arranged into row block and is exchanged, and preceding 9 pieces of row are exchanged with latter 48 pieces row；2nd step, into row block row It exchanges, first trip moves to footline；All permutation matrixes are distinguished ring shift left 1 by the 3rd step.

In Fig. 1, the unit of all matrixes is all b=127 bits rather than 1 bit.A is by 9 × 48 127 × 127 Rank circular matrix is formed, and B is made of 9 × 2 127 × 127 rank circular matrixes, and T is by 9 × 9 127 × 127 rank Cyclic Moments Battle array is formed, and C is made of 2 × 48 127 × 127 rank circular matrixes, and D is made of 2 × 2 127 × 127 rank circular matrixes, E It is to be made of 2 × 9 127 × 127 rank circular matrixes.T is lower triangular matrix, and u=2 reflects check matrix H_ALTWith lower triangle The degree of closeness of matrix.In Fig. 1, matrix A and C corresponding informance vector a, matrix B and D correspond to part verification vector p_x= (p₁,p₂), matrix T and E then correspond to remaining verification vector p_y=(p₃,p₄,…,p₁₁).P=(p_x,p_y).Above-mentioned matrix and vector Meet following relationship：

p_x ^Τ=Φ (ET^-1Aa^Τ+Ca^Τ) (3)

p_y ^Τ=T^-1(Aa^Τ+Bp_x ^Τ) (4)

Wherein, Φ=(ET^-1B+D)^-1, subscript^ΤWith^-1Transposition and inverse is represented respectively.It is well known that circular matrix it is inverse, multiply Product and be still circular matrix.Therefore, Φ is also the array being made of circular matrix.Although matrix E, T, B and D are sparse Matrix, but Φ is no longer sparse but highdensity under normal conditions.

Enable f^T=Aa^T, q^T=T^-1f^T, w^T=Ca^T, x^T=Eq^T+w^T, p_x ^T=Φ x^T, y^T=T^–1Bp_x ^TAnd p_y ^T=q^T+y^T.To Amount f and w can be calculated by following formula：

Wherein,

q^T=T^–1f^TAnd x^T=Eq^T+w^TIt may make up following matrix equality：

Wherein,

Once p is calculated_x, y^T=T^–1Bp_x ^TIt can be rewritten as：

[B T][p_x y]^Τ=Y [p_x y]^Τ=0 (9)

Wherein,

Y=[B T] (10)

Because Q and Y are lower triangular matrix as T, the y in [q x] and formula (9) in formula (7) can be used The calculation of backward iteration.

Φ is related to high-density matrix and the multiplication of vector, and F is related to the multiplication of sparse matrix and vector, and Q and Y are related to backward Iterative calculation.From the above discussion, a kind of QC-LDPC cataloged procedures based on four level production lines can be provided, as shown in Figure 2.

p_x ^T=Φ x^TIt is equivalent to p_x=x Φ^T.Enable x=(x₁,x₂,…,x_u×b).Define u bit vectors s_n=(x_n,x_n+b,…, x_n+(u-1)×b), wherein 1≤n≤b.Enable Φ_j(1≤j≤u) is by Φ^TJth block row in all circular matrix generator polynomial structures Into u × b rank matrixes.Then have

p_j=(... ((0+s₁Φ_j)^ls(1)+s₂Φ_j)^ls(1)+…+s_bΦ_j)^ls(1) (11)

Wherein, subscript^ls(1)Represent ring shift left 1.

A kind of ring shift left accumulator (Rotate-Left-Accumulator, RLA) circuit can obtain by formula (11), such as Shown in Fig. 3.The index of look-up table is u bit vectors s_n, look-up table L_jIt is previously stored variable u bit vectors and fixed Φ_j's Be possible to product, therefore need 2^uThe read-only memory (Read-Only Memory, ROM) of b bits.B bit registers R₁, R₂,…,R_uIt is respectively used to the array section x of buffering vector x₁,x₂,…,x_u, b bit registers R_u+jFor storing p_xVerification section p_j.1 RLA circuit counting vectors p_jNeed b clock cycle.

For DTMB systems, 2 RLA circuit countings p are used_x=(p₁,p₂) it is a kind of reasonable plan, height as shown in Figure 4 The multiplier of density matrix and vector.High-density matrix is with vectorial multiplier by 2 look-up table L₁,L₂, 4 127 bit registers Device R_3,1,R_3,2,…,R_3,4With 2 127 two input XOR gate X_3,1,X_3,2Composition.Look-up table L₁,L₂2 variable ratios are stored respectively Special vector and fixed matrix Φ₁,Φ₂Be possible to product, register R_3,1,R_3,2It is respectively used to the array section of buffering vector x x₁,x₂, register R_3,3,R_3,4It is respectively used to storage p_xVerification section p₁,p₂.2 RLA circuits need to use 127 two input exclusive or Door, ROM and 254 register of 1016 bits.2 RLA circuit counting vectors p_xNeed 127 clock cycle.Using highly dense The multiplier for spending matrix and vector calculates vector p_xThe step of it is as follows：

1st step resets register R_3,3,R_3,4, input vector section x₁,x₂, they are stored in register R respectively_3,1,R_3,2In；

2nd step, register R_3,1,R_3,2Ring shift left 1 time simultaneously, XOR gate X_3,1,X_3,2Respectively to look-up table L₁,L₂It is defeated Go out and register R_3,3,R_3,4Content carry out exclusive or, exclusive or result is stored back to register R respectively after ring shift left 1 time_3,3,R_3,4；

3rd step, repeats the 2nd step 127 times, after the completion, register R_3,3,R_3,4The content of storage is verification section p respectively₁,p₂, It constitutes part verification vector p_x。

Enable f=(f₁,f₂,…,f₉) and w=(f₁₀,f₁₁), then [f w]=(f₁,f₂,…,f₁₁).By formula (5) it is found that f_jIt is The jth block row and a of matrix F^TProduct, i.e.,

Wherein, 1≤i≤48,1≤j≤11.f_jThe n-th bit f_j,n(1≤n≤127) are

Wherein, subscript^rs(n–1)With^ls(n–1)Ring shift right n -1 and ring shift left n -1 are represented respectively.Since any cycle Matrix generator polynomial g_j,iOnly a small amount of ' 1 ' even complete zero, then the inner product in formula (13) can be by posting ring shift left The tap of storage sums to realize, the multiplier of sparse matrix as shown in Figure 5 and vector.The multiplier of sparse matrix and vector By 59 127 bit register R_1,1,R_1,2,…,R_1,59With 11 multi input XOR gate X_1,1,X_1,2,…,X_1,11Composition.Register R_1,1,R_1,2,…,R_1,48For loading and ring shift left message segment a₁,a₂,…,a₄₈, register R_1,49,R_1,50,…,R_1,59For Store the array section f of [f w]₁,f₂,…,f₁₁.All circular matrixes generation that partially connected in Fig. 5 is depended in matrix F is more Item formula.If g_j,i,m=1 (1≤m≤127), then message segment a_iM bits be connected to XOR gate X_1,j.Therefore, register R_1,iAll taps depend on the nonzero element positions of all circular matrix generator polynomials in i-th piece of matrix F row, and Multi input XOR gate X_1,jInput depend on matrix F jth block row in all circular matrix generator polynomials nonzero element where Position.Fig. 6 gives sparse matrix and the connection relation of each multi input XOR gate and register in the multiplier of vector.Since All circular matrix generator polynomials in F share α=127 ' 1 ', then the multiplier of sparse matrix and vector needs to use (α-c)=250 two input XOR gate and calculate f simultaneously_1,n,f_2,n,…,f_11,n.F and w can have been calculated within 127 clock cycle Finish.The step of calculating vector f and w using the multiplier of sparse matrix and vector is as follows：

1st step, input message segment a₁,a₂,…,a₄₈, they are stored in register R respectively_1,1,R_1,2,…,R_1,48In；

2nd step, register R_1,1,R_1,2,…,R_1,48Ring shift left 1 time simultaneously, XOR gate X_1,1,X_1,2,…,X_1,11Respectively will Exclusive or result is moved to left into register R_1,49,R_1,50,…,R_1,59In；

3rd step, repeats the 2nd step 127 times, after the completion, register R_1,49,R_1,50,…,R_1,59The content of storage be respectively to Measure section f₁,f₂,…,f₁₁, they constitute vector f and w.

Formula (7) implies backward iterative operation, it is necessary to solve vector q and x paragraph by paragraph.Define [q x]=(q₁,q₂,…, q₁₁), and it is initialized as complete zero.First, q₁Exactly equal to f₁.Secondly, q₂It is the 2nd piece of row of matrix Q and vectorial [q x]^TProduct with f₂2 He of mould.Then, q₃It is the 3rd piece of row of matrix Q and vectorial [q x]^TProduct and f₃2 He of mould.It repeats the above process, until Q is calculated₁₁Until, to iterative circuit after I types as shown in Figure 7.To iterative circuit by 11 127 bit register R after I types_2,1, R_2,2,…,R_2,11With 10 multi input modulo 2 adder A_2,2,A_2,3,…,A_2,11Composition.

To calculate q_jFor (1≤j≤11).Nonzero circle matrix in check matrix H is typically the cycle of unit matrix Move to right version.Assuming that having N number of nonzero circle matrix in the jth block row of matrix Q, their ring shift right digit is s respectively_j,k1, s_j,k2,…,s_j,kN(1≤k1,k2,…,kN<j).Then,

Because of N very littles, formula (14) can be by a multi input modulo 2 adder to inputting ring shift left in 1 clock It calculates and finishes in period.Therefore, calculate vectorial [q x] needs 11 clock cycle altogether.Since β=29 non-zero is shared in matrix Q Circular matrix, then need (β-c) b=2286 two input XOR gate of use to iterative circuit after I types.

Matrix Q is by 11 × 11 127 × 127 rank circular matrix Q_j,kThe array that (1≤j≤11,1≤k≤11) are formed. Nonzero circle matrix Q_j,kRing shift right digit relative to 127 × 127 rank unit matrixs is s_j,k, 0≤s_j,k<127.For ease of Description, complete zero circular matrix are denoted as s relative to the ring shift right digit of 127 × 127 rank circular matrixes_j,k='-'.In the figure 7, Nonzero circle matrix Q_j,kCorresponding array section q_kBy ring shift left s_j,kMulti input modulo 2 adder A is sent into behind position_2,jIn with vector Section f_jXOR operation is carried out, the corresponding array section of complete zero circular matrix is not involved in XOR operation, A_2,jResult of calculation be q_j, deposit Register R_2,jIn.Fig. 8 gives the block position and its ring shift right digit in matrix Q where nonzero circle matrix.Use I types The step of backward iterative circuit calculates vector q and x is as follows：

1st step, input vector section f₁, by array section q₁=f₁It is stored in register R_2,1In；

2nd step, input vector section f_j, nonzero circle matrix Q_j,kCorresponding array section q_kBy ring shift left s_j,kIt is sent into behind position Multi input modulo 2 adder A_2,jIn with array section f_jCarry out XOR operation, exclusive or result q_jIt is stored into register R_2,jIn, wherein, 2 ≤j≤11,1≤k<J, 0≤s_j,k<127；

3rd step incrementally changes the value of j with 1 for step-length, repeats the 2nd step 10 times, finally, register R_2,1,R_2,2,…, R_2,11Storage is array section q respectively₁,q₂,…,q₁₁, they constitute vectorial q and x.

Formula (9) also implies backward iterative operation, it is necessary to solve vector y paragraph by paragraph.Define y=(y₁,y₂,…,y₉), and just Beginning turns to complete zero.First, y₁It is the 1st piece of row of matrix Y and vector [p_x y]^TProduct.Secondly, y₂Be matrix Y the 2nd piece of row with Vector [p_x y]^TProduct.It repeats the above process, until having calculated y₉Until, to iterative circuit after II types as shown in Figure 9.After II types To iterative circuit by 11 127 bit register R_4,1,R_4,2,…,R_4,11With 9 multi input modulo 2 adder A_4,1,A_4,2,…, A_4,9Composition.Calculate vector y needs 9 clock cycle altogether.Since ξ=27 nonzero circle matrix is shared in matrix Y, then II types Backward iterative circuit needs to use (ξ -2c+2u) b=1143 two input XOR gate.Matrix Y is followed by 9 × 11 127 × 127 ranks Ring matrix Y_j,kThe array that (1≤j≤9,1≤k≤11) are formed.Nonzero circle matrix Y_j,kRelative to 127 × 127 rank unit matrixs Ring shift right digit be s_j,k, 0≤s_j,k<127.Figure 10 give block position in matrix Y where nonzero circle matrix and its Ring shift right digit.Using as follows the step of calculating vector y to iterative circuit after II types：

1st step, input validation section p₁,p₂, they are stored in register R respectively_4,10,R_4,11In；

2nd step, nonzero circle matrix Y_j,kCorresponding array section p_kOr y_kBy ring shift left s_j,kMulti input mould 2 is sent into behind position Adder A_4,jMiddle carry out XOR operation, exclusive or result y_jIt is stored into register R_4,jIn, wherein, 1≤j≤9,1≤k<1+j, 0≤ s_j,k<127；

3rd step incrementally changes the value of j with 1 for step-length, repeats the 2nd step 9 times, finally, register R_4,1,R_4,2,…,R_4,9 Storage is array section y respectively₁,y₂,…,y₉, they constitute vectorial y.

The present invention provides a kind of high speed QC-LDPC coding methods based on four level production lines, suitable for DTMB systems 4/5 code check QC-LDPC codes, coding step is described as follows：

1st step calculates vector f and w using the multiplier of sparse matrix and vector；

2nd step calculates vector q and x using after I types to iterative circuit；

3rd step uses high-density matrix and the multiplier calculating section verification vector p of vector_x；

4th step obtains part verification vector p using vector y, y is calculated to iterative circuit after II types with vector q exclusive or_y, from And it obtains verifying vectorial p=(p_x,p_y)。

When Figure 11 summarizes each coding step of encoder and hardware resource consumption needed for entire cataloged procedure and processing Between.

It is not difficult to find out from Figure 11, when assembly line is full of, when entire cataloged procedure needs max (t-c+b, c, u+b)=175 altogether The clock period, less than 6096 clock cycle needed for the serial encoding method based on 11 SRAA-I circuits.The former coding speed Degree is 34.8 times of the latter.

In DTMB standards the existing solution of 4/5 code check QC-LDPC encoders need 2794 registers, 1397 two Input and door and 1397 two input XOR gates, it is also necessary to which 67056 bit ROM store the generator polynomial of circular matrix.And this Invention needs 11121 registers, 0 two input and door and 3933 two input XOR gates, it is only necessary to 1016 bit ROM.

To sum up, compared with traditional serial SRAA methods, it is excellent that the present invention has that coding rate is fast, memory consumption is few etc. Point.

One of the above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, Any those skilled in the art disclosed herein technical scope in, the change that can expect without creative work Change or replace, should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with claims Subject to the protection domain limited.

Claims (3)

1. the high speed QC-LDPC encoders based on four level production lines in a kind of DTMB, the check matrix H of 4/5 code check QC-LDPC codes It is the array being made of c × t b × b rank circular matrix, wherein, c=11, t=59, b=127, e=t-c=48 verify square Battle array H is transformed near lower triangular shape by ranks exchange, can be divided into 6 submatrixs,A is by 9 × 48 A b × b ranks circular matrix is formed, and B is made of 9 × 2 b × b rank circular matrixes, and lower triangular matrix T is by 9 × 9 b × b Rank circular matrix is formed, and C is made of 2 × 48 b × b rank circular matrixes, and D is made of 2 × 2 b × b rank circular matrixes, E It is to be made of 2 × 9 b × b rank circular matrixes, Φ=(ET^-1B+D)^-1It is to be made of 2 × 2 b × b rank circular matrixes, Φ_jIt is By Φ^TJth block row in 2 × b rank matrixes for forming of all circular matrix generator polynomials, wherein, subscript^TWith^-1It represents respectively Transposition and inverse, 1≤j≤2,It is by 11 × 11 b × b rank circular matrixes Q_j,kIt forms, wherein, I is unit matrix, 0 is full null matrix, 1≤j≤11,1≤k≤11, nonzero circle matrix Q_j,kRelative to the ring shift right position of b × b rank unit matrixs Number is s_j,k, wherein, 0≤s_j,k<B, Y=[B T] are by 9 × 11 b × b rank circular matrixes Y_j,kIt forms, wherein, 1≤j≤9,1 ≤ k≤11, nonzero circle matrix Y_j,kRing shift right digit relative to b × b rank unit matrixs is s_j,k, wherein, 0≤s_j,k<B, A and C corresponding informance vector a, matrix B and D correspond to part verification vector p_x, matrix T and E then correspond to remaining verification vector p_y, Verify vector p=(p_x,p_y), using b bits as one section, information vector a is divided into 48 sections, i.e. a=(a₁,a₂,…,a₄₈), verification Vectorial p is divided into 11 sections, i.e. p=(p₁,p₂,…,p₁₁), p_x=(p₁,p₂), p_y=(p₃,p₄,…,p₁₁), vector f is divided It is 9 sections, i.e. f=(f₁,f₂,…,f₉), vectorial w is divided into 2 sections, i.e. w=(f₁₀,f₁₁), [f w]=(f₁,f₂,…,f₁₁), to Amount q is divided into 9 sections, i.e. q=(q₁,q₂,…,q₉), vector x is divided into 2 sections, i.e. x=(p₁₀,p₁₁), [q x]=(q₁, q₂,…,q₁₁), vectorial y is divided into 9 sections, i.e. y=(y₁,y₂,…,y₉), which is characterized in that the encoder is included with lower part Part：

The multiplier of sparse matrix and vector, by 59 127 bit register R_1,1,R_1,2,…,R_1,59With 11 multi input exclusive or Door X_1,1,X_1,2,…,X_1,11Composition, for calculating vector f and w；The multiplier of the sparse matrix and vector calculates vector f and w The step of it is as follows：

1st step, input message segment a₁,a₂,…,a₄₈, they are stored in register R respectively_1,1,R_1,2,…,R_1,48In；

2nd step, register R_1,1,R_1,2,…,R_1,48Ring shift left 1 time simultaneously, XOR gate X_1,1,X_1,2,…,X_1,11Respectively by exclusive or As a result it moves to left into register R_1,49,R_1,50,…,R_1,59In；

3rd step, repeats the 2nd step 127 times, after the completion, register R_1,49,R_1,50,…,R_1,59The content of storage is array section respectively f₁,f₂,…,f₁₁, they constitute vector f and w；

To iterative circuit after I types, by 11 127 bit register R_2,1,R_2,2,…,R_2,11With 10 multi input modulo 2 adders A_2,2,A_2,3,…,A_2,11Composition, for calculating vectorial q and x；The step of calculating vector q and x to iterative circuit after the I types is such as Under：

1st step, input vector section f₁, by array section q₁=f₁It is stored in register R_2,1In；

2nd step, input vector section f_j, nonzero circle matrix Q_j,kCorresponding array section q_kBy ring shift left s_j,kIt how defeated is sent into behind position Enter modulo 2 adder A_2,jIn with array section f_jCarry out XOR operation, exclusive or result q_jIt is stored into register R_2,jIn, wherein, 2≤j≤ 11,1≤k<J, 0≤s_j,k<127；

3rd step incrementally changes the value of j with 1 for step-length, repeats the 2nd step 10 times, finally, register R_2,1,R_2,2,…,R_2,11It deposits Storage is array section q respectively₁,q₂,…,q₁₁, they constitute vectorial q and x；

High-density matrix and the multiplier of vector, by 2 look-up table L₁,L₂, 4 127 bit register R_3,1,R_3,2,…,R_3,4With 2 127 two input XOR gate X_3,1,X_3,2Composition, for calculating section verification vector p_x, look-up table L₁,L₂It stores respectively variable 2 bit vectors and fixed matrix Φ₁,Φ₂Be possible to product；The high-density matrix and the multiplier of vector calculate Vectorial p_xThe step of it is as follows：

1st step resets register R_3,3,R_3,4, input vector section x₁,x₂, they are stored in register R respectively_3,1,R_3,2In；

2nd step, register R_3,1,R_3,2Ring shift left 1 time simultaneously, XOR gate X_3,1,X_3,2Respectively to look-up table L₁,L₂Output and Register R_3,3,R_3,4Content carry out exclusive or, exclusive or result is stored back to register R respectively after ring shift left 1 time_3,3,R_3,4；

3rd step, repeats the 2nd step 127 times, after the completion, register R_3,3,R_3,4The content of storage is verification section p respectively₁,p₂, they Constitute part verification vector p_x；

To iterative circuit after II types, by 11 127 bit register R_4,1,R_4,2,…,R_4,11With 9 multi input modulo 2 adders A_4,1,A_4,2,…,A_4,9Composition, for calculating vectorial y, y obtains part verification vector p with vector q exclusive or_y, so as to be verified Vectorial p=(p_x,p_y)；The step of calculating vector y to iterative circuit after the II types is as follows：

1st step, input validation section p₁,p₂, they are stored in register R respectively_4,10,R_4,11In；

2nd step, nonzero circle matrix Y_j,kCorresponding array section p_kOr y_kBy ring shift left s_j,kMulti input nodulo-2 addition is sent into behind position Device A_4,jMiddle carry out XOR operation, exclusive or result y_jIt is stored into register R_4,jIn, wherein, 1≤j≤9,1≤k<2+j, 0≤s_j,k< 127；

3rd step incrementally changes the value of j with 1 for step-length, repeats the 2nd step 9 times, finally, register R_4,1,R_4,2,…,R_4,9Storage Be array section y respectively₁,y₂,…,y₉, they constitute vectorial y.

2. the high speed QC-LDPC encoders based on four level production lines, feature exist in a kind of DTMB according to claim 1 In the process that the ranks exchange is as follows：

1st step is arranged into row block and is exchanged, and preceding 9 pieces of row are exchanged with latter 48 pieces row；

2nd step, exchanges into row block row, and first trip moves to footline；

All permutation matrixes are distinguished ring shift left 1 by the 3rd step.

3. the high speed QC-LDPC coding methods based on four level production lines in a kind of DTMB, the verification square of 4/5 code check QC-LDPC codes Battle array H is the array being made of c × t b × b rank circular matrix, wherein, c=11, t=59, b=127, e=t-c=48, verification Matrix H is transformed near lower triangular shape by ranks exchange, can be divided into 6 submatrixs,A be by 9 × 48 b × b ranks circular matrixes are formed, and B is made of 9 × 2 b × b rank circular matrixes, lower triangular matrix T be by 9 × 9 b × B ranks circular matrix is formed, and C is made of 2 × 48 b × b rank circular matrixes, and D is made of 2 × 2 b × b rank circular matrixes, E is made of 2 × 9 b × b rank circular matrixes, Φ=(ET^-1B+D)^-1It is to be made of 2 × 2 b × b rank circular matrixes, Φ_jIt is By Φ^TJth block row in 2 × b rank matrixes for forming of all circular matrix generator polynomials, wherein, subscript^TWith^-1It represents respectively Transposition and inverse, 1≤j≤2,It is by 11 × 11 b × b rank circular matrixes Q_j,kIt forms, wherein, I is unit matrix, 0 is full null matrix, 1≤j≤11,1≤k≤11, nonzero circle matrix Q_j,kRelative to the ring shift right position of b × b rank unit matrixs Number is s_j,k, wherein, 0≤s_j,k<B, Y=[B T] are by 9 × 11 b × b rank circular matrixes Y_j,kIt forms, wherein, 1≤j≤9,1 ≤ k≤11, nonzero circle matrix Y_j,kRing shift right digit relative to b × b rank unit matrixs is s_j,k, wherein, 0≤s_j,k<B, A and C corresponding informance vector a, matrix B and D correspond to part verification vector p_x, matrix T and E then correspond to remaining verification vector p_y, Verify vector p=(p_x,p_y), using b bits as one section, information vector a is divided into 48 sections, i.e. a=(a₁,a₂,…,a₄₈), verification Vectorial p is divided into 11 sections, i.e. p=(p₁,p₂,…,p₁₁), p_x=(p₁,p₂), p_y=(p₃,p₄,…,p₁₁), vector f is divided It is 9 sections, i.e. f=(f₁,f₂,…,f₉), vectorial w is divided into 2 sections, i.e. w=(f₁₀,f₁₁), [f w]=(f₁,f₂,…,f₁₁), to Amount q is divided into 9 sections, i.e. q=(q₁,q₂,…,q₉), vector x is divided into 2 sections, i.e. x=(p₁₀,p₁₁), [q x]=(q₁, q₂,…,q₁₁), vectorial y is divided into 9 sections, i.e. y=(y₁,y₂,…,y₉), which is characterized in that the coding method includes following Step：

1st step calculates vector f and w using the multiplier of sparse matrix and vector；The multiplier meter of the sparse matrix and vector The step of calculating vector f and w is as follows：

Input message segment a₁,a₂,…,a₄₈, they are stored in register R respectively_1,1,R_1,2,…,R_1,48In；

Register R_1,1,R_1,2,…,R_1,48Ring shift left 1 time simultaneously, XOR gate X_1,1,X_1,2,…,X_1,11Respectively by an exclusive or result left side Move into register R_1,49,R_1,50,…,R_1,59In；

Repeat previous step 127 times, after the completion, register R_1,49,R_1,50,…,R_1,59The content of storage is array section f respectively₁, f₂,…,f₁₁, they constitute vector f and w；

2nd step calculates vector q and x using after I types to iterative circuit；The step of vector q and x is calculated after the I types to iterative circuit It is rapid as follows：

Input vector section f₁, by array section q₁=f₁It is stored in register R_2,1In；

Input vector section f_j, nonzero circle matrix Q_j,kCorresponding array section q_kBy ring shift left s_j,kMulti input mould 2 is sent into behind position to add Musical instruments used in a Buddhist or Taoist mass A_2,jIn with array section f_jCarry out XOR operation, exclusive or result q_jIt is stored into register R_2,jIn, wherein, 2≤j≤11,1≤k <J, 0≤s_j,k<127；

Incrementally change the value of j for step-length with 1, repeat previous step 10 times, finally, register R_2,1,R_2,2,…,R_2,11Point of storage It is not array section q₁,q₂,…,q₁₁, they constitute vectorial q and x；

3rd step uses high-density matrix and the multiplier calculating section verification vector p of vector_x；The high-density matrix and vector Multiplier calculate vector p_xThe step of it is as follows：

Reset register R_3,3,R_3,4, input vector section x₁,x₂, they are stored in register R respectively_3,1,R_3,2In；

Register R_3,1,R_3,2Ring shift left 1 time simultaneously, XOR gate X_3,1,X_3,2Respectively to look-up table L₁,L₂Output and register R_3,3,R_3,4Content carry out exclusive or, exclusive or result is stored back to register R respectively after ring shift left 1 time_3,3,R_3,4；

Repeat previous step 127 times, after the completion, register R_3,3,R_3,4The content of storage is verification section p respectively₁,p₂, they are constituted Part verification vector p_x；

4th step obtains part verification vector p using vector y, y is calculated to iterative circuit after II types with vector q exclusive or_y, so as to To verification vector p=(p_x,p_y)；The step of calculating vector y to iterative circuit after the II types is as follows：

Input validation section p₁,p₂, they are stored in register R respectively_4,10,R_4,11In；

Nonzero circle matrix Y_j,kCorresponding array section p_kOr y_kBy ring shift left s_j,kMulti input modulo 2 adder A is sent into behind position_4,jIn Carry out XOR operation, exclusive or result y_jIt is stored into register R_4,jIn, wherein, 1≤j≤9,1≤k<2+j, 0≤s_j,k<127；

Incrementally change the value of j for step-length with 1, repeat previous step 9 times, finally, register R_4,1,R_4,2,…,R_4,9Point of storage It is not array section y₁,y₂,…,y₉, they constitute vectorial y.