CN106656206A - Two-level full parallel input ring left shift LDPC encoder in CDR - Google Patents

Abstract

The invention provides a QC-LDPC encoder based on a two-level pipeline in a CDR. The encoder includes a sparse matrix and vector multiplier and a vector and high-density matrix multiplier. The sparse matrix and vector multiplier achieves sparse matrix and vector multiplication, and the vector and high-density matrix multiplier achieves vector and high-density matrix multiplication using a full parallel input ring left shift mechanism. The whole encoding process is divided into a two-level pipeline. According to the invention, the 3/4 code rate QC-LDPC encoder in a CDR system has the advantages of simple structure, large throughput and the like.

Description

The LDPC encoder of two grades of full parellel input ring shift lefts in CDR

Technical field

The present invention relates to field of channel coding, two grades of full parellels are input into ring shift left in more particularly to a kind of CDR systems QC-LDPC encoders.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The life of QC-LDPC codes All it is the array being made up of circular matrix into matrix G and check matrix H, the characteristics of with stages cycle, therefore is referred to as QC-LDPC Code.The first trip of circular matrix is the result of footline ring shift right 1, and remaining each row is all the knot of its lastrow ring shift right 1 Really, therefore, circular matrix is characterized completely by its first trip.Generally, the first trip of circular matrix is referred to as its generator polynomial.

Generally using the QC-LDPC codes of system form, the left-half of its generator matrix G is a unit square to communication system Battle array, right half part is by e × c b × b rank circular matrix G_i,j(1≤i≤e,e<J≤t, t=e+c) constitute array, it is as follows It is shown：

Wherein, I is b × b rank unit matrixs, and 0 is b × b rank full null matrix.The continuous b rows of G and b row are known respectively as block Row and block row.From formula (1), G has e blocks row and t blocks row.Information vector a=(a₁,a₂,…,a_e×b).CDR standards are employed A kind of QC-LDPC codes of code check η=3/4, for the code, t=36, e=27, c=9, b=256.

The existing full parellel of 3/4 code check QC-LDPC encoders is input into solution as shown in figure 1, the program in CDR standards Major defect be that modulo 2 adder has e × b input, the time delay of additive operation is long, can cause the operating frequency of encoder Low, handling capacity is little.

The content of the invention

The existing implementation of 3/4 code check QC-LDPC encoders has that operating frequency is low, handling capacity is little in CDR systems Shortcoming, for these technical problems, the invention provides a kind of QC-LDPC encoders based on two-level pipeline.

As shown in Fig. 2 the QC-LDPC encoders in CDR systems based on two-level pipeline are mainly made up of 2 parts：It is sparse Matrix and the multiplier and vector of vector and the multiplier of high-density matrix.2 steps of cataloged procedure point are completed：1st step, using sparse Matrix calculates vector s with the multiplier of vector；2nd step, verification vector p is calculated using vector with the multiplier of high-density matrix.

Can be further understood by following detailed description and accompanying drawings with method with regard to the advantage of the present invention.

Description of the drawings

Fig. 1 is existing full parellel input QC-LDPC encoders；

Fig. 2 is based on the QC-LDPC cataloged procedures of two-level pipeline；

Fig. 3 is the multiplier of sparse matrix and vector；

Fig. 4 is a kind of vector and high-density matrix multiplier that ring shift left is input into based on full parellel.

Specific embodiment

Presently preferred embodiments of the present invention is elaborated below in conjunction with the accompanying drawings, so that advantages and features of the invention can be more It is easy to be readily appreciated by one skilled in the art, apparent clearly defines so as to make to protection scope of the present invention.

The row weight of circular matrix and row heavy phase are same, are denoted as w.If w=0, then the circular matrix is full null matrix.If W=1, then the circular matrix is replaceable, referred to as permutation matrix, and it can be by some positions of unit matrix I ring shift rights Obtain.The check matrix H of QC-LDPC codes is by c × t b × b rank circular matrix H_j,k(1≤j≤c, 1≤k≤t, t=e+c) The following array for constituting：

Under normal circumstances, the arbitrary circular matrix in check matrix H is either full null matrix (w=0) or is displacement square Battle array (w=1).Make circular matrix H_j,kFirst trip h_j,k=(h_j,k,1,h_j,k,2,…,h_j,k,b) it is its generator polynomial, wherein h_j,k,m =0 or 1 (1≤m≤b).Because H is sparse, h_j,kOnly 1 ' 1 ', even without ' 1 '.

It is information vector a that the front e blocks row of H are corresponding, and it is to verify vector p, code word v=(a, p) that rear c blocks row are corresponding.With b Bit is one section, and information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e)；Verification vector p is divided into c sections, i.e. p= (p₁,p₂,…,p_c).The front e blocks row and rear c blocks of H are arranged the matrix for constituting and is denoted as C and D respectively, then

H=[C D] (3)

C is made up of c × e b × b rank circular matrix, and D is made up of c × c b × b rank circular matrix.By formula (3) and Code word v=(a, p) substitutes into Hv^Τ=0, arrangement can be obtained

p^Τ=Φ^ΤCa^Τ (4)

Wherein, Φ^T=D^–1, subscript^TWith^–1Transposition and inverse of a matrix are represented respectively, and D must full rank.It is well known that Cyclic Moment The inverse, product of battle array and remain circular matrix.Therefore, Φ is also the array being made up of circular matrix.But, although matrix D is Sparse, but Φ is generally no longer sparse but highdensity.

Make s^T=Ca^TAnd p^T=Φ^Ts^T, then p=s Φ.The multiplication that s is related to sparse matrix and vector is calculated using C, using Φ Calculate the multiplication that p is related to vector and high-density matrix.From the above discussion, a kind of QC- based on two-level pipeline can be given LDPC cataloged procedures, as shown in Figure 2.

Make s=(s₁,s₂,…,s_c), then s_j ^TIt is the jth block row and a of Matrix C^TProduct, i.e.,

Wherein, 1≤i≤e, 1≤j≤c.s_jThe n-th bit s_j,n(1≤n≤b) is

Wherein, subscript^rs(n–1)With^ls(n–1)Ring shift right n -1 and ring shift left n -1 are represented respectively.Since arbitrary circulation Matrix generator polynomial h_j,iOnly a small amount of ' 1 ' even complete zero, then the inner product in formula (6) can be by posting ring shift left The tap summation of storage realizing, the multiplier of sparse matrix as shown in Figure 3 and vector.Sparse matrix and vectorial multiplier By t b bit register R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition.Depositor R_1,1, R_1,2,…,R_1,eFor loading and ring shift left message segment a₁,a₂,…,a_e, depositor R_1,e+1,R_1,e+2,…,R_1,tFor storing s Array section s₁,s₂,…,s_c.Partially connected in Fig. 3 depends on all circular matrix generator polynomials in Matrix C.If h_j,i,m=1 (1≤m≤b), then message segment a_iM bits be connected to XOR gate X_1,j.Therefore, depositor R_1,iAll take out Head depends on the nonzero element position of all circular matrix generator polynomials in i-th piece of Matrix C row, and multi input XOR gate X_1,jInput depending on all circular matrix generator polynomials in Matrix C jth block row nonzero element position.If in C All circular matrix generator polynomials it is total α ' 1 ', then sparse matrix needs use (α-c) individual with the multiplier of vector Two input XOR gates calculate s simultaneously_1,n,s_2,n,…,s_c,n.S can be calculated within b clock cycle and finished.Using sparse matrix with The step of multiplier of vector calculates vector s is as follows：

1st step, input information section a₁,a₂,…,a_e, they are stored in respectively depositor R_1,1,R_1,2,…,R_1,eIn；

2nd step, depositor R_1,1,R_1,2,…,R_1,eSimultaneously ring shift left 1 time, XOR gate X_1,1,X_1,2,…,X_1,cRespectively will XOR result is moved to left into depositor R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 time, after the completion of, depositor R_1,e+1,R_1,e+2,…,R_1,tThe content of storage be respectively to Amount section s₁,s₂,…,s_c, they constitute vectorial s.

p^T=Φ^Ts^TIt is equivalent to p=s Φ.Φ is by c × c b × b rank circular matrix Φ_j,u(1≤j≤c,1≤u≤c) The array of composition.Make circular matrix Φ_j,uFirst trip g_j,uIt is its generator polynomial.From p=s Φ, u sections verification vector is full Foot

p_u=s₁Φ_1,u+s₂Φ_2,u+…+s_jΦ_j,u+…+s_cΦ_c,u (7)

Make generator polynomial g_j,u=(g_j,u,1,g_j,u,2,…,g_j,u,b), then Φ_j,uCan be considered unit matrix ring shift right version This weighted sum, i.e.,

Φ_j,u=g_j,u,1I^r(0)+g_j,u,2I^r(1)+…+g_j,u,bI^r(b-1) (8)

Wherein, subscript^r()Represent ring shift right.So, jth item on the right of formula (7) equal sign is deployable to be

Since by s_jRing shift right n positions are equivalent to its ring shift left b-n position, i.e.,Wherein, subscript^l()Table Show ring shift left, then formula (9) is rewritable to be

Formula (10) is substituted into into formula (7), arrangement can be obtained

Formula (11) is the process of a-multiply-add-move to left-store, and can derive and a kind of be input into ring shift left based on full parellel Vector and high-density matrix multiplier.Fig. 4 is its functional block diagram, by generator polynomial look-up table, b positions binary multiplier, (c+1) four kinds of functional module compositions of position binary adder and shift register.Generator polynomial look-up table L₁,L₂,…,L_cPoint Do not prestore matrix Φ the 1,2nd ..., all circular matrix generator polynomials in c block rows.Generator polynomial look-up table L₁,L₂,…, L_cThe generator polynomial bit of output respectively with array section s₁,s₂,…,s_cScalar multiplication is carried out, this c scalar multiplication passes through respectively b Position binary multiplier M₁,M₂,…,M_cComplete.B positions binary multiplier M₁,M₂,…,M_cProduct it is interior with shift register R Hold and be added, the addition is by b (c+1) position binary adder A₁,A₂,…,A_bComplete.(c+1) position binary adder A₁, A₂,…,A_bAnd shift register R is stored in by the result after ring shift left 1.

Generator polynomial look-up table L₁,L₂,…,L_cPrestore the circular matrix generator polynomial of matrix Φ.Generator polynomial is looked into Look for table L₁～L_cThe all generator polynomials in 1～c block rows of Φ are stored respectively, for any block row, the 1st are stored successively, 2 ..., c blocks arrange corresponding generator polynomial.Generator polynomial look-up table L₁～L_cThe bit of Serial output generator polynomial.

The step of calculating verification vector p using vector and the multiplier of high-density matrix is as follows：

1st step, full parellel input vector s；

2nd step, resets shift register R；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1st in output matrix Φ u (1≤u≤c) block row, The generator polynomial bit of 2 ..., c block row, these generator polynomial bits pass through respectively b positions binary multiplier M₁,M₂,…, M_cWith message segment s₁,s₂,…,s_cCarry out scalar multiplication, b positions binary multiplier M₁,M₂,…,M_cProduct by b (c+1) positions Binary adder A₁,A₂,…,A_bIt is added with the content of shift register R, (c+1) position binary adder A₁,A₂,…,A_b's Shift register R is stored in by the result after ring shift left 1；

4th step, repeats the 3rd step b-1 time, and now, shift register R storages are verification sections p_u；

5th step, with 1 as step-length the value for changing u is incremented by, and repeats the 2nd～4 step c-1 time, and shift register R is obtained successively Be verification section p₁,p₂,…,p_c, they constitute verification vector p=(p₁,p₂,…,p_c)。

The invention provides a kind of QC-LDPC coded methods based on two-level pipeline, it is adaptable to 3/4 in CDR systems Code check QC-LDPC codes, its coding step is described as follows：

1st step, vector s is calculated using sparse matrix with the multiplier of vector；

2nd step, verification vector p is calculated using vector with the multiplier of high-density matrix.

Existing solution needs 1 e × b positions modulo 2 adder, and the second level circuit of the present invention is average by nodulo-2 addition It is allocated to b (c+1) position modulo 2 adder.For 3/4 code check QC-LDPC encoders in CDR standards, (c+1) it is far smaller than e ×b.It can be seen that, the adder time delay of the present invention is much smaller than existing solution.

As fully visible, for 3/4 code check QC-LDPC encoders in CDR standards, compared with existing solution, the present invention The time delay of logic circuit is highly shortened, has the advantages that operating frequency height, handling capacity are big.

The above, only one of specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, Any those of ordinary skill in the art disclosed herein technical scope in, the change that can be expected without creative work Change or replace, all should be included within the scope of the present invention.Therefore, protection scope of the present invention should be with claims The protection domain for being limited is defined.

Claims (4)

1. the QC-LDPC encoders of two-level pipeline are based in a kind of CDR, and the check matrix H of 3/4 code check QC-LDPC codes is by c The array that × t b × b ranks circular matrix is constituted, wherein, c=9, t=36, b=256, e=t-c=27, check matrix H can draw It is divided into 2 submatrixs, H=[C D], C is made up of c × e b × b rank circular matrix, and D is by c × c b × b rank Cyclic Moment Battle array is constituted, Φ^T=D^–1, wherein, subscript^ΤWith^-1Transposition and inverse, Matrix C corresponding informance vector a are represented respectively, and matrix D correspondence is verified Vectorial p, with b bits as one section, information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e), verification vector p is divided into c Section, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s is divided into c sections, i.e. s=(s₁,s₂,…,s_c), its feature It is that the encoder is included with lower component：

Sparse matrix and vectorial multiplier, by t b bit register R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition, for calculating vectorial s；

Vector and the multiplier of high-density matrix, are input into ring shift left mechanism, by generator polynomial look-up table, b based on full parellel Position binary multiplier, (c+1) position binary adder and shift register composition, for calculating verification vector p, generate multinomial Formula look-up table L₁,L₂,…,L_cPrestore respectively matrix Φ the 1st, 2 ..., all circular matrix generator polynomials in c block rows, generates Multinomial look-up table L₁,L₂,…,L_cThe generator polynomial bit of output respectively with array section s₁,s₂,…,s_cScalar multiplication is carried out, this C scalar multiplication passes through respectively b positions binary multiplier M₁,M₂,…,M_cComplete, b positions binary multiplier M₁,M₂,…,M_c's Product is added with the content of shift register R, and the addition is by b (c+1) position binary adder A₁,A₂,…,A_bComplete, (c + 1) position binary adder A₁,A₂,…,A_bAnd shift register R is stored in by the result after ring shift left 1.

2. the QC-LDPC encoders of two-level pipeline are based in a kind of CDR according to claim 1, it is characterised in that institute State as follows the step of sparse matrix calculates vector s with the multiplier of vector：

1st step, input information section a₁,a₂,…,a_e, they are stored in respectively depositor R_1,1,R_1,2,…,R_1,eIn；

2nd step, depositor R_1,1,R_1,2,…,R_1,eSimultaneously ring shift left 1 time, XOR gate X_1,1,X_1,2,…,X_1,cRespectively by XOR As a result move to left into depositor R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 time, after the completion of, depositor R_1,e+1,R_1,e+2,…,R_1,tThe content of storage is respectively array section s₁,s₂,…,s_c, they constitute vectorial s.

3. the QC-LDPC encoders of two-level pipeline are based in a kind of CDR according to claim 1, it is characterised in that institute State as follows the step of vector calculates verification vector p with the multiplier of high-density matrix：

1st step, full parellel input vector s；

2nd step, resets shift register R；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ u (1≤u≤c) block row ..., The generator polynomial bit of c block rows, these generator polynomial bits pass through respectively b positions binary multiplier M₁,M₂,…,M_cWith letter Breath section s₁,s₂,…,s_cCarry out scalar multiplication, b positions binary multiplier M₁,M₂,…,M_cProduct by b (c+1) positions binary system Adder A₁,A₂,…,A_bIt is added with the content of shift register R, (c+1) position binary adder A₁,A₂,…,A_bAnd followed Ring moves to left the result after 1 and is stored in shift register R；

4th step, repeats the 3rd step b-1 time, and now, shift register R storages are verification sections p_u；

5th step, with 1 as step-length the value for changing u is incremented by, and repeats the 2nd～4 step c-1 time, and what shift register R was obtained successively is Verification section p₁,p₂,…,p_c, they constitute verification vector p=(p₁,p₂,…,p_c)。

4. the QC-LDPC coded methods of two-level pipeline are based in a kind of CDR, and the check matrix H of 3/4 code check QC-LDPC codes is The array being made up of c × t b × b rank circular matrix, wherein, c=9, t=36, b=256, e=t-c=27, check matrix H 2 submatrixs, H=[C D] can be divided into, C is made up of c × e b × b rank circular matrix, and D is followed by c × c b × b rank Ring matrix is constituted, Φ^T=D^–1, wherein, subscript^ΤWith^-1Transposition and inverse, Matrix C corresponding informance vector a, matrix D correspondence are represented respectively Verification vector p, with b bits as one section, information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e), verification vector p by etc. It is divided into c sections, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s is divided into c sections, i.e. s=(s₁,s₂,…,s_c), its It is characterised by, the coded method is comprised the following steps：

1st step, vector s is calculated using sparse matrix with the multiplier of vector；

2nd step, verification vector p is calculated using vector with the multiplier of high-density matrix.