CN103236851A - Quasi-cyclic matrix high-speed multiplier based on look-up table in CMMB (China Mobile Multimedia Broadcasting) - Google Patents

Abstract

The invention provides a quasi-cyclic matrix high-speed multiplier based on a look-up table in CMMB (China Mobile Multimedia Broadcasting), which is used for realizing multiplication of a vector m and a quasi-cyclic matrix F in standard multi-code-rate QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) approximate lower triangular coding of CMMB. The multiplier comprises five product look-up tables, five 256-bit binary adders and five 256-bit shifting registers, wherein the five product look-up tables are used for prestoring possible algebraic sum of all generator polynomials on a two-element field in block rows of all of the code-rate matrices F, the five 256-bit binary adders are used for outputting the product look-up tables and performing modulo-2 adding on the contents of the shifting registers, and the five 256-bit shifting registers are used for storing the sum of one bit by cyclic shift to the left. The quasi-cyclic matrix high-speed multiplier provided by the invention is compatible with all code rates, a memory and a logical resource are reduced, and the quasi-cyclic matrix high-speed multiplier has the advantages of simple structure, less power consumption, low cost and the like.

Description

Accurate circular matrix high-speed gear among the CMMB based on look-up table

Technical field

The present invention relates to field of channel coding, particularly the accurate circular matrix high-speed gear in a kind of CMMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) sign indicating number is one of channel coding technology efficiently, and QC-LDPC(Quasic-LDPC, QC-LDPC) sign indicating number is a kind of special LDPC sign indicating number.Generator matrix G and the check matrix H of QC-LDPC sign indicating number all are the arrays that is made of circular matrix, have the characteristics of segmentation circulation, so be called as the QC-LDPC sign indicating number.The first trip of circular matrix is the result of 1 of footline ring shift right, and all the other each provisional capitals are results of 1 of its lastrow ring shift right, and therefore, circular matrix is characterized by its first trip fully.Usually, the first trip of circular matrix is called as its generator polynomial.

When adopting the near lower triangular coding method that the QC-LDPC sign indicating number is encoded, by the ranks exchange, check matrix H is transformed near lower triangular shape H _ALT, it is composed as follows by 6 sub-matrixes:

$H_{\mathrm{ALT}}=\begin{array}{c}\left[\begin{array}{ccc}A& B& L\\ C& D& E\end{array}\right]\end{array}---\left(1\right)$

Wherein, L is lower triangular matrix.H _ALTCorresponding code word v _ALT=(s, p, q), and matrix A and C corresponding informance vector s, the corresponding a part of verification vector of matrix B and D p, matrix L and E be corresponding remaining verification vector q then.The method of calculating section verification vector p is as follows:

P=s (C+EL ^-1A) ^Τ((D+EL ^-1B) ^-1) ^Τ(2) wherein, subscript ^-1With ^ΤRepresent respectively matrix inversion and transposition.Order

m＝s(C+EL ^-1A) ^Τ (3)

F＝((D+EL ^-1B) ^-1) ^Τ (4)

Then vectorial m and matrix F satisfy following relation:

p＝mF (5)

Matrix F is by following u * u b * b rank circular matrix F _{I, j}(0≤i＜u, the accurate circular matrix that 0≤j＜u) constitutes:

Capable and the b of the continuous b of F row are called as the capable and piece row of piece respectively.By formula (6) as can be known, F has the capable and u piece row of u piece.Make f _{I, j}Be circular matrix F _{I, j}Generator polynomial, they have constituted following generator polynomial matrix f

Make f _jBe all the circular matrix generator polynomials formations by generator polynomial matrix f j row in the formula (7).

Make vectorial m=(e ₀, e ₁..., e _{U * b-1}), part verification vector p=(d ₀, d ₁..., d _{U * b-1}).Be one section with the b bit, vectorial m and part verification vector p all are divided into the u section, i.e. m=(m ₀, m ₁..., m _U-1) and p=(p ₀, p ₁..., p _U-1).By formula (5) as can be known, the j section p of part verification vector _jSatisfy

p _j＝m ₀F _0,j+m ₁F _1,j+…+m _iF _i,j+…+m _u-1F _u-1,j (8)

Wherein, 0≤i＜u, 0≤j＜u.Order

With

Be respectively generator polynomial f _{I, j}The result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.So, the i item on formula (8) equal sign the right is deployable is

$m_i{F}_{i,j}=e_{i\×b}{f}_{i,j}^{r\left(0\right)}+e_{i\×b+1}{f}_{i,j}^{r\left(1\right)}+...+e_{i\×b+b-1}{f}_{i,j}^{r(b-1)}---\left(9\right)$

For the multiplication of vector in the quick realization formula (5) with accurate circular matrix, at present extensively employing be based on u ²Individual I type shift register adds accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) scheme of circuit.Fig. 1 is the functional block diagram of single SRAA-I circuit.When calculating m with the SRAA-I circuit _iF _{I, j}(when 0≤i＜u, 0≤j＜u), array section m _iThis circuit is sent in serial by turn, and the generator polynomial look-up table is stored the generator polynomial f that generator polynomial matrix i is capable, j is listed as in advance _{I, j}, accumulator is cleared initialization.When the 0th clock cycle arrived, shift register loaded generator polynomial from the generator polynomial look-up table

, bit e _{I * b}Move into circuit, and with the content of shift register

Carry out scalar and take advantage of product

Add with content 0 mould 2 of accumulator and

Deposit back accumulator.When the 1st clock cycle arrives, 1 of shift register ring shift right, content becomes

, bit e _{I * b+1}Move into circuit, and with the content of shift register Carry out scalar and take advantage of product

Content with accumulator

Mould 2 add and

Deposit back accumulator.Above-mentioned moving to right-take advantage of-Jia-storing process is proceeded down.When b-1 clock cycle finishes, bit e _{I * b+b-1}Moved into circuit, that cumulative adder stores is part and m at this moment _iF _{I, j}, this is array section m _iTo p _jContribution.

Use u ²Individual SRAA-I circuit can constitute a kind of accurate circular matrix high-speed gear, and it obtains u verification section simultaneously in b clock cycle.U SRAA-I circuit shared 1 accumulator, so u ²Individual SRAA-I circuit needs u accumulator altogether.This scheme needs u * (u+1) * b register, u ²* b two inputs and door and u ²* b two input XOR gate also need u ²The generator polynomial of individual b bit ROM storage circular matrix.

The CMMB standard has adopted code check η=0.5 and 0.75 two kind of QC-LDPC sign indicating number, and b=256 is all arranged.Be respectively 5 and 3 for code check η=0.5 and 0.75, u.

Be compatible 2 kinds of code checks, the existing solution of accurate circular matrix high-speed multiplication is based on 25 SRAA-I circuit in the CMMB standard QC-LDPC near lower triangular coding, need 7680 registers, 6400 two inputs and door and 6400 two input XOR gate, also need the ROM of 9 512 bits to store the 0th～2 row of 2 kinds of code check generator polynomial matrix f, 9 circular matrix generator polynomials of the 0th～2 row respectively, all the other 16 the circular matrix generator polynomials among the ROM storage η=0.5 code check f of 16 256 bits.The shortcoming of this scheme is that register quantity is big, needs to finish multiplying with door in a large number and finishes add operation with a large amount of XOR gate, and too many little ROM can waste memory resource, and these all can cause the power consumption of circuit big, cost is high.

Summary of the invention

There is the shortcoming that power consumption is big, cost is high in the existing implementation of accurate circular matrix high-speed multiplication in the CMMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding, at these technical problems, the invention provides a kind of accurate circular matrix high-speed gear based on look-up table.

As shown in Figure 3, the accurate circular matrix high-speed gear in the CMMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding mainly is made up of 3 parts: product look-up table, b position binary adder and shift register.Multiplication process divided for 3 steps finished: the 1st step, zero clearing shift register R ₀, R ₁..., R ₄The 2nd step, the data segment z of input vector m _k, product look-up table L ₀, L ₁..., L ₄According to code check η with z _kFor z exported respectively in index _kf ₀, z _kf ₁..., z _kf ₄Product, product look-up table L ₀, L ₁..., L ₄Output respectively by b position binary adder A ₀, A ₁..., A ₄With shift register R ₀, R ₁..., R ₄The content addition, b position binary adder A ₀, A ₁..., A ₄And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R ₄The 3rd step was that step-length increases progressively the value that changes k with 1, repeated the 2nd and went on foot b time, finish up to whole vectorial m input, at this moment, shift register R ₀, R ₁..., R _U-1That store is respectively verification section p ₀, p ₁..., p _U-1, they have constituted part verification vector p=(p ₀, p ₁..., p _U-1).

Accurate circular matrix high-speed gear provided by the invention is simple in structure, and the QC-LDPC sign indicating number of all code checks has reduced memory and logical resource in the compatible CMMB standard, has reduced power consumption, has saved cost.

Can be further understood by following detailed description and accompanying drawings about advantage of the present invention and method.

Description of drawings

Fig. 1 is the functional block diagram that I type shift register adds accumulator SRAA-I circuit;

Fig. 2 searches the functional block diagram that adds shift register LASR circuit;

Fig. 3 is a kind of accurate circular matrix high-speed gear based on look-up table that is made of 5 LASR circuit.

Embodiment

Below in conjunction with accompanying drawing preferred embodiment of the present invention is elaborated, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that protection scope of the present invention is made more explicit defining.

Since the generator polynomial f with circular matrix _{I, j}Ring shift right n position is equivalent to its ring shift left b-n position, namely , formula (9) can be rewritten as so

$m_i{F}_{i,j}=e_{i\×b}{f}_{i,j}^{l\left(b\right)}+e_{i\×b+1}{f}_{i,j}^{l(b-1)}+...+e_{i\×b+b-1}{f}_{i,j}^{l\left(1\right)}$

$={\left(e_{i\×b}{f}_{i,j}\right)}^{l\left(b\right)}+{\left(e_{i\×b+1}{f}_{i,j}\right)}^{l(b-1)}+...+{\left(e_{i\×b+b-1}{f}_{i,j}\right)}^{l\left(1\right)}$

$={(0+e_{i\×b}{f}_{i,j})}^{l\left(b\right)}+{\left(e_{i\×b+1}{f}_{i,j}\right)}^{l(b-1)}+...+{\left(e_{i\×b+b-1}{f}_{i,j}\right)}^{l\left(1\right)}---\left(10\right)$

$={({(0+e_{i\×b}{f}_{i,j})}^{l\left(1\right)}+e_{i\×b+1}{f}_{i,j})}^{l(b-1)}+...+{\left(e_{i\×b+b-1}{f}_{i,j}\right)}^{l\left(\text{1}\right)}$

$={(...{({(0+e_{i\×b}{f}_{i,j})}^{l\left(1\right)}+e_{i\×b+1}{f}_{i,j})}^{l\left(1\right)}+...+e_{i\×b+b-1}{f}_{i,j})}^{l\left(1\right)}$

With formula (10) substitution formula (8), can get

$p_j={(...{({(0+\underset{i=0}{\overset{u-1}{\mathrm{\Σ}}}{e}_{i\×b}{f}_{i,j})}^{l\left(1\right)}+\underset{i=0}{\overset{u-1}{\mathrm{\Σ}}}{e}_{i\×b+1}{f}_{i,j})}^{l\left(1\right)}+...+\underset{i=0}{\overset{u-1}{\mathrm{\Σ}}}{e}_{i\×b+b-1}{f}_{i,j})}^{l\left(1\right)}---\left(11\right)$

Make the data segment z of vectorial m _k=(e _k, e _B+k..., e _{(u-1) * b+k}), wherein, 0≤k＜b, and f _jBe that then formula (11) can be rewritten as by all circular matrix generator polynomials formations of generator polynomial matrix f j row in the formula (7)

p _j＝(…((0+z ₀f _j) ^l(1)+z ₁f _j) ^l(1)+…+z _b-1f _j) ^l(1) (12)

In following formula, z _kBe at random, f _jBe constant, z _kf _jProduct depend on z fully _kU bit random data, so have 2 ^uPlanting may.z _kf _jAvailable one in advance the possible product of storage institute 2 ^u* b bit look-up table is finished, and its index is the z of u bit _k, its output is the z of b bit _kf _j

Formula (12) is one to be taken advantage of-process of Jia-move to left-store, and its realization adds shift register (Lookup-Adder-Shift-Register, LASR) circuit with searching.Fig. 2 is the functional block diagram of LASR circuit, and vectorial m is sent into this circuit by the u parallel-by-bit.When using LASR circuit calculation check section p _j(during 0≤j＜u), the product look-up table is stored generator polynomial matrix j row f in advance _jThe possible algebraical sum of all generator polynomials on two element field, shift register is cleared initialization.When the 0th clock cycle arrives, the data segment z of vectorial m ₀Move into circuit, the product look-up table is with z ₀Be index output z ₀f _jProduct, the output of product look-up table and the content of shift register 0 mould 2 add, and z ₀f _jResult (the 0+z that ring shift left is 1 ₀f _j) ^{L (1)}Deposit the travelling backwards bit register.When the 1st clock cycle arrives, the data segment z of vectorial m ₁Move into circuit, the product look-up table is with z ₁Be index output z ₁f _jProduct, the content (0+z of the output of product look-up table and shift register ₀f _j) ^{L (1)}Mould 2 adds and (0+z ₀f _j) ^{L (1)}+ z ₁f _jThe result ((0+z that ring shift left is 1 ₀f _j) ^{L (1)}+ z ₁f _j) ^{L (1)}Deposit the travelling backwards bit register.Above-mentioned taking advantage of-Jia-move to left-storing process is proceeded down.When b-1 clock cycle finishes, the final data section z of vectorial m _B-1Moved into circuit, that this moment, shift register was stored is verification section p _jA LASR circuit is obtained verification section p in b clock cycle _j, need b two input XOR gate, a b register and 2 ^u* b bit ROM.

Fig. 3 has provided a kind of accurate circular matrix high-speed gear based on look-up table that is made of 5 LASR circuit, is made up of product look-up table, b position binary adder and three kinds of functional modules of shift register.Product look-up table L ₀, L ₁..., L ₄All code check generator polynomial matrix the 0th row f prestore respectively ₀, the 1st row f ₁..., the 4th row f ₄The possible algebraical sum of all generator polynomials on two element field.Product look-up table L ₀, L ₁..., L ₄Output respectively with shift register R ₀, R ₁..., R ₄The content addition, these 5 nodulo-2 additions are respectively by b position binary adder A ₀, A ₁..., A ₄Finish.B position binary adder A ₀, A ₁..., A ₄And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R ₄

Product look-up table L ₀, L ₁..., L ₄Store the possible algebraical sum of all generator polynomials on two element field in the accurate circular matrix F of all code checks piece row.Product look-up table L ₀～L ₂Store two kinds of code check generator polynomial matrixes the 0th～2 row f respectively ₀～f ₂The possible algebraical sum of all generator polynomials on two element field.Product look-up table L ₃, L ₄Store η=0.5 code check generator polynomial matrix the 3rd row f respectively ₃, the 4th row f ₄The possible algebraical sum of all generator polynomials on two element field.

The invention provides a kind of accurate circular matrix high-speed multiplication based on look-up table, 2 kinds of code check QC-LDPC sign indicating numbers in its compatible CMMB standard, its multiplication step is described below:

The 1st step, zero clearing shift register R ₀, R ₁..., R ₄

The 2nd step, the data segment z of input vector m _k, product look-up table L ₀, L ₁..., L ₄According to code check η with z _kFor z exported respectively in index _kf ₀, z _kf ₁..., z _kf ₄Product, product look-up table L ₀, L ₁..., L ₄Output respectively by b position binary adder A ₀, A ₁..., A ₄With shift register R ₀, R ₁..., R ₄The content addition, b position binary adder A ₀, A ₁..., A ₄And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R ₄

The 3rd step was that step-length increases progressively the value that changes k with 1, repeated the 2nd and went on foot b time, finish up to whole vectorial m input, at this moment, shift register R ₀, R ₁..., R _U-1That store is respectively verification section p ₀, p ₁..., p _U-1, they have constituted part verification vector p=(p ₀, p ₁..., p _U-1).

Be not difficult to find out that from above step whole computational process needs b clock cycle altogether, identical with existing multiplication scheme based on 25 SRAA-I circuit.

The existing solution of accurate circular matrix high-speed multiplication needs the ROM of 9 512 bits and the ROM of 16 256 bits in the CMMB standard, and the present invention needs the ROM of 3 10240 bits and the ROM of 2 8192 bits.In a word, existing solution has been used 25 trifling little ROM, and the present invention has used the big ROM of 5 compactnesses.As everyone knows, when realizing ROM with the memory in the FPGA sheet, can cause the waste of memory inevitably, the more many wastes of ROM number are more serious.Therefore, the actual memory that expends of the present invention will be less than existing solution usually.

The existing solution of accurate circular matrix high-speed multiplication needs 7680 registers, 6400 two inputs and door and 6400 two input XOR gate in the CMMB standard, and the present invention needs 1280 registers, 0 two input and door and 1280 two input XOR gate.As seen, the present invention need not and door, and the register that expends and XOR gate are respectively 16.7% and 20% of existing solutions.

As fully visible, for the accurate circular matrix high-speed multiplication in the CMMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding, compare with existing solution, the present invention has kept identical speed, used less memory, saved a large amount of logical resources, have simple in structure, power consumption is little, low cost and other advantages.

The above; it only is one of the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; variation or the replacement that can expect without creative work all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claims were limited.

Claims (4)

1. accurate circular matrix high-speed gear among the CMMB based on look-up table, when adopting the near lower triangular coding method that CMMB standard multi code Rate of Chinese character QC-LDPC sign indicating number is encoded, relate to the multiplying of vectorial m and accurate circular matrix F, matrix F is divided into the capable and u piece row of u piece, is by u * u b * b rank circular matrix F _{I, j}The array that constitutes, f _{I, j}Be circular matrix F _{I, j}Generator polynomial, u * u f _{I, j}Constituted generator polynomial matrix f, all circular matrix generator polynomials of f j row have constituted f _j, wherein, b, i, j and u are nonnegative integer, 0≤i＜u, 0≤j＜u, the CMMB standard has adopted the QC-LDPC sign indicating number of 2 kinds of different code check η, and η is respectively 0.5,0.75, for these 2 kinds different code check QC-LDPC sign indicating numbers, b=256 is all arranged, and 2 kinds of different code check corresponding parameters u are respectively 5,3, are one section with continuous b bit, part verification vector p is divided into the u section, i.e. p=(p ₀, p ₁..., p _U-1), vectorial m=(e ₀, e ₁..., e _{U * b-1}), be step-length with the b bit, the uniformly-spaced bit of vectorial m has constituted data segment z _k=(e _k, e _B+k..., e _{(u-1) * b+k}), wherein, 0≤k＜b is characterized in that, described multiplier comprises with lower member:

Product look-up table L ₀, L ₁..., L ₄, all code check generator polynomial matrix the 0th row f prestore respectively ₀, the 1st row f ₁..., the 4th row f ₄The possible algebraical sum of all generator polynomials on two element field, their index all is vectorial m data segment z _kU bit random data, output be respectively z _kf ₀, z _kf ₁..., z _kf ₄B bit product;

B position binary adder A ₀, A ₁..., A ₄, respectively to product look-up table L ₀, L ₁..., L ₄Output and shift register R ₀, R ₁..., R ₄Content carry out mould 2 and add;

Shift register R ₀, R ₁..., R ₄, store b position binary adder A respectively ₀, A ₁..., A ₄And be recycled the result that moves to left after 1 and final verification section p ₀, p ₁..., p ₄

2. accurate circular matrix high-speed gear among a kind of CMMB based on look-up table according to claim 1 is characterized in that, described product look-up table L ₀～L ₂Store two kinds of code check generator polynomial matrixes the 0th～2 row f respectively ₀～f ₂The possible algebraical sum of all generator polynomials on two element field.

3. accurate circular matrix high-speed gear among a kind of CMMB based on look-up table according to claim 1 is characterized in that, described product look-up table L ₃, L ₄Store η=0.5 code check generator polynomial matrix the 3rd row f respectively ₃, the 4th row f ₄The possible algebraical sum of all generator polynomials on two element field.

4. accurate circular matrix high-speed multiplication method among the CMMB based on look-up table, when adopting the near lower triangular coding method that CMMB standard multi code Rate of Chinese character QC-LDPC sign indicating number is encoded, relate to the multiplying of vectorial m and accurate circular matrix F, matrix F is divided into the capable and u piece row of u piece, is by u * u b * b rank circular matrix F _{I, j}The array that constitutes, f _{I, j}Be circular matrix F _{I, j}Generator polynomial, u * u f _{I, j}Constituted generator polynomial matrix f, all circular matrix generator polynomials of f j row have constituted f _j, wherein, b, i, j and u are nonnegative integer, 0≤i＜u, 0≤j＜u, the CMMB standard has adopted the QC-LDPC sign indicating number of 2 kinds of different code check η, and η is respectively 0.5,0.75, for these 2 kinds different code check QC-LDPC sign indicating numbers, b=256 is all arranged, and 2 kinds of different code check corresponding parameters u are respectively 5,3, are one section with continuous b bit, part verification vector p is divided into the u section, i.e. p=(p ₀, p ₁..., p _U-1), vectorial m=(e ₀, e ₁..., e _{U * b-1}), be step-length with the b bit, the uniformly-spaced bit of vectorial m has constituted data segment z _k=(e _k, e _B+k..., e _{(u-1) * b+k}), wherein, 0≤k＜b is characterized in that, described multiplication method may further comprise the steps:

The 1st step, zero clearing shift register R ₀, R ₁..., R ₄

The 2nd step, the data segment z of u parallel-by-bit input vector m _k, product look-up table L ₀, L ₁..., L ₄According to code check η with z _kFor z exported respectively in index _kf ₀, z _kf ₁..., z _kf ₄Product, product look-up table L ₀, L ₁..., L ₄Output respectively by b position binary adder A ₀, A ₁..., A ₄With shift register R ₀, R ₁..., R ₄The content addition, b position binary adder A ₀, A ₁..., A ₄And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R ₄

The 3rd step was that step-length increases progressively the value that changes k with 1, repeated the 2nd and went on foot b time, finish up to whole vectorial m input, at this moment, shift register R ₀, R ₁..., R _U-1That store is respectively verification section p ₀, p ₁..., p _U-1, they have constituted part verification vector p=(p ₀, p ₁..., p _U-1).

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