CN103236859A - Quasi-cyclic LDPC (low-density parity-check) serial encoder based on shared storage mechanism - Google Patents

Abstract

The invention provides a quasi-cyclic LDPC (low-density parity-check) serial encoder based on a shared storage mechanism. The encoder comprises a generation polynomial finding list, a c-bit delayer, c b-bit buffers, c b-bit binary multipliers, c b-bit binary adders, and c b-bit shift registers, wherein the generation polynomial finding list is used for prestoring all cyclic matrix generation polynomials in a generation matrix, the c-bit delay is used for slidingly storing information bytes, the c b-bit buffers are used for buffering the generation polynomials, the c b-bit binary multipliers are used for multiplying information bytes and the generation polynomials, the c b-bit binary adders are used for carrying out modulo-2 adding on the products and the contents of the shift registers, the c b-bit shift registers are used for storing the sum of the cycled and left-shifted one bit, and finally, the verification data is stored in the c b-bit shift registers. The serial encoder has the advantages that the power consumption is little, the structure is simple, the consumption of the memory is little, the cost is low, and the like.

Description

Share the quasi-cyclic LDPC serial encoder of memory mechanism

Technical field

The present invention relates to field of channel coding, particularly the serial encoder of quasi-cyclic LDPC code in a kind of communication system.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) sign indicating number is one of channel coding technology efficiently, and quasi-cyclic LDPC (Quasic-LDPC, QC-LDPC) sign indicating number is a kind of special LDPC sign indicating number.Generator matrix G and the check matrix H of QC-LDPC sign indicating number all are the arrays that is made of circular matrix, have the characteristics of segmentation circulation, so be called as quasi-cyclic LDPC code.The first trip of circular matrix is the result of 1 of footline ring shift right, and all the other each provisional capitals are results of 1 of its lastrow ring shift right, and therefore, circular matrix is characterized by its first trip fully.Usually, the first trip of circular matrix is called as its generator polynomial.

Communication system adopts the QC-LDPC sign indicating number of system form usually, and the left-half of its generator matrix G is a unit matrix, and right half part is by a * c b * b rank circular matrix G _{I, j}(0≤i＜a, a≤j＜t, the t=a+c) array of Gou Chenging, as follows:

Wherein, I is b * b rank unit matrix, the 0th, the b * full null matrix in b rank.Capable and the b of the continuous b of G row are called as the capable and piece row of piece respectively.By formula (1) as can be known, G has the capable and t piece row of a piece.Make g _{I, j}Be circular matrix G _{I, j}Generator polynomial.

(s, p), that the preceding a piece row of G are corresponding is information vector s=(e to the corresponding code word v=of generator matrix G ₀, e ₁..., e _{A * b-1}), that back c piece row are corresponding is verification vector p=(d ₀, d ₁..., d _{C * b-1}).Be one section with the b bit, information vector s is divided into a section, i.e. s=(s ₀, s ₁..., s _A-1); Verification vector p is divided into the c section, i.e. p=(p ₀, p ₁..., p _C-1).By v=sG as can be known, j-a section verification vector satisfies

p _j-a＝s ₀G _0,j+s ₁G _1,j+…+s _iG _i,j+…+s _a-1G _a-1,j (c)

Wherein, 0≤i＜a, a≤j＜t, t=a+c.Order

With

Be respectively generator polynomial g _{I, j}The result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.So, the i item on formula (c) equal sign the right is deployable is

$s_i{G}_{i,j}=e_{i\×b}{g}_{i,j}^{r\left(0\right)}+e_{i\×b+1}{g}_{i,j}^{r\left(1\right)}+\·\·\·+e_{i\×b+b-1}{g}_{i,j}^{r(b-1)}---\left(3\right)$

At present, extensive c the I type shift register that be based on that adopts of QC-LDPC serial code adds accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) scheme of circuit.Fig. 1 is the functional block diagram of single SRAA-I circuit, and information vector s serial by turn sends into this circuit.When using the SRAA-I circuit to verification section p _J-a(a≤j＜when t) encoding, the generator polynomial look-up table is stored all generator polynomials of the j piece row of generator matrix G in advance, and accumulator is cleared initialization.When the 0th clock cycle arrived, shift register loaded the 0th row of G, the generator polynomial of j piece row from the generator polynomial look-up table

Information bit e ₀Move into circuit, and with the content of shift register

Carry out scalar and take advantage of product

Add with content 0 mould 2 of accumulator and

Deposit back accumulator.When the 1st clock cycle arrives, 1 of shift register ring shift right, content becomes

Information bit e ₁Move into circuit, and with the content of shift register

Carry out scalar and take advantage of product

Content with accumulator Mould 2 add and

Deposit back accumulator.Above-mentioned moving to right-take advantage of-Jia-storing process is proceeded down.When b-1 clock cycle finishes, information bit e _B-1Moved into circuit, that cumulative adder stores is part and s at this moment ₀G _{0, j}, this is message segment s ₀To p _J-aContribution.When b clock cycle arrived, shift register loaded the 1st row of G, the generator polynomial of j piece row from the generator polynomial look-up table

Repeat above-mentioned moving to right-take advantage of-Jia-storing process.As message segment s ₁When moving into circuit fully, cumulative adder stores be the part and s ₀G _{0, j}+ s ₁G _{1, j}Repeat said process, move into circuit up to the whole serials of whole information vector s.At this moment, that cumulative adder stores is verification section p _J-aUse c SRAA-I circuit can constitute serial encoder shown in Figure 2, it obtains c verification section simultaneously in a * b clock cycle.This scheme needs 2 * c * b register, c * b two input and door and c * b two input XOR gate, also needs the generator polynomial of c a * b bit ROM storage circular matrix.

The existing solution of QC-LDPC serial code is based on c SRAA-I circuit in the communication system, this scheme has two shortcomings: the one, and shift register is in each clock cycle or load new generator polynomial, 1 of ring shift right, cause the memory contents of single register constantly to change, and then cause the power consumption of circuit big; The 2nd, the generator polynomial of circular matrix is dispersed among a plurality of ROM, as everyone knows, when realizing ROM with the memory in the FPGA sheet, can cause the waste of memory inevitably, the more many wastes of ROM number are more serious, certainly will cause the memory of circuit big, cost is high.

Summary of the invention

The existing implementation of QC-LDPC serial code exists power consumption height, memory is big, cost is high shortcoming in the communication system, at these technical problems, the invention provides a kind of based on the serial encoder of sharing memory mechanism.

As shown in Figure 4, the serial encoder of QC-LDPC sign indicating number mainly is made up of 6 parts in the communication system: generator polynomial look-up table, buffer, b position binary multiplier, b position binary adder, shift register and delayer.Cataloged procedure divided for 5 steps finished: the 1st step, zero clearing delayer D and shift register R ₀, R ₁..., R _C-1, buffer B _J-aWhen arriving, the i * b+j-a clock cycle load the generator polynomial g that generator matrix G i piece is capable, the j piece is listed as from the generator polynomial look-up table _{I, j}, and remain unchanged constantly at other; The 2nd step, when k clock cycle arrives, delayer D input information bits e _k(0≤k＜a * b), buffer B ₀, B ₁..., B _C-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _C-1With the data bit D among the delayer D ₀, D ₁..., D _C-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _C-1Product respectively by b position binary adder A ₀, A ₁..., A _C-1With shift register R ₀, R ₁..., R _C-1The content addition, b position binary adder A ₀, A ₁..., A _C-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _C-1The 3rd step be that step-length increases progressively the value that changes k with 1, repeated the 2nd step a * b time, imported up to whole information vector s to finish; In the 4th step, when the clock cycle arrived, delayer D imported filling bit 0, buffer B ₀, B ₁..., B _C-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _C-1With the data bit D among the delayer D ₀, D ₁..., D _C-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _C-1Product respectively by b position binary adder A ₀, A ₁..., A _C-1With shift register R ₀, R ₁..., R _C-1The content addition, b position binary adder A ₀, A ₁..., A _C-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _C-1The 5th step repeated the 4th and goes on foot c time, finishes up to 0 input of c filling bit, at this moment, shift register R ₀, R ₁..., R _C-1That store is respectively verification section p ₀, p ₁..., p _C-1, they have constituted verification vector p=(p ₀, p ₁..., p _C-1).

Serial encoder provided by the invention is simple in structure, can keep coding rate and logical resource to expend under the constant condition basically, reduces power consumption, reduces storage requirement, saves cost.

Can be further understood by following detailed description and accompanying drawings about advantage of the present invention and method.

Description of drawings

Fig. 1 is the functional block diagram that I type shift register adds accumulator SRAA-I circuit;

Fig. 2 is the QC-LDPC serial encoder that is made of c SRAA-I circuit;

Fig. 3 is the functional block diagram that buffer adds shift register BASR circuit;

Fig. 4 is a kind of QC-LDPC serial encoder based on shared memory mechanism that is made of c BASR circuit.

Embodiment

Below in conjunction with accompanying drawing preferred embodiment of the present invention is elaborated, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that protection scope of the present invention is made more explicit defining.

Since the generator polynomial g with circular matrix _{I, j}Ring shift right n position is equivalent to its ring shift left b-n position, namely $g_{i,j}^{r\left(n\right)}=g_{i,j}^{l(b-n)},$ Formula (3) can be rewritten as so

$s_i{G}_{i,j}=e_{i\×b}{g}_{i,j}^{l\left(b\right)}+e_{i\×b+1}{g}_{i,j}^{l(b-1)}+\·\·\·+e_{i\×b+b-1}{g}_{i,j}^{l\left(1\right)}$

$={\left(e_{i\×b}{g}_{i,j}\right)}^{l\left(b\right)}+{\left(e_{i\×b+1}{g}_{i,j}\right)}^{l(b-1)}+\·\·\·+{\left(e_{i\×b+b-1}{g}_{i,j}\right)}^{l\left(1\right)}$

$={(0+e_{i\×b}{g}_{i,j})}^{l\left(b\right)}+{\left(e_{i\×b+1}{g}_{i,j}\right)}^{l(b-1)}+\·\·\·+{\left(e_{i\×b+b-1}{g}_{i,j}\right)}^{l\left(1\right)}---\left(4\right)$

$={({(0+e_{i\×b}{g}_{i,j})}^{l\left(1\right)}+e_{i\×b+1}{g}_{i,j})}^{l(b-1)}+\·\·\·+{\left(e_{i\×b+b-1}{g}_{i,j}\right)}^{l\left(1\right)}$

$={(\·\·\·{({(0+e_{i\×b}{g}_{i,j})}^{l\left(1\right)}+e_{i\×b+1}{g}_{i,j})}^{l\left(1\right)}+\·\·\·+e_{i\×b+b-1}{g}_{i,j})}^{l\left(1\right)}$

Formula (4) is one to be taken advantage of-process of Jia-move to left-store, and its realization adds shift register (Buffer-Adder-Shift-Register, BASR) circuit with buffer.Fig. 3 is the functional block diagram of BASR circuit, and information vector s is sent into this circuit by serial by turn.When using the BASR circuit to verification section p _J-a(0≤j＜when c) encoding, the generator polynomial look-up table is stored all generator polynomials of the j piece row of generator matrix G in advance, and shift register is cleared initialization.When the 0th clock cycle arrived, buffer loaded the 0th row of G, the generator polynomial g of j piece row from the generator polynomial look-up table _{0, j}, information bit e ₀Move into circuit, and with the content g of buffer _{0, j}Carry out scalar and take advantage of, product e ₀g _{0, j}Add with content 0 mould 2 of shift register, and e ₀g _{0, j}Result (the 0+e that ring shift left is 1 ₀g _{0, j}) ^{L (1)}Deposit the travelling backwards bit register.When the 1st clock cycle arrived, the content of buffer remained unchanged, information bit e ₁Move into circuit, and with the content g of buffer _{0, j}Carry out scalar and take advantage of, product e ₁g _{0, j}Content (0+e with shift register ₀g _{0, j}) ^{L (1)}Mould 2 adds and (0+e ₀g _{0, j}) ^{L (1)}+ e ₁g _{0, j}The result ((0+e that ring shift left is 1 ₀g _{0, j}) ^{L (1)}+ e ₁g _{0, j}) ^{L (1)}Deposit the travelling backwards bit register.Above-mentioned taking advantage of-Jia-move to left-storing process is proceeded down.When b-1 clock cycle finishes, information bit e _B-1Moved into circuit, that this moment, shift register was stored is part and s ₀G _{0, j}, this is message segment s ₀To p _J-aContribution.When b clock cycle arrived, buffer loaded the 1st row of G, the generator polynomial g of j piece row from the generator polynomial look-up table _{1, j}, repeat above-mentioned taking advantage of-Jia-move to left-storing process.As message segment s ₁When moving into circuit fully, that shift register is stored is part and s ₀G _{0, j}+ s ₁G _{1, j}Repeat said process, move into circuit up to the whole serials of whole information vector s.At this moment, that the shift register storage is verification section p _J-a

Fig. 4 has provided a kind of QC-LDPC serial encoder based on shared memory mechanism that is made of c BASR circuit, is made up of generator polynomial look-up table, buffer, b position binary multiplier, b position binary adder, shift register and six kinds of functional modules of delayer.The generator polynomial look-up table is used for the generator polynomial of all circular matrixes of storage, and c BASR circuit shared this look-up table, and generator polynomial is therefrom read in timesharing.Buffer B ₀, B ₁..., B _C-1Difference buffer memory a, a+1 ..., the generator polynomial of circular matrix in the t-1 piece row.Buffer B ₀, B ₁..., B _C-1In generator polynomial respectively with delayer D in data bit D ₀, D ₁..., D _C-1Carry out scalar and take advantage of, this c scalar multiplication is respectively by b position binary multiplier M ₀, M ₁..., M _C-1Finish.B position binary multiplier M ₀, M ₁..., M _C-1Product respectively with shift register R ₀, R ₁..., R _C-1The content addition, this c nodulo-2 addition is respectively by b position binary adder A ₀, A ₁..., A _C-1Finish.B position binary adder A ₀, A ₁..., A _C-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _C-1Data bit D among the delayer D ₀～D _C-1Storage c bit information slides.

All circular matrix generator polynomials in the generator polynomial look-up table stores QC-LDPC sign indicating number generator matrix are stored earlier a in the 0th row, a+1 successively,, the corresponding generator polynomial of t-1 piece row is stored a in the 1st row more successively, a+1,, the corresponding generator polynomial of t-1 piece row, the rest may be inferred, store successively at last the a-1 piece capable in a, a+1 ..., the corresponding generator polynomial of t-1 piece row.

The invention provides a kind of QC-LDPC serial code method based on shared memory mechanism, be applicable to the QC-LDPC sign indicating number in the communication system, its coding step is described below:

The 1st step, zero clearing delayer D and shift register R ₀, R ₁..., R _C-1, buffer B _J-aWhen arriving, the i * b+j-a clock cycle load the generator polynomial g that generator matrix G i piece is capable, the j piece is listed as from the generator polynomial look-up table _{I, j}, and remain unchanged constantly at other;

The 2nd step, when k clock cycle arrives, delayer D input information bits e _k(0≤k＜a * b), buffer B ₀, B ₁..., B _C-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _C-1With the data bit D among the delayer D ₀, D ₁..., D _C-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _C-1Product respectively by b position binary adder A ₀, A ₁..., A _C-1With shift register R ₀, R ₁..., R _C-1The content addition, b position binary adder A ₀, A ₁..., A _C-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _C-1

The 3rd step be that step-length increases progressively the value that changes k with 1, repeated the 2nd step a * b time, imported up to whole information vector s to finish;

In the 4th step, when the clock cycle arrived, delayer D imported filling bit 0, buffer B ₀, B ₁..., B _C-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _C-1With the data bit D among the delayer D ₀, D ₁..., D _C-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _C-1Product respectively by b position binary adder A ₀, A ₁..., A _C-1With shift register R ₀, R ₁..., R _C-1The content addition, b position binary adder A ₀, A ₁..., A _C-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _C-1

The 5th step repeated the 4th and goes on foot c time, finishes up to 0 input of c filling bit, at this moment, shift register R ₀, R ₁..., R _C-1That store is respectively verification section p ₀, p ₁..., p _C-1, they have constituted verification vector p=(p ₀, p ₁..., p _C-1).

Be not difficult to find out that from above step whole cataloged procedure needs a * b+c clock cycle altogether, Duoed c clock cycle than existing serial code method based on c SRAA-I circuit.Usually, c can ignore much smaller than a * b.As seen, the speed of two kinds of coding methods is basic identical.

The existing solution of QC-LDPC serial code needs 2 * c * b register, c * b two input and door and c * b two input XOR gate in the communication system, and the present invention needs 2 * c * b+c register, c * b two input and door and c * b two input XOR gate.Two kinds of coding methods expend equal number with door and XOR gate, the present invention has used c register more.Usually, c can ignore much smaller than 2 * c * b.As seen, the register that expends of two kinds of coding methods is also basic identical.

To sum up, two kinds of coding methods have almost completely identical coding rate and logical resource to expend.Yet the present invention has two clear superiorities, has overcome the shortcoming of the existing solution of QC-LDPC serial code in the communication system.In existing solution, shift register is in each clock cycle or load new generator polynomial, 1 of ring shift right, the memory contents of single register constantly variation causes the power consumption of circuit big, and the present invention uses the generator polynomial of buffer load circular matrix, it is mobile to need not circulation, and the every b of its content clock cycle changes once, greatly reduced power consumption.This is first advantage of the present invention.Second advantage is to adopt to share memory mechanism, use single ROM and same data/address bus to realize the generator polynomial look-up table, overcome that the waste that a plurality of ROM bring in the existing solution is many, memory is big, the high shortcoming of cost, simplified the project organization of generator polynomial look-up table greatly, farthest save memory space, reduced cost.

In brief, for the serial code of QC-LDPC sign indicating number in the communication system, compare with existing solution, the present invention has kept identical coding rate and logical resource to expend basically, has that power consumption is little, simple in structure, memory consumption is few, low cost and other advantages.

The above; it only is one of the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; variation or the replacement that can expect without creative work all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claims were limited.

Claims (4)

1. the quasi-cyclic LDPC serial encoder of a shared memory mechanism, the generator matrix G of quasi-cyclic LDPC code are divided into the capable and t piece row of a piece, and the part generator matrix of back c piece row correspondence is by a * c b * b rank circular matrix G _{I, j}The array that constitutes, g _{I, j}Be circular matrix G _{I, j}Generator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i＜a, a≤j＜t, (s, p), that the preceding a piece row of G are corresponding is information vector s=(e to the corresponding code word v=of generator matrix G ₀, e ₁..., e _{A * b-1}), that back c piece row are corresponding is verification vector p, is one section with the b bit, verification vector p is divided into the c section, i.e. p=(p ₀, p ₁..., p _C-1), it is characterized in that described encoder comprises following parts:

The generator polynomial look-up table, the generator polynomial that is used for storing all generator matrix G circular matrixes;

Delayer D, its data bit D ₀, D ₁..., D _C-1Storage c bit information slides;

Buffer B ₀, B ₁..., B _C-1, difference buffer memory generator matrix G a, a+1 ..., the generator polynomial of circular matrix in the t-1 piece row;

B position binary multiplier M ₀, M ₁..., M _C-1, respectively to data bit D ₀, D ₁..., D _C-1With buffer B ₀, B ₁..., B _C-1In generator polynomial carry out scalar and take advantage of;

B position binary adder A ₀, A ₁..., A _C-1, respectively to b position binary multiplier M ₀, M ₁..., M _C-1Sum of products shift register R ₀, R ₁..., R _C-1Content carry out mould 2 and add;

Shift register R ₀, R ₁..., R _C-1, store b position binary adder A respectively ₀, A ₁..., A _C-1And be recycled the result that moves to left after 1 and final verification section p ₀, p ₁..., p _C-1

2. the quasi-cyclic LDPC serial encoder of a kind of shared memory mechanism according to claim 1, it is characterized in that, all circular matrix generator polynomials in the described generator polynomial look-up table stores quasi-cyclic LDPC code generator matrix, store earlier a in the 0th row successively, a+1,, the corresponding generator polynomial of t-1 piece row is stored a in the 1st row more successively, a+1,, the corresponding generator polynomial of t-1 piece row, the rest may be inferred, store successively at last the a-1 piece capable in a, a+1 ..., the corresponding generator polynomial of t-1 piece row.

3. the quasi-cyclic LDPC serial encoder of a kind of shared memory mechanism according to claim 1 is characterized in that, described buffer B ₀, B ₁..., B _C-1Share the generator polynomial look-up table, generator polynomial is therefrom read in timesharing, buffer B _J-aWhen arriving, the i * b+j-a clock cycle load the generator polynomial g that generator matrix G i piece is capable, the j piece is listed as from the generator polynomial look-up table _{I, j}, and remain unchanged constantly at other.

4. the quasi-cyclic LDPC serial code method of a shared memory mechanism, the generator matrix G of quasi-cyclic LDPC code is divided into the capable and t piece row of a piece, and the part generator matrix of back c piece row correspondence is by a * c b * b rank circular matrix G _{I, j}The array that constitutes, g _{I, j}Be circular matrix G _{I, j}Generator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i＜a, a≤j＜t, (s, p), that the preceding a piece row of G are corresponding is information vector s=(e to the corresponding code word v=of generator matrix G ₀, e ₁..., e _{A * b-1}), that back c piece row are corresponding is verification vector p, is one section with the b bit, verification vector p is divided into the c section, i.e. p=(p ₀, p ₁..., p _C-1), it is characterized in that described coding method may further comprise the steps:

The 1st step, zero clearing delayer D and shift register R ₀, R ₁..., R _C-1, buffer B _J-aWhen arriving, the i * b+j-a clock cycle load the generator polynomial g that generator matrix G i piece is capable, the j piece is listed as from the generator polynomial look-up table _{I, j}, and remain unchanged constantly at other;

The 2nd step, when k clock cycle arrives, delayer D input information bits e _k, buffer B ₀, B ₁..., B _C-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _C-1With the data bit D among the delayer D ₀, D ₁..., D _C-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _C-1Product respectively by b position binary adder A ₀, A ₁..., A _C-1With shift register R ₀, R ₁..., R _C-1The content addition, b position binary adder A ₀, A ₁..., A _C-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _C-1, wherein, 0≤k＜a * b;

The 3rd step be that step-length increases progressively the value that changes k with 1, repeated the 2nd step a * b time, imported up to whole information vector s to finish;

In the 4th step, when the clock cycle arrived, delayer D imported filling bit 0, buffer B ₀, B ₁..., B _C-1In generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _C-1With the data bit D among the delayer D ₀, D ₁..., D _C-1Carry out scalar and take advantage of, b position binary multiplier M ₀, M ₁..., M _C-1Product respectively by b position binary adder A ₀, A ₁..., A _C-1With shift register R ₀, R ₁..., R _C-1The content addition, b position binary adder A ₀, A ₁..., A _C-1And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R _C-1

The 5th step repeated the 4th and goes on foot c time, finishes up to 0 input of c filling bit, at this moment, shift register R ₀, R ₁..., R _C-1That store is respectively verification section p ₀, p ₁..., p _C-1, they have constituted verification vector p=(p ₀, p ₁..., p _C-1).

Images