CN106385264A - Two-level partial parallel inputting, accumulating and left-shifting LDPC encoder - Google Patents

Abstract

The invention provides a two-level streamline-based QC-LDPC encoder. The encoder comprises one sparse matrix and vector multiplier and one vector and high-density matrix multiplier, wherein the sparse matrix and vector multiplier realizes multiplication operation of sparse matrixes and vectors, the vector and high-density matrix multiplier employs a partial parallel inputting, accumulating and left-shifting mechanism to realize multiplication operation of vectors and high-density matrixes. The entire encoding process is divided into two-level streamlines. The QC-LDPC encoder has the advantages of low cost and large throughput.

Description

Second part is parallel to input the cumulative LDPC encoder moving to left

Technical field

The present invention relates to field of channel coding, input cumulative moving to left particularly to second part in a kind of communication system is parallel QC-LDPC encoder.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The life of QC-LDPC code Become matrix G and check matrix H to be all the array being made up of circular matrix, there is stages cycle, therefore be referred to as QC-LDPC Code.The first trip of circular matrix is the result of footline ring shift right 1, and remaining each row is all the knot of its lastrow ring shift right 1 Really, therefore, circular matrix to be characterized by its first trip completely.Generally, the first trip of circular matrix is referred to as its generator polynomial.

Communication system generally adopts the QC-LDPC code of system form, and the left-half of its generator matrix G is a unit square Battle array, right half part is by e × c b × b rank circular matrix G_i,j(1≤i≤e,e<J≤t, t=e+c) array that constitutes, as follows Shown：

Wherein, I is b × b rank unit matrix, and 0 is b × b rank full null matrix.The continuous b row of G and b row are known respectively as block Row and block row.From formula (1), G has e block row and t block row.

At present, what QC-LDPC code was widely used is to add accumulator (Type-I Shift- based on c I type shift register Register-Adder-Accumulator, SRAA-I) circuit serial encoder.The serial being made up of c SRAA-I circuit Encoder, completed to encode within e × b clock cycle.The program needs 2 × c × b depositor, c × b two input and door With c × b two input XOR gate in addition it is also necessary to e × c × b bit ROM stores the generator polynomial of circular matrix.The program has two Individual shortcoming：One is to need a large amount of memorizeies, leads to circuit cost high；Two is serial input information bit, and coding rate is slow.

Content of the invention

In communication system, the existing implementation of QC-LDPC encoder haves the shortcomings that high cost, coding rate are slow, for These technical problems, the invention provides a kind of QC-LDPC encoder based on two-level pipeline.

As shown in figure 1, the QC-LDPC encoder based on two-level pipeline is mainly made up of 2 parts in communication system：Sparse Matrix and vectorial multiplier and the vectorial multiplier with high-density matrix.Cataloged procedure divides 2 steps to complete：1st step, using sparse Matrix calculates vectorial s with the multiplier of vector；2nd step, calculates the vectorial p of verification using the multiplier of vector and high-density matrix.

Advantage and method with regard to the present invention can be further understood by following detailed description and accompanying drawings.

Brief description

Fig. 1 is the QC-LDPC cataloged procedure based on two-level pipeline；

Fig. 2 is the multiplier of sparse matrix and vector；

Fig. 3 is the functional block diagram of the multiply-add shift register MASR circuit of parallel input；

Fig. 4 be made up of the MASR circuit of the parallel input of c a kind of based on the cumulative vector moving to left of part parallel input With high-density matrix multiplier；

Fig. 5 summarizes hardware resource and process time needed for each coding step of encoder and whole cataloged procedure.

Specific embodiment

Below in conjunction with the accompanying drawings presently preferred embodiments of the present invention is elaborated, so that advantages and features of the invention can be more It is easy to be readily appreciated by one skilled in the art, thus protection scope of the present invention is made apparent clearly defining.

The row weight of circular matrix and row heavy phase are same, are denoted as w.If w=0, then this circular matrix is full null matrix.If W=1, then this circular matrix is replaceable, referred to as permutation matrix, it can be by positions some to unit matrix I ring shift right Obtain.The check matrix H of QC-LDPC code is by c × t b × b rank circular matrix H_j,k(1≤j≤c, 1≤k≤t, t=e+c) The following array constituting：

Under normal circumstances, the arbitrary circular matrix in check matrix H is full null matrix (w=0) or being displacement square Battle array (w=1).Make circular matrix H_j,kFirst trip h_j,k=(h_j,k,1,h_j,k,2,…,h_j,k,b) it is its generator polynomial, wherein h_j,k,m =0 or 1 (1≤m≤b).Because H is sparse, h_j,kOnly 1 ' 1 ', even without ' 1 '.

The front e block row of H are corresponding to be information vector a, and rear c block row are corresponding to be the vectorial p of verification, code word v=(a, p).With b Bit is one section, and information vector a is divided into e section, i.e. a=(a₁,a₂,…,a_e)；The vectorial p of verification is divided into c section, i.e. p= (p₁,p₂,…,p_c).The matrix that the front e block row of H and rear c block row are constituted is denoted as C and D respectively, then

H=[C D] (3)

C is to be made up of c × e b × b rank circular matrix, and D is to be made up of c × c b × b rank circular matrix.By formula (3) and Code word v=(a, p) substitutes into Hv^Τ=0, arrangement can obtain

p^Τ=Φ^ΤCa^Τ(4)

Wherein, Φ^T=D^–1, subscript^TWith^–1Represent transposition and inverse of a matrix respectively, D must full rank.It is known that Cyclic Moment Battle array inverse, product and remain circular matrix.Therefore, Φ is also the array being made up of circular matrix.But although matrix D is Sparse, but Φ is generally no longer sparse but highdensity.

Make s^T=Ca^TAnd p^T=Φ^Ts^T, then p=s Φ.Calculate the multiplication that s is related to sparse matrix and vector using C, using Φ Calculate the multiplication that p is related to vector and high-density matrix.From the above discussion, a kind of QC- based on two-level pipeline can be provided LDPC cataloged procedure, as shown in Figure 1.

Make s=(s₁,s₂,…,s_c), then s_j ^TIt is jth block row and a of Matrix C^TProduct, that is,

$s_j^T=H_{j,1}{a}_1^T+H_{j,2}{a}_2^T+...+H_{j,i}{a}_i^T+...+H_{j,e}{a}_e^T---\left(5\right)$

Wherein, 1≤i≤e, 1≤j≤c.s_jThe n-th bit s_j,n(1≤n≤b) is

$\begin{array}{c}{s}_{j,n}=h_{j,1}^{rs(n-1)}{a}_1+h_{j,2}^{rs(n-1)}{a}_2+\mathrm{...}+h_{j,i}^{rs(n-1)}{a}_i+\mathrm{...}+h_{j,e}^{rs(n-1)}{a}_e\\ =h_{j,1}{a}_1^{ls(n-1)}+h_{j,2}{a}_2^{ls(n-1)}+...+h_{j,i}{a}_i^{ls(n-1)}+...+h_{j,e}{a}_e^{ls(n-1)}\end{array}---\left(6\right)$

Wherein, subscript^rs(n–1)With^ls(n–1)Represent ring shift right n 1 and ring shift left n 1 respectively.Since arbitrary circulation Matrix generator polynomial h_j,iOnly a small amount of ' 1 ' even complete zero, then the inner product in formula (6) can be by posting to ring shift left The tap of storage is sued for peace and to be realized, the multiplier of sparse matrix as shown in Figure 2 and vector.Sparse matrix and vectorial multiplier By t b bit register R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition.Depositor R_1,1, R_1,2,…,R_1,eFor loading and ring shift left message segment a₁,a₂,…,a_e, depositor R_1,e+1,R_1,e+2,…,R_1,tFor storing s Array section s₁,s₂,…,s_c.Partially connected in Fig. 2 depends on all circular matrix generator polynomials in Matrix C.If h_j,i,m=1 (1≤m≤b), then message segment a_iM bit be connected to XOR gate X_1,j.Therefore, depositor R_1,iAll take out Head is depending on the nonzero element position of all circular matrix generator polynomials in i-th piece of row of Matrix C, and multi input XOR gate X_1,jInput depend on Matrix C jth block row in all circular matrix generator polynomials nonzero element position.If in C All circular matrix generator polynomials have α ' 1 ', then sparse matrix needs use (α c) individual with the multiplier of vector Two input XOR gates calculate s simultaneously_1,n,s_2,n,…,s_c,n.S can calculate within b clock cycle and finish.Using sparse matrix with The step that the multiplier of vector calculates vectorial s is as follows：

1st step, input information section a₁,a₂,…,a_e, they are stored in respectively depositor R_1,1,R_1,2,…,R_1,eIn；

2nd step, depositor R_1,1,R_1,2,…,R_1,eRing shift left 1 time simultaneously, XOR gate X_1,1,X_1,2,…,X_1,cRespectively will XOR result moves to left into depositor R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 time, after the completion of, depositor R_1,e+1,R_1,e+2,…,R_1,tStorage content be respectively to Amount section s₁,s₂,…,s_c, they constitute vectorial s.

p^T=Φ^Ts^TIt is equivalent to p=s Φ.Φ is by c × c b × b rank circular matrix Φ_j,u(1≤j≤c,1≤u≤c) The array constituting.Make circular matrix Φ_j,uFirst trip g_j,uIt is its generator polynomial.From p=s Φ, u section verification vector is full Foot

p_u=s₁Φ_1,u+s₂Φ_2,u+…+s_jΦ_j,u+…+s_cΦ_c,u(7)

Make generator polynomial g_j,u=(g_j,u,1,g_j,u,2,…,g_j,u,b), then Φ_j,uCan be considered unit matrix ring shift right version This weighted sum, that is,

Φ_j,u=g_j,u,1I^r(0)+g_j,u,2I^r(1)+…+g_j,u,bI^r(b-1)(8)

Wherein, subscript^r()Represent ring shift right.So, the jth item on the right of formula (7) equal sign is deployable is

$\begin{array}{c}{s}_j{\mathrm{\&Phi;}}_{j,u}=s_j(g_{j,u,1}{I}^{r\left(0\right)}+g_{j,u,2}{I}^{r\left(1\right)}+\mathrm{...}+g_{j,u,b}{I}^{r(b-1)})\\ =g_{j,u,1}{s}_j{I}^{r\left(0\right)}+g_{j,u,2}{s}_j{I}^{r\left(1\right)}+\mathrm{...}+g_{j,u,b}{s}_j{I}^{r(b-1)}\\ =g_{j,u,1}{s}_j^{r\left(0\right)}+g_{j,u,2}{s}_j^{r\left(1\right)}+\mathrm{...}+g_{j,u,b}{s}_j^{r(b-1)}\end{array}---\left(9\right)$

Since by s_jRing shift right n position is equivalent to its ring shift left b-n position, that is,So formula (9) can change It is written as

$\begin{array}{c}{s}_i{G}_{i,j}=g_{j,u,1}{s}_j^{l\left(b\right)}+g_{j,u,2}{s}_j^{l(b-1)}+\mathrm{...}+g_{j,u,b}{s}_j^{l\left(1\right)})\\ ={\left(g_{j,u,1}{s}_j\right)}^{l\left(b\right)}+{\left(g_{j,u,2}{s}_j\right)}^{l(b-1)}+\mathrm{...}+{\left(g_{j,u,b}{s}_j\right)}^{l\left(1\right)}\\ ={(0+g_{j,u,1}{s}_j)}^{l\left(b\right)}+{\left(g_{j,u,2}{s}_j\right)}^{l(b-1)}+\mathrm{...}+{\left(g_{j,u,b}{s}_j\right)}^{l\left(1\right)}\\ ={({\left(0+g_{j,u,1}{s}_j\right)}^{l\left(1\right)}+g_{j,u,2}{s}_j)}^{l(b-1)}+\mathrm{...}+{\left(g_{j,u,b}{s}_j\right)}^{l\left(1\right)}\\ ={(\mathrm{...}{\left({\left(0+g_{j,u,1}{s}_j\right)}^{l\left(1\right)}+g_{j,u,2}{s}_j\right)}^{l\left(1\right)}+\mathrm{...}+g_{j,u,b}{s}_j)}^{l\left(1\right)}\end{array}---\left(10\right)$

Formula (10) is the process of a-multiply-add-move to left-store, and it realizes the multiply-add shift register with parallel input (Multiplier-Adder-Shift-Register, MASR) circuit.Fig. 3 is the functional block diagram of the MASR circuit of parallel input, Vectorial s sends into this circuit with b bit parallel for one section.When the MASR circuit with parallel input is to verification section p_u(1≤u≤c) enters During row coding, generator polynomial look-up table prestores all generator polynomials of the u block row of matrix Φ, shift register quilt Reset initialization.When arriving the 1st clock cycle, array section s₁Move into circuit, generator polynomial look-up table exports the 1st of Φ Block row, generator polynomial Φ of u block row_1,uThe 0th bit g_1,u,1, and with array section s₁Carry out scalar multiplication, product g_1,u,1s₁ Add with content 0 mould 2 of shift register, and g_1,u,1s₁Result (the 0+g of ring shift left 1_1,u,1s₁)^l(1)It is stored back to shift LD Device.When arriving the 2nd clock cycle, generator polynomial look-up table exports Φ_1,uThe 2nd bit g_1,u,2, and with array section s₁ Carry out scalar multiplication, product g_1,u,2s₁Content (0+g with shift register_1,u,1s₁)^l(1)Mould 2 adds, and (0+g_1,u,1s₁)^l(1)+ g_1,u,2s₁The result ((0+g of ring shift left 1_1,u,1s₁)^l(1)+g_1,u,2s₁)^l(1)It is stored back to shift register.Above-mentioned-multiply-add-move to left- Storing process proceeds down.At the end of b-th clock cycle, shift register storage is part and s₁Φ_1,u, this It is array section s₁To p_uContribution.When arriving the b+1 clock cycle, array section s₂Move into circuit, repeat above-mentioned-multiply-add-left side Shifting-storing process.When generator polynomial look-up table has exported Φ_2,uLast bit g_2,u,bWhen, accumulator storage is portion Divide and s₁Φ_1,u+s₂Φ_2,u.Repeat said process, until entirely vectorial s all moves into circuit parallel.Now, accumulator stores It is verification section p_u.

Fig. 4 give be made up of the MASR of the parallel input of c a kind of based on the cumulative vector moving to left of part parallel input With high-density matrix multiplier, posted by generator polynomial look-up table, b position binary multiplier, b position binary adder and displacement Four kinds of functional module compositions of storage.Generator polynomial look-up table L₁,L₂,…,L_cPrestore matrix Φ the 1,2nd respectively ..., in c block row All circular matrix generator polynomials.Generator polynomial look-up table L₁,L₂,…,L_cOutput generator polynomial bit respectively with Array section s_j(1≤j≤c) carries out scalar multiplication, and this c scalar multiplication passes through b position binary multiplier M respectively₁,M₂,…,M_cComplete Become.B position binary multiplier M₁,M₂,…,M_cProduct respectively with shift register R₁,R₂,…,R_cContent be added, this c B position binary adder A is passed through in nodulo-2 addition respectively₁,A₂,…,A_cComplete.B position binary adder A₁,A₂,…,A_cAnd quilt Result after ring shift left 1 is stored in shift register R respectively₁,R₂,…,R_c.

Generator polynomial look-up table L₁,L₂,…,L_cCircular matrix generator polynomial in storage matrix Φ.Generator polynomial Look-up table L₁～L_cAll generator polynomials in 1～c block row of storage Φ, for any block row, store the 1st successively respectively, 2 ..., the corresponding generator polynomial of c block row.Generator polynomial look-up table L₁～L_cThe bit of Serial output generator polynomial.

The step calculating the vectorial p of verification using the multiplier of vector and high-density matrix is as follows：

1st step, resets shift register R₁,R₂,…,R_c；

2nd step, input vector section s_j(1≤j≤c)；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ jth block row ..., c block arranges Generator polynomial bit, these generator polynomial bits respectively pass through b position binary multiplier M₁,M₂,…,M_cWith array section s_jCarry out scalar multiplication, b position binary multiplier M₁,M₂,…,M_cProduct respectively pass through b position binary adder A₁,A₂,…,A_c With shift register R₁,R₂,…,R_cContent be added, b position binary adder A₁,A₂,…,A_cAnd by after ring shift left 1 Result be stored in shift register R respectively₁,R₂,…,R_c；

4th step, repeats the 3rd step b-1 time；

5th step, is incremented by, with 1 for step-length, the value changing j, repeats the 2nd～4 step c-1 time, until entirely vectorial s has inputted Finish, now, shift register R₁,R₂,…,R_cStorage is verification section p respectively₁,p₂,…,p_c, they constitute the vectorial p of verification =(p₁,p₂,…,p_c).

The invention provides a kind of QC-LDPC coded method based on two-level pipeline is it is adaptable to QC- in communication system LDPC code, its coding step is described as follows：

1st step, calculates vectorial s using the multiplier of sparse matrix and vector；

2nd step, calculates the vectorial p of verification using the multiplier of vector and high-density matrix.

When Fig. 5 summarizes the hardware resource consumption needed for each coding step of encoder and whole cataloged procedure and processes Between.

It is not difficult to find out from Fig. 5, when streamline is full of, whole cataloged procedure needs max (t c+b, cb)=cb clock week altogether Phase, work as c<During e, required time is less than the e × b clock cycle needed for serial encoding method based on c SRAA-I circuit.

In communication system, the existing solution of QC-LDPC encoder needs e × c × b bit ROM, and the present invention needs c²B bit ROM.Work as c<During e, the present invention needs less ROM.

As fully visible, work as c<During e, compared with traditional serial SRAA method, the present invention has that coding rate is fast, memorizer disappears The advantages of consumption is few.

The above, only one of specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, Any those of ordinary skill in the art disclosed herein technical scope in, the change that can expect without creative work Change or replace, all should be included within the scope of the present invention.Therefore, protection scope of the present invention should be with claims The protection domain being limited is defined.

Claims (4)

1. a kind of QC-LDPC encoder based on two-level pipeline, the check matrix H of QC-LDPC code is by c × t b × b rank The array that circular matrix is constituted, wherein, c, t and b are all positive integer, t=e+c, and check matrix H can be divided into 2 submatrixs, H =[C D], C are to be made up of c × e b × b rank circular matrix, and D is to be made up of c × c b × b rank circular matrix, Φ^T=D^–1, Wherein, subscript^ΤWith^-1Represent transposition and inverse, Matrix C corresponding informance vector a, the vectorial p of the corresponding verification of matrix D respectively, with b bit be One section, information vector a is divided into e section, i.e. a=(a₁,a₂,…,a_e), the vectorial p of verification is divided into c section, i.e. p=(p₁, p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s is divided into c section, i.e. s=(s₁,s₂,…,s_c) it is characterised in that described volume Code device is included with lower component：

Sparse matrix and vectorial multiplier, by t b bit register R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition, for calculating vectorial s；

Vector and the multiplier of high-density matrix, move to left mechanism based on part parallel input is cumulative, by generator polynomial look-up table, B position binary multiplier, b position binary adder and shift register composition, for calculating the vectorial p of verification, generator polynomial Look-up table L₁,L₂,…,L_cPrestore matrix Φ the 1,2nd respectively ..., all circular matrix generator polynomials in c block row；Generate many Item formula look-up table L₁,L₂,…,L_cOutput generator polynomial bit respectively with array section s_jCarry out scalar multiplication, this c scalar multiplication Method passes through b position binary multiplier M respectively₁,M₂,…,M_cComplete；B position binary multiplier M₁,M₂,…,M_cProduct respectively with Shift register R₁,R₂,…,R_cContent be added, this c nodulo-2 addition is respectively by b position binary adder A₁,A₂,…,A_c Complete；B position binary adder A₁,A₂,…,A_cAnd shift register R is stored in respectively by the result after ring shift left 1₁, R₂,…,R_c, wherein, 1≤j≤c.

2. a kind of QC-LDPC encoder based on two-level pipeline according to claim 1 is it is characterised in that described dilute Thin matrix is as follows with the step of the vectorial s of multiplier calculating of vector：

1st step, input information section a₁,a₂,…,a_e, they are stored in respectively depositor R_1,1,R_1,2,…,R_1,eIn；

2nd step, depositor R_1,1,R_1,2,…,R_1,eRing shift left 1 time simultaneously, XOR gate X_1,1,X_1,2,…,X_1,cRespectively by XOR Result moves to left into depositor R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 time, after the completion of, depositor R_1,e+1,R_1,e+2,…,R_1,tThe content of storage is array section respectively s₁,s₂,…,s_c, they constitute vectorial s.

3. a kind of QC-LDPC encoder based on two-level pipeline according to claim 1 it is characterised in that described to Amount is as follows with the step of the vectorial p of multiplier calculating verification of high-density matrix：

1st step, resets shift register R₁,R₂,…,R_c；

2nd step, input vector section s_j, wherein, 1≤j≤c；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ jth block row ..., the life of c block row Become multinomial bit, these generator polynomial bits pass through b position binary multiplier M respectively₁,M₂,…,M_cWith array section s_jEnter Row scalar multiplication, b position binary multiplier M₁,M₂,…,M_cProduct respectively pass through b position binary adder A₁,A₂,…,A_cWith shifting Bit register R₁,R₂,…,R_cContent be added, b position binary adder A₁,A₂,…,A_cAnd by the knot after ring shift left 1 Fruit is stored in shift register R respectively₁,R₂,…,R_c；

4th step, repeats the 3rd step b-1 time；

5th step, is incremented by, with 1 for step-length, the value changing j, repeats the 2nd～4 step c-1 time, until entirely vectorial s input finishes, this When, shift register R₁,R₂,…,R_cStorage is verification section p respectively₁,p₂,…,p_c, they constitute the vectorial p=(p of verification₁, p₂,…,p_c).

4. a kind of QC-LDPC coded method based on two-level pipeline, the check matrix H of QC-LDPC code is by c × t b × b The array that rank circular matrix is constituted, wherein, c, t and b are all positive integer, t=e+c, and check matrix H can be divided into 2 submatrixs, H=[C D], C are to be made up of c × e b × b rank circular matrix, and D is to be made up of c × c b × b rank circular matrix, Φ^T=D^–1, Wherein, subscript^ΤWith^-1Represent transposition and inverse, Matrix C corresponding informance vector a, the vectorial p of the corresponding verification of matrix D respectively, with b bit be One section, information vector a is divided into e section, i.e. a=(a₁,a₂,…,a_e), the vectorial p of verification is divided into c section, i.e. p=(p₁, p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s is divided into c section, i.e. s=(s₁,s₂,…,s_c) it is characterised in that described volume Code method comprises the following steps：

1st step, calculates vectorial s using the multiplier of sparse matrix and vector；

2nd step, calculates the vectorial p of verification using the multiplier of vector and high-density matrix.