CN106656207A - LDPC encoder for two-level partial parallel input right shift accumulation in WPAN - Google Patents

Abstract

The invention provides a QC-LDPC encoder based on a two-level assembly line in WPAN. The encoder comprises a sparse matrix and vector multiplier and a vector and high-density matrix multiplier. The sparse matrix and vector multiplier implements the multiplication of a sparse matrix and a vector. The vector and high-density matrix multiplier implements the multiplication of a vector and a high-density matrix through use of a partial parallel input right shift accumulation mechanism. The whole encoding process is divided into two levels of assembly lines. The 7/8 bit rate QC-LDPC encoder in a WPAN system provided by the invention has the advantages of low cost, large throughput, and the like.

Description

Parallel input moves to right cumulative LDPC encoder to second part in WPAN

Technical field

The present invention relates to field of channel coding, the parallel input of second part in more particularly to a kind of WPAN systems moves to right cumulative QC-LDPC encoders.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The life of QC-LDPC codes All it is the array being made up of circular matrix into matrix G and check matrix H, the characteristics of with stages cycle, therefore is referred to as QC-LDPC Code.The first trip of circular matrix is the result of footline ring shift right 1, and remaining each row is all the knot of its lastrow ring shift right 1 Really, therefore, circular matrix is characterized completely by its first trip.Generally, the first trip of circular matrix is referred to as its generator polynomial.

WPAN standards employ the QC-LDPC codes of system form, and the left-half of its generator matrix G is a unit square Battle array, right half part is by e × c b × b rank circular matrix G_i,j(1≤i≤e,e<J≤t, t=e+c) constitute array, it is as follows It is shown：

Wherein, I is b × b rank unit matrixs, and 0 is b × b rank full null matrix.The continuous b rows of G and b row are known respectively as block Row and block row.From formula (1), G has e blocks row and t blocks row.WPAN standards employ a kind of QC-LDPC codes of code check η=7/8, For the code, t=32, e=28, c=4, b=21.

The existing solution of 7/8 code check QC-LDPC encoders is added based on c I type shift register in WPAN standards The serial encoder of accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) circuit.By c The serial encoder that SRAA-I circuits are constituted, completes coding within e × b clock cycle.The program needs 2 × c × b deposit Device, c × b two inputs and door and c × b two input XOR gate, in addition it is also necessary to which e × c × b bits ROM stores the life of circular matrix Into multinomial.The program has two shortcomings：One is to need a large amount of memories, causes circuit cost high；Two is serial input information Bit, coding rate is slow.

The content of the invention

In WPAN systems the existing implementation of 7/8 code check QC-LDPC encoders exist high cost, coding rate it is slow lack Point, for these technical problems, the invention provides a kind of QC-LDPC encoders based on two-level pipeline.

As shown in figure 1, the QC-LDPC encoders in WPAN systems based on two-level pipeline are mainly made up of 2 parts：It is sparse Matrix and the multiplier and vector of vector and the multiplier of high-density matrix.2 steps of cataloged procedure point are completed：1st step, using sparse Matrix calculates vector s with the multiplier of vector；2nd step, verification vector p is calculated using vector with the multiplier of high-density matrix.

Can be further understood by following detailed description and accompanying drawings with method with regard to the advantage of the present invention.

Description of the drawings

Fig. 1 is based on the QC-LDPC cataloged procedures of two-level pipeline；

Fig. 2 is the multiplier of sparse matrix and vector；

Fig. 3 is the functional block diagram of II types shift register plus accumulator SRAA-II circuits；

Fig. 4 is that a kind of the input based on part parallel being made up of c SRAA-II circuit moves to right cumulative vectorial and high density Matrix multiplier；

Fig. 5 summarizes each coding step of encoder and hardware resource and process time needed for whole cataloged procedure.

Specific embodiment

Presently preferred embodiments of the present invention is elaborated below in conjunction with the accompanying drawings, so that advantages and features of the invention can be more It is easy to be readily appreciated by one skilled in the art, apparent clearly defines so as to make to protection scope of the present invention.

The row weight of circular matrix and row heavy phase are same, are denoted as w.If w=0, then the circular matrix is full null matrix.If W=1, then the circular matrix is replaceable, referred to as permutation matrix, and it can be by some positions of unit matrix I ring shift rights Obtain.The check matrix H of QC-LDPC codes is by c × t b × b rank circular matrix H_j,k(1≤j≤c, 1≤k≤t, t=e+c) The following array for constituting：

Under normal circumstances, the arbitrary circular matrix in check matrix H is either full null matrix (w=0) or is displacement square Battle array (w=1).Make circular matrix H_j,kFirst trip h_j,k=(h_j,k,1,h_j,k,2,…,h_j,k,b) it is its generator polynomial, wherein h_j,k,m =0 or 1 (1≤m≤b).Because H is sparse, h_j,kOnly 1 ' 1 ', even without ' 1 '.

It is information vector a that the front e blocks row of H are corresponding, and it is to verify vector p, code word v=(a, p) that rear c blocks row are corresponding.With b Bit is one section, and information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e)；Verification vector p is divided into c sections, i.e. p= (p₁,p₂,…,p_c).The front e blocks row and rear c blocks of H are arranged the matrix for constituting and is denoted as C and D respectively, then

H=[C D] (3)

C is made up of c × e b × b rank circular matrix, and D is made up of c × c b × b rank circular matrix.By formula (3) and Code word v=(a, p) substitutes into Hv^T=0, arrangement can be obtained

p^T=Φ^TCa^T(4) wherein, Φ^T=D^–1, subscript^TWith^–1Transposition and inverse of a matrix are represented respectively, and D must full rank. It is well known that the inverse of circular matrix, product and remaining circular matrix.Therefore, Φ is also the array being made up of circular matrix. But, although matrix D is sparse, but Φ is generally no longer sparse but highdensity.

Make s^T=Ca^TAnd p^T=Φ^Ts^T, then p=s Φ.The multiplication that s is related to sparse matrix and vector is calculated using C, using Φ Calculate the multiplication that p is related to vector and high-density matrix.From the above discussion, a kind of QC- based on two-level pipeline can be given LDPC cataloged procedures, as shown in Figure 1.

Make s=(s₁,s₂,…,s_c), then s_j ^TIt is the jth block row and a of Matrix C^TProduct, i.e.,

Wherein, 1≤i≤e, 1≤j≤c.s_jThe n-th bit s_j,n(1≤n≤b) is

Wherein, subscript^rs(n–1)With^ls(n–1) ring shift right n -1 and ring shift left n -1 are represented respectively.Since arbitrary follow Ring matrix generator polynomial h_j,iOnly a small amount of ' 1 ' even complete zero, then the inner product in formula (6) can be by ring shift left The tap summation of register realizing, the multiplier of sparse matrix as shown in Figure 2 and vector.Sparse matrix and vectorial multiplication Device is by t b bit register R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition.Register R_1,1,R_1,2,…,R_1,eFor loading and ring shift left message segment a₁,a₂,…,a_e, register R_1,e+1,R_1,e+2,…,R_1,tFor The array section s of storage s₁,s₂,…,s_c.Partially connected in Fig. 2 depends on all circular matrix generator polynomials in Matrix C. If h_j,i,m=1 (1≤m≤b), then message segment a_iM bits be connected to XOR gate X_1,j.Therefore, register R_1,iInstitute There is tap to depend on the nonzero element position of all circular matrix generator polynomials in i-th piece of row of Matrix C, and multi input is different OR gate X_1,jInput depending on all circular matrix generator polynomials in Matrix C jth block row nonzero element position.Such as All circular matrix generator polynomials in fruit C are total α ' 1 ', then sparse matrix need to use with the multiplier of vector (α- C) individual two inputs XOR gate calculates s simultaneously_1,n,s_2,n,…,s_c,n.S can be calculated within b clock cycle and finished.Using sparse square The step of battle array calculates vector s with the multiplier of vector is as follows：

1st step, input information section a₁,a₂,…,a_e, they are stored in respectively register R_1,1,R_1,2,…,R_1,eIn；

2nd step, register R_1,1,R_1,2,…,R_1,eSimultaneously ring shift left 1 time, XOR gate X_1,1,X_1,2,…,X_1,cRespectively will XOR result is moved to left into register R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 time, after the completion of, register R_1,e+1,R_1,e+2,…,R_1,tThe content of storage be respectively to Amount section s₁,s₂,…,s_c, they constitute vectorial s.

p^T=Φ^Ts^TIt is equivalent to p=s Φ.Φ is by c × c b × b rank circular matrix Φ_j,u(1≤j≤c,1≤u≤c) The array of composition.Make circular matrix Φ_j,uFirst trip g_j,uIt is its generator polynomial.From p=s Φ, u sections verification vector is full Foot

p_u=s₁Φ_1,u+s₂Φ_2,u+…+s_jΦ_j,u+…+s_cΦ_c,u (7)

Make generator polynomial g_j,u=(g_j,u,1,g_j,u,2,…,g_j,u,b), then Φ_j,uCan be considered unit matrix ring shift right version This weighted sum, i.e.,

Φ_j,u=g_j,u,1I^r(0)+g_j,u,2I^r(1)+…+g_j,u,bI^r(b-1) (8)

Wherein, subscript r () represents ring shift right.So, jth item on the right of formula (7) equal sign is deployable to be

Formula (9) is one and moves to right-the process of-multiply-add-storage, and its realization adds accumulator (Type- with II type shift registers II Shift-Register-Adder-Accumulator, SRAA-II) circuit.Fig. 3 is the functional block diagram of SRAA-II circuits, Vectorial s sends into parallel the circuit with b bits as one section.When with SRAA-II circuits to verify section p_u(1≤u≤c) is encoded When, generator polynomial look-up table prestores all generator polynomials of the u blocks row of matrix Φ, and accumulator is cleared initially Change.When arriving the 1st clock cycle, array section s₁Shift register is moved into, generator polynomial look-up table exports the 1st piece of Φ Generator polynomial Φ of row, u blocks row_1,uThe 1st bit g_1,u,1, and with the content of shift registerCarry out scalar multiplication, ProductAdd with the mould 2 of content 0 of accumulator, andIt is stored back to accumulator.When arriving the 2nd clock cycle, displacement Register cycle moves to right 1, and content is changed intoGenerator polynomial look-up table exports Φ_1,uThe 2nd bit g_1,u,2, and with shifting The content of bit registerCarry out scalar multiplication, productWith the content of accumulatorMould 2 adds, andIt is stored back to accumulator.It is above-mentioned move to right-- multiply-add-storing process proceeds down.When b-th clock cycle At the end of, generator polynomial look-up table has exported Φ_1,uLast bit g_1,u,b, now accumulator storage be part and s₁Φ_1,u, this is array section s₁To p_uContribution.When arriving the b+1 clock cycle, array section s₂Move into shift register, Repetition is above-mentioned to move to right-- multiply-add-storing process.When generator polynomial look-up table has exported Φ_2,uLast bit g_2,u,bWhen, Accumulator storage is part and s₁Φ_1,u+s₂Φ_2,u.Repeat said process, until whole vector s is all parallel circuit is moved into. Now, accumulator storage is verification section p_u。

Fig. 4 is given a kind of the input based on part parallel being made up of c SRAA-II circuit and moves to right cumulative vector with height Density matrix multiplier, by shift register, generator polynomial look-up table, b positions binary multiplier, b positions binary adder With five kinds of functional module compositions of accumulator.Shift register is to array section s_j(1≤j≤c) ring shift right.Generator polynomial is searched Table L₁,L₂,…,L_cPrestore respectively matrix Φ the 1,2nd ..., all circular matrix generator polynomials in c blocks row.Generator polynomial Look-up table L₁,L₂,…,L_cThe generator polynomial bit of output carries out scalar multiplication with the content of shift register respectively, this c mark Amount multiplication passes through respectively b positions binary multiplier M₁,M₂,…,M_cComplete.B positions binary multiplier M₁,M₂,…,M_cProduct point Not with accumulator R₁,R₂,…,R_cContent be added, this c nodulo-2 addition is respectively by b positions binary adder A₁,A₂,…,A_c Complete.B positions binary adder A₁,A₂,…,A_cAnd be stored in accumulator R respectively₁,R₂,…,R_c。

Generator polynomial look-up table L₁,L₂,…,L_cCircular matrix generator polynomial in storage matrix Φ.Generator polynomial Look-up table L₁～L_cThe all generator polynomials in 1～c blocks row of Φ are stored respectively, for any block row, the 1st are stored successively, 2 ..., the corresponding generator polynomial of c block rows.Generator polynomial look-up table L₁～L_cThe bit of Serial output generator polynomial.

The step of calculating verification vector p using vector and the multiplier of high-density matrix is as follows：

1st step, resets accumulator R₁,R₂,…,R_c；

2nd step, shift register input vector section s_j(1≤j≤c)；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ jth block rows ..., c blocks row Generator polynomial bit, these generator polynomial bits respectively pass through b positions binary multiplier M₁,M₂,…,M_cPost with displacement The content of storage carries out scalar multiplication, b positions binary multiplier M₁,M₂,…,M_cProduct respectively pass through b positions binary adder A₁,A₂,…,A_cWith accumulator R₁,R₂,…,R_cContent be added, b positions binary adder A₁,A₂,…,A_cAnd be stored in respectively Accumulator R₁,R₂,…,R_c；

4th step, shift register ring shift right one repeats the 3rd step b-1 time；

5th step, with 1 as step-length the value for changing j is incremented by, and repeats the 2nd～4 step c-1 time, until whole vector s has been input into Finish, now, accumulator R₁,R₂,…,R_cStorage is respectively verification section p₁,p₂,…,p_c, they constitute verification vector p= (p₁,p₂,…,p_c)。

The invention provides a kind of QC-LDPC coding methods based on two-level pipeline, it is adaptable to 7/8 in WPAN systems Code check QC-LDPC codes, its coding step is described as follows：

1st step, vector s is calculated using sparse matrix with the multiplier of vector；

2nd step, verification vector p is calculated using vector with the multiplier of high-density matrix.

When Fig. 5 summarizes each coding step of encoder and the hardware resource consumption needed for whole cataloged procedure and processes Between.

It is not difficult to find out from Fig. 5, when streamline is full of, whole cataloged procedure needs altogether max (t-c+b, cb)=cb clock week Phase, less than the e × b clock cycle needed for the serial encoding method based on c SRAA-I circuit.For 7/8 in WPAN standards Code check QC-LDPC encoders, the coding rate of the present invention is 7 times of the latter.

The existing solution of 7/8 code check QC-LDPC encoders needs e × c × b bit ROM in WPAN standards, and this It is bright to need c²B bit ROM.The present invention needs less ROM, is the 1/7 of existing solution.

As fully visible, for 7/8 code check QC-LDPC encoders in WPAN standards, compared with traditional serial SRAA methods, this Invention has the advantages that coding rate is fast, memory consumption lacks.

The above, only one of specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, Any those of ordinary skill in the art disclosed herein technical scope in, the change that can be expected without creative work Change or replace, all should be included within the scope of the present invention.Therefore, protection scope of the present invention should be with claims The protection domain for being limited is defined.

Claims (4)

1. QC-LDPC encoders in a kind of WPAN based on two-level pipeline, the check matrix H of 7/8 code check QC-LDPC codes be by The array that c × t b × b ranks circular matrix is constituted, wherein, c=4, t=32, b=21, e=t-c=28, check matrix H can draw It is divided into 2 submatrixs, H=[C D], C is made up of c × e b × b rank circular matrix, and D is by c × c b × b rank Cyclic Moment Battle array is constituted, Φ^T=D^–1, wherein, subscript^ΤWith^-1Transposition and inverse, Matrix C corresponding informance vector a are represented respectively, and matrix D correspondence is verified Vectorial p, with b bits as one section, information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e), verification vector p is divided into c Section, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s is divided into c sections, i.e. s=(s₁,s₂,…,s_c), its feature It is that the encoder is included with lower component：

Sparse matrix and vectorial multiplier, by t b bit register R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition, for calculating vectorial s；

Vector and the multiplier of high-density matrix, based on part parallel input cumulative mechanism is moved to right, many by shift register, generation Item formula look-up table, b positions binary multiplier, b positions binary adder and accumulator composition, for calculating verification vector p, displacement Register pair array section s_jRing shift right, generator polynomial look-up table L₁,L₂,…,L_cPrestore respectively matrix Φ the 1,2nd ..., c blocks All circular matrix generator polynomials in row, generator polynomial look-up table L₁,L₂,…,L_cThe generator polynomial bit of output point Scalar multiplication is not carried out with the content of shift register, this c scalar multiplication passes through respectively b positions binary multiplier M₁,M₂,…,M_c Complete, b positions binary multiplier M₁,M₂,…,M_cProduct respectively with accumulator R₁,R₂,…,R_cContent be added, this c mould 2 Addition passes through respectively b positions binary adder A₁,A₂,…,A_cComplete, b positions binary adder A₁,A₂,…,A_cAnd deposit respectively Enter accumulator R₁,R₂,…,R_c, wherein, 1≤j≤c.

2. the QC-LDPC encoders of two-level pipeline are based in a kind of WPAN according to claim 1, it is characterised in that The step of sparse matrix calculates vector s with the multiplier of vector is as follows：

1st step, input information section a₁,a₂,…,a_e, they are stored in respectively register R_1,1,R_1,2,…,R_1,eIn；

2nd step, register R_1,1,R_1,2,…,R_1,eSimultaneously ring shift left 1 time, XOR gate X_1,1,X_1,2,…,X_1,cRespectively by XOR As a result move to left into register R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 time, after the completion of, register R_1,e+1,R_1,e+2,…,R_1,tThe content of storage is respectively array section s₁,s₂,…,s_c, they constitute vectorial s.

3. the QC-LDPC encoders of two-level pipeline are based in a kind of WPAN according to claim 1, it is characterised in that The step of vector calculates verification vector p with the multiplier of high-density matrix is as follows：

1st step, resets accumulator R₁,R₂,…,R_c；

2nd step, shift register input vector section s_j, wherein, 1≤j≤c；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ jth block rows ..., the life of c blocks row Into multinomial bit, these generator polynomial bits pass through respectively b positions binary multiplier M₁,M₂,…,M_cWith shift register Content carry out scalar multiplication, b positions binary multiplier M₁,M₂,…,M_cProduct respectively pass through b positions binary adder A₁, A₂,…,A_cWith accumulator R₁,R₂,…,R_cContent be added, b positions binary adder A₁,A₂,…,A_cAnd be stored in respectively it is cumulative Device R₁,R₂,…,R_c；

4th step, shift register ring shift right one repeats the 3rd step b-1 time；

5th step, with 1 as step-length the value for changing j is incremented by, and repeats the 2nd～4 step c-1 time, until whole vector s inputs are finished, this When, accumulator R₁,R₂,…,R_cStorage is respectively verification section p₁,p₂,…,p_c, they constitute verification vector p=(p₁, p₂,…,p_c)。

4. the QC-LDPC coding methods of two-level pipeline are based in a kind of WPAN, and the check matrix H of 7/8 code check QC-LDPC codes is The array being made up of c × t b × b rank circular matrix, wherein, c=4, t=32, b=21, e=t-c=28, check matrix H can 2 submatrixs, H=[C D] are divided into, C is made up of c × e b × b rank circular matrix, D is circulated by c × c b × b rank Matrix is constituted, Φ^T=D^–1, wherein, subscript^ΤWith-¹Transposition and inverse, Matrix C corresponding informance vector a, matrix D correspondence are represented respectively Verification vector p, with b bits as one section, information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e), verification vector p by etc. It is divided into c sections, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s is divided into c sections, i.e. s=(s₁,s₂,…,s_c), its It is characterised by, the coding method is comprised the following steps：

1st step, vector s is calculated using sparse matrix with the multiplier of vector；

2nd step, verification vector p is calculated using vector with the multiplier of high-density matrix.