CN103236852B - Without quasi cyclic matrix serial multiplier in the DTMB of multiplying - Google Patents

Abstract

The invention provides a kind of without quasi cyclic matrix serial multiplier in the DTMB of multiplying, for realizing the multiplying of vectorial m and quasi-cyclic matrix F in DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding, this multiplier comprise 3 generator polynomial look-up tables prestoring circular matrix generator polynomial and 127 null vectors in all code check matrix F, 3 127 binary adders that mould 2 adds are carried out to the output of generator polynomial look-up table and shift register content, 3 storages be recycled move to left 1 and 127 bit shift register.The compatible all code checks of quasi cyclic matrix serial multiplier provided by the invention, eliminate multiplying, have that logical resource is few, structure is simple, power consumption is little, low cost and other advantages.

Description

Without quasi cyclic matrix serial multiplier in the DTMB of multiplying

Technical field

The present invention relates to field of channel coding, the quasi cyclic matrix serial multiplier particularly in a kind of DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding.

Background technology

Low-density checksum (Low-DensityParity-Check, LDPC) code is one of efficient channel coding technology, and QC-LDPC(Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code.The generator matrix G of QC-LDPC code and check matrix H are all the arrays be made up of circular matrix, have the feature of stages cycle, therefore are called as QC-LDPC code.The first trip of circular matrix is the result of footline ring shift right 1, and all the other each provisional capitals are results of its lastrow ring shift right 1, and therefore, circular matrix is characterized by its first trip completely.Usually, the first trip of circular matrix is called as its generator polynomial.

When adopting near lower triangular coding method to encode to QC-LDPC code, exchanged by ranks, check matrix H is transformed near lower triangular shape HALT, and it is composed as follows by 6 sub-matrixes:

$H_{\mathrm{ALT}}=\left[\begin{array}{ccc}A& B& L\\ C& D& E\end{array}\right]---\left(1\right)$

Wherein, L is lower triangular matrix.H _aLTcorresponding code word v _aLT=(s, p, q), matrix A and C corresponding informance vector s, matrix B and the vectorial p of the corresponding part verification of D, matrix L and E be corresponding remaining verification vector q then.The method that calculating section verifies vectorial p is as follows:

P=s (C+EL ^-1a) ^Τ((D+EL ^-1b) ^-1) ^t(2) wherein, subscript ^-1with ^Τrepresent respectively matrix inversion and transposition.Order

m＝s(C+EL ^-1A) ^Τ(3)

F=((D+EL ^-1b) ^-1) ^Τ(4) then vectorial m and matrix F meet following relation:

p＝mF(5)

Matrix F is by following u × u b × b rank circular matrix F _i,jthe quasi-cyclic matrix that (0≤i<u, 0≤j<u) is formed:

The continuous b of F capable and b row are called as the capable and block row of block respectively.From formula (6), F has u block capable and u block row.Make f _i,jcircular matrix F _i,jgenerator polynomial.

Make vectorial m=(e ₀, e ₁..., e _{u × b-1}), part verifies vectorial p=(d ₀, d ₁..., d _{u × b-1}).Be one section with b bit, vectorial m and part verify vectorial p and are all divided into u section, i.e. m=(m ₀, m ₁..., m _u-1) and p=(p ₀, p ₁..., p _u-1).From formula (5), the jth section p of part verification vector _jmeet

p _j＝m ₀F _0,j+m ₁F _1,j+…+m _iF _i,j+…+m _u-1F _u-1,j(7)

Wherein, 0≤i<u, 0≤j<u.Order with generator polynomial f respectively _i,jthe result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.So, i-th on the right of formula (7) equal sign deployable is

$m_i{F}_{i,j}=e_{i\&times;b}{f}_{i,j}^{r\left(0\right)}+e_{i\&times;b+1}{f}_{i,j}^{r\left(1\right)}+\&CenterDot;\&CenterDot;\&CenterDot;+e_{i\&times;b+b-1}{f}_{i,j}^{r(b-1)}---\left(8\right)$

Formula (5) relates to the multiplication of vector and quasi-cyclic matrix, and what extensively adopt at present is the scheme adding accumulator (Type-IShift-Register-Adder-Accumulator, SRAA-I) circuit based on u I type shift register.Fig. 1 is the functional block diagram of single SRAA-I circuit, and vectorial m by turn serial sends into this circuit.When verifying section p with SRAA-I circuit counting _jtime (0≤j<u), generator polynomial look-up table prestores all generator polynomials of the jth block row of quasi-cyclic matrix F, and accumulator is cleared initialization.When the 0th clock cycle arrives, shift register loads the 0th piece of row of F, the generator polynomial of jth block row from generator polynomial look-up table bit e ₀move into circuit, and with the content of shift register carry out scalar multiplication, product add with content 0 mould 2 of accumulator, and deposit back accumulator.When the 1st clock cycle arrives, shift register ring shift right 1, content becomes bit e ₁move into circuit, and with the content of shift register carry out scalar multiplication, product with the content of accumulator mould 2 adds, and deposit back accumulator.Above-mentioned-the Jia that moves to right-take advantage of-storing process proceeds down.At the end of b-1 clock cycle, bit e _b-1move into circuit, that now accumulator stores is part and m ₀f _{0, j}, this is array section m ₀to p _jcontribution.When b clock cycle arrives, shift register loads the 1st piece of row of F, the generator polynomial of jth block row from generator polynomial look-up table repeat the above-mentioned-Jia that moves to right-take advantage of-storing process.As array section m ₁when moving into circuit completely, that accumulator stores is part and m ₀f _{0, j}+ m ₁f _{1, j}.Repeat said process, until the whole serial of whole vectorial m moves into circuit.Now, that accumulator stores is verification section p _j.Use the quasi cyclic matrix serial multiplier shown in u SRAA-I circuit energy pie graph 2, it obtains u verification section within u × b clock cycle simultaneously.The program needs 2 × u × b register, u × b two inputs to input XOR gate with door and u × b individual two, also needs u u × b bit ROM to store the generator polynomial of circular matrix.

DTMB standard have employed code check η=0.4,0.6 and 0.8 3 kind of QC-LDPC code, all has b=127.For code check η=0.4,0.6 and 0.8, u be 3,2 and 2 respectively.

For compatible 3 kinds of code checks, in DTMB standard QC-LDPC near lower triangular coding, the existing solution of quasi-cyclic matrix serial multiplication is based on 3 SRAA-I circuit, need 762 registers, 381 two inputs input XOR gate with door and 381 two, also need the ROM of 2 889 bits to store the circular matrix generator polynomial of the 0th, the 1 piece of row of 3 kinds of code check quasi-cyclic matrix F respectively, the ROM of 1 381 bit stores the circular matrix generator polynomial of the 2nd piece of row of η=0.4 code check F.The shortcoming of the program is that register number is large, needs a large amount of and door to complete multiplying, and so many logical resource will certainly cause that the power consumption of circuit is large, cost is high.

Summary of the invention

In DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding there is the shortcoming that power consumption is large, cost is high in the existing implementation of quasi-cyclic matrix serial multiplication, for these technical problems, the invention provides a kind of quasi cyclic matrix serial multiplier without multiplying.

As shown in Figure 4, the quasi cyclic matrix serial multiplier in DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding forms primarily of 3 parts: generator polynomial look-up table, b position binary adder and shift register.Multiplication process divides 3 steps to complete: the 1st step, resets shift register R ₀, R ₁, R ₂; 2nd step, input bit e _k(0≤k<u × b), generator polynomial look-up table L ₀, L ₁, L ₂according to e _k=1 or the 0 respectively generator polynomials of bit rate output η quasi-cyclic matrix F i-th=[k/b] the 0th, 1,2 pieces of row during (symbol [k/b] represents the maximum integer being not more than k/b), block was capable or b position null vector, generator polynomial look-up table L ₀, L ₁, L ₂output respectively by b position binary adder A ₀, A ₁, A ₂with shift register R ₀, R ₁, R ₂content be added, b position binary adder A ₀, A ₁, A ₂and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁, R ₂; 3rd step, with 1 for step-length increases progressively the value changing k, repetition the 2nd step u × b time, until whole vectorial m input is complete, now, shift register R ₀, R ₁..., R _u-1that store is verification section p respectively ₀, p ₁..., p _u-1, they constitute part and verify vectorial p=(p ₀, p ₁..., p _u-1).

Quasi cyclic matrix serial multiplier structure provided by the invention is simple, the QC-LDPC code of all code checks in compatible DTMB standard, removes multiplying, reduces logical resource, reduces power consumption, cost-saving.

Be further understood by detailed description and accompanying drawings below about advantage of the present invention and method.

Accompanying drawing explanation

Fig. 1 is the functional block diagram that I type shift register adds accumulator SRAA-I circuit;

Fig. 2 is the quasi cyclic matrix serial multiplier be made up of u SRAA-I circuit;

Fig. 3 is the functional block diagram selecting to add shift register SASR circuit;

Fig. 4 is a kind of quasi cyclic matrix serial multiplier without multiplying be made up of 3 SASR circuit.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment of the present invention is elaborated, can be easier to make advantages and features of the invention be readily appreciated by one skilled in the art, thus more explicit defining is made to protection scope of the present invention.

Since by the generator polynomial f of circular matrix _i,jring shift right n position is equivalent to its ring shift left b-n position, namely so formula (8) can be rewritten as

$m_i{F}_{i,j}=e_{i\&times;b}{f}_{i,j}^{l\left(b\right)}+e_{i\&times;b+1}{f}_{i,j}^{l(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+e_{i\&times;b+b-1}{f}_{i,j}^{l\left(1\right)}$

$={\left(e_{i\&times;b}{f}_{i,j}\right)}^{l\left(b\right)}+{\left(e_{i\&times;b+1}{f}_{i,j}\right)}^{l(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+{\left(e_{i\&times;b+b-1}{f}_{i,j}\right)}^{l\left(1\right)}$

$={\left({0+e}_{i\&times;b}{f}_{i,j}\right)}^{l\left(b\right)}+{\left(e_{i\&times;b+1}{f}_{i,j}\right)}^{l(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+{\left(e_{i\&times;b+b-1}{f}_{i,j}\right)}^{l\left(1\right)}---\left(9\right)$

$={({(0+e_{i\&times;b}{f}_{i,j})}^{l\left(1\right)}+e_{i\&times;b+1}{f}_{i,j})}^{l(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+{\left(e_{i\&times;b+b-1}{f}_{i,j}\right)}^{l\left(1\right)}$

$={(\&CenterDot;\&CenterDot;\&CenterDot;{({(0+e_{i\&times;b}{f}_{i,j})}^{l\left(1\right)}+e_{i\&times;b+1}{f}_{i,j})}^{l\left(1\right)}+\&CenterDot;\&CenterDot;\&CenterDot;+e_{i\&times;b+b-1}{f}_{i,j})}^{l\left(1\right)}$

Compared with formula (8), the remarkable advantage of formula (9) is generator polynomial f _i,jwithout the need to ring shift right.Product term in the very big simplified style (9) of this feature energy: with e _{i × b}f _i,jfor example, if e _{i × b}=1, so e _{i × b}f _i,j=f _i,j; Otherwise product is b position null vector.Obviously, this is the operation principle of a typical alternative selector, and its input is f _i,jwith b position null vector, control end is e _{i × b}.That removes the multiplying in formula (9).Formula (9) is simplified to the process that is selected-Jia-move to left-store, and its realization selection adds shift register (Selecter-Adder-Shift-Register, SASR) circuit.Fig. 3 is the functional block diagram of SASR circuit, and vectorial m is sent into this circuit by serial by turn.When verifying section p with SASR circuit counting _jtime (0≤j<u), generator polynomial look-up table prestores all generator polynomials and 1 b position null vector of the jth block row of quasi-cyclic matrix F, and shift register is cleared initialization.When the 0th clock cycle arrives, bit e ₀move into circuit, generator polynomial look-up table is according to e ₀=1 or 0 exports the 0th piece of row of F, the generator polynomial f of jth block row _{0, j}or b position null vector, the output of generator polynomial look-up table and content 0 mould 2 of shift register add, and e ₀f _{0, j}result (the 0+e of ring shift left 1 ₀f _{0, j}) ^{l (1)}deposit travelling backwards bit register.When the 1st clock cycle arrives, bit e ₁move into circuit, generator polynomial look-up table is according to e ₁=1 or 0 exports f _{0, j}or b position null vector, the output of generator polynomial look-up table and the content (0+e of shift register ₀f _{0, j}) ^{l (1)}mould 2 adds, and (0+e ₀f _{0, j}) ^{l (1)}+ e ₁f _{0, j}the result ((0+e of ring shift left 1 ₀f _{0, j}) ^{l (1)}+ e ₁f _{0, j}) ^{l (1)}deposit travelling backwards bit register.Above-mentioned selection-Jia-move to left-storing process proceeds down.At the end of b-1 clock cycle, bit e _b-1move into circuit, that now shift register stores is part and m ₀f _{0, j}, this is array section m ₀to p _jcontribution.When b clock cycle arrives, generator polynomial look-up table exports the 1st piece of row of F, the generator polynomial f of jth block row according to the data bit of vectorial m _{1, j}or b position null vector, repeat that above-mentioned selection-Jia-move to left-storing process.As array section m ₁when moving into circuit completely, that shift register stores is part and m ₀f _{0, j}+ m ₁f _{1, j}.Repeat said process, until the whole serial of whole vectorial m moves into circuit.Now, that shift register stores is verification section p _j.

Fig. 4 gives a kind of quasi cyclic matrix serial multiplier without multiplying be made up of 3 SASR circuit, is made up of generator polynomial look-up table, b position binary adder and shift register three kinds of functional modules.Generator polynomial look-up table L ₀, L ₁, L ₂circular matrix generator polynomial during all code check quasi-cyclic matrix F the 0th, 1,2 pieces that prestore respectively arrange and b position null vector.Generator polynomial look-up table L ₀, L ₁, L ₂output respectively with shift register R ₀, R ₁, R ₂content be added, these 3 nodulo-2 additions are respectively by b position binary adder A ₀, A ₁, A ₂complete.B position binary adder A ₀, A ₁, A ₂and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁, R ₂.

Generator polynomial look-up table L ₀, L ₁, L ₂store the circular matrix generator polynomial in all code check quasi-cyclic matrix F and b position null vector.Generator polynomial look-up table L ₀, L ₁store all generator polynomials in the 0th, the 1 piece of row of three kinds of code check F and b position null vector respectively, for arbitrary piece of row, store the 0th, 1 successively ..., the capable corresponding generator polynomial of u-1 block, finally stores 1 b position null vector.Generator polynomial look-up table L ₂store all generator polynomials in the 2nd piece of row of η=0.4 code check F and b position null vector, store the 0th, 1 successively ..., the capable corresponding generator polynomial of u-1 block, finally stores 1 b position null vector.

The invention provides a kind of quasi-cyclic matrix serial multiplication without multiplying, 3 kinds of code check QC-LDPC codes in its compatible DTMB standard, its multiplication step is described below:

1st step, resets shift register R ₀, R ₁, R ₂;

2nd step, input bit e _k(0≤k<u × b), generator polynomial look-up table L ₀, L ₁, L ₂according to e _k=1 or the 0 respectively generator polynomials of bit rate output η quasi-cyclic matrix F i-th=[k/b] the 0th, 1,2 pieces of row during (symbol [k/b] represents the maximum integer being not more than k/b), block was capable or b position null vector, generator polynomial look-up table L ₀, L ₁, L ₂output respectively by b position binary adder A ₀, A ₁, A ₂with shift register R ₀, R ₁, R ₂content be added, b position binary adder A ₀, A ₁, A ₂and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁, R ₂;

3rd step, with 1 for step-length increases progressively the value changing k, repetition the 2nd step u × b time, until whole vectorial m input is complete, now, shift register R ₀, R ₁..., R _u-1that store is verification section p respectively ₀, p ₁..., p _u-1, they constitute part and verify vectorial p=(p ₀, p ₁..., p _u-1).

Be not difficult to find out from above step, whole computational process needs u × b clock cycle altogether, identical with the existing multiplication scheme based on 3 SRAA-I circuit.

In DTMB standard, the existing solution of quasi-cyclic matrix serial multiplication needs the ROM of 2 889 bits to store the circular matrix generator polynomial of the 0th, the 1 piece of row of 3 kinds of code check quasi-cyclic matrix F respectively, and the ROM of 1 381 bit stores the circular matrix generator polynomial of the 2nd piece of row of η=0.4 code check F; And the present invention needs the ROM of 2 1016 bits to store the circular matrix generator polynomial of the 0th, the 1 piece of row of 3 kinds of code check quasi-cyclic matrix F respectively, the ROM of 1 508 bit stores the circular matrix generator polynomial of the 2nd piece of row of η=0.4 code check F.Although the ROM of the present invention is multiplex 3 × 127 bits, if realize generator polynomial look-up table with the block RAM in FPGA sheet, so due to inevitable waste, the memory of the actual use of the present invention does not increase.

In DTMB standard, the existing solution of quasi-cyclic matrix serial multiplication needs 762 registers, 381 two inputs inputs XOR gate with door and 381 two, and the present invention needs 381 registers, 0 two input and door and 381 two to input XOR gate.Two kinds of multiplication scheme expend the XOR gate of equal number, the present invention without the need to door, saved the register of 50%.

As fully visible, for the quasi-cyclic matrix serial multiplication in DTMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding, compared with existing solution, the present invention maintains identical speed, eliminate multiplying, without the need to door, employ the register of half, save a large amount of logical resources, had that structure is simple, power consumption is little, low cost and other advantages.

The above; be only one of the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the technical scope disclosed by the present invention; the change can expected without creative work or replacement, all should be encompassed within protection scope of the present invention.Therefore, the protection range that protection scope of the present invention should limit with claims is as the criterion.

Claims (4)

1. one kind without quasi cyclic matrix serial multiplier in the DTMB of multiplying, DTMB is the English abbreviation of digital television terrestrial broadcasting system, English full name is DigitalTelevisionTerrestrialMultimediaBroadcasting, the multiplying of vectorial m and quasi-cyclic matrix F is related to when adopting near lower triangular coding method to encode to DTMB standard multi code Rate of Chinese character QC-LDPC code, matrix F is divided into u block capable and u block row, is by u × u b × b rank circular matrix F _i,jthe array formed, f _i,jcircular matrix F _i,jgenerator polynomial, wherein, b, i, j and u are nonnegative integer, 0≤i<u, 0≤j<u, DTMB standard have employed the QC-LDPC code of 3 kinds of different code check η, η is 0.4,0.6,0.8 respectively, for these 3 kinds different code check QC-LDPC codes, all has b=127, the parameter u that 3 kinds of different code checks are corresponding is 3,2,2 respectively, vectorial m=(e ₀, e ₁..., e _{u × b-1}), be one section with b bit, part verifies vectorial p and is divided into u section, i.e. p=(p ₀, p ₁..., p _u-1), it is characterized in that, described multiplier comprises with lower component:

Generator polynomial look-up table L ₀, L ₁, L ₂, the 0th, 1,2 pieces of circular matrix generator polynomials arranged and b position null vector in all code check quasi-cyclic matrix F that prestores respectively;

B position binary adder A ₀, A ₁, A ₂, respectively to generator polynomial look-up table L ₀, L ₁, L ₂output and shift register R ₀, R ₁, R ₂content carry out mould 2 and add;

Shift register R ₀, R ₁, R ₂, store b position binary adder A respectively ₀, A ₁, A ₂and be recycled the move to left result after 1 and final verification section p ₀, p ₁, p ₂.

2. according to claim 1ly a kind ofly to it is characterized in that without quasi cyclic matrix serial multiplier in the DTMB of multiplying, described generator polynomial look-up table L ₀, L ₁store all generator polynomials in the 0th, the 1 piece of row of three kinds of code check F and b position null vector respectively, for arbitrary piece of row, store the 0th, 1 successively ..., the capable corresponding generator polynomial of u-1 block, finally stores 1 b position null vector.

3. according to claim 1ly a kind ofly to it is characterized in that without quasi cyclic matrix serial multiplier in the DTMB of multiplying, described generator polynomial look-up table L ₂store all generator polynomials in the 2nd piece of row of η=0.4 code check F and b position null vector, store the 0th, 1 successively ..., the capable corresponding generator polynomial of u-1 block, finally stores 1 b position null vector.

4. one kind without quasi-cyclic matrix serial multiplication method in the DTMB of multiplying, DTMB is the English abbreviation of digital television terrestrial broadcasting system, English full name is DigitalTelevisionTerrestrialMultimediaBroadcasting, the multiplying of vectorial m and quasi-cyclic matrix F is related to when adopting near lower triangular coding method to encode to DTMB standard multi code Rate of Chinese character QC-LDPC code, matrix F is divided into u block capable and u block row, is by u × u b × b rank circular matrix F _i,jthe array formed, f _i,jcircular matrix F _i,jgenerator polynomial, wherein, b, i, j and u are nonnegative integer, 0≤i<u, 0≤j<u, DTMB standard have employed the QC-LDPC code of 3 kinds of different code check η, η is 0.4,0.6,0.8 respectively, for these 3 kinds different code check QC-LDPC codes, all has b=127, the parameter u that 3 kinds of different code checks are corresponding is 3,2,2 respectively, vectorial m=(e ₀, e ₁..., e _{u × b-1}), be one section with b bit, part verifies vectorial p and is divided into u section, i.e. p=(p ₀, p ₁..., p _u-1), it is characterized in that, described multiplication method comprises the following steps:

1st step, resets shift register R ₀, R ₁, R ₂;

2nd step, input bit e _k, generator polynomial look-up table L ₀, L ₁, L ₂, according to e _k=1 or 0 respectively bit rate output η quasi-cyclic matrix F i-th=[k/b] block capable in the 0th, 1,2 pieces of row generator polynomials or all export b position null vector, generator polynomial look-up table L ₀, L ₁, L ₂output respectively by b position binary adder A ₀, A ₁, A ₂with shift register R ₀, R ₁, R ₂content be added, b position binary adder A ₀, A ₁, A ₂and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁, R ₂, wherein, 0≤k<u × b, symbol [k/b] represents the maximum integer being not more than k/b;

3rd step, with 1 for step-length increases progressively the value changing k, repetition the 2nd step u × b time, until whole vectorial m input is complete, now, shift register R ₀, R ₁..., R _u-1that store is verification section p respectively ₀, p ₁..., p _u-1, they constitute part and verify vectorial p=(p ₀, p ₁..., p _u-1).