CN106374939A - Secondary part parallel input right shift accumulation LDPC encoder - Google Patents
Secondary part parallel input right shift accumulation LDPC encoder Download PDFInfo
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- CN106374939A CN106374939A CN201610969004.XA CN201610969004A CN106374939A CN 106374939 A CN106374939 A CN 106374939A CN 201610969004 A CN201610969004 A CN 201610969004A CN 106374939 A CN106374939 A CN 106374939A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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Abstract
The invention provides a QC-LDPC encoder based on a secondary assembly line. The encoder comprises a multiplier of a sparse matrix and a vector and a multiplier of a vector and a high density matrix. The multiplier of the sparse matrix and the vector realizes multiplication of the sparse matrix and the vector. The multiplier of the vector and the high density matrix uses a part parallel input right shift accumulation mechanism to realize multiplication of the vector and the high density matrix. The whole coding process is divided into two levels of assembly line. The QC-LDPC encoder provided by the invention has the advantages of low cost, high throughput and the like.
Description
Technical field
The present invention relates to field of channel coding, move to right cumulative particularly to a kind of parallel input of second part in communication system
Qc-ldpc encoder.
Background technology
Low-density checksum (low-density parity-check, ldpc) code be efficient channel coding technology it
One, and quasi- circulation ldpc (quasi-cyclic ldpc, qc-ldpc) code is a kind of special ldpc code.The life of qc-ldpc code
Become matrix g and check matrix h to be all the array being made up of circular matrix, there is stages cycle, therefore be referred to as qc-ldpc
Code.The first trip of circular matrix is the result of footline ring shift right 1, and remaining each row is all the knot of its lastrow ring shift right 1
Really, therefore, circular matrix to be characterized by its first trip completely.Generally, the first trip of circular matrix is referred to as its generator polynomial.
Communication system generally adopts the qc-ldpc code of system form, and the left-half of its generator matrix g is a unit square
Battle array, right half part is by e × c b × b rank circular matrix gi,jThe array that (1≤i≤e, e < j≤t, t=e+c) is constituted, as follows
Shown:
Wherein, i is b × b rank unit matrix, and 0 is b × b rank full null matrix.The continuous b row of g and b row are known respectively as block
Row and block row.From formula (1), g has e block row and t block row.
At present, what qc-ldpc code was widely used is to add accumulator (type-i shift- based on c i type shift register
Register-adder-accumulator, sraa-i) circuit serial encoder.The serial being made up of c sraa-i circuit
Encoder, completed to encode within e × b clock cycle.The program needs 2 × c × b depositor, c × b two input and door
With c × b two input XOR gate in addition it is also necessary to e × c × b bit rom stores the generator polynomial of circular matrix.The program has two
Individual shortcoming: one is to need a large amount of memorizeies, leads to circuit cost high;Two is serial input information bit, and coding rate is slow.
Content of the invention
In communication system, the existing implementation of qc-ldpc encoder haves the shortcomings that high cost, coding rate are slow, for
These technical problems, the invention provides a kind of qc-ldpc encoder based on two-level pipeline.
As shown in figure 1, the qc-ldpc encoder based on two-level pipeline is mainly made up of 2 parts in communication system: sparse
Matrix and vectorial multiplier and the vectorial multiplier with high-density matrix.Cataloged procedure divides 2 steps to complete: the 1st step, using sparse
Matrix calculates vectorial s with the multiplier of vector;2nd step, calculates the vectorial p of verification using the multiplier of vector and high-density matrix.
Advantage and method with regard to the present invention can be further understood by following detailed description and accompanying drawings.
Brief description
Fig. 1 is the qc-ldpc cataloged procedure based on two-level pipeline;
Fig. 2 is the multiplier of sparse matrix and vector;
Fig. 3 is the functional block diagram that ii type shift register adds accumulator sraa-ii circuit;
Fig. 4 is that a kind of the input based on part parallel being made up of c sraa-ii circuit moves to right cumulative vector and high density
Matrix multiplier;
Fig. 5 summarizes hardware resource and process time needed for each coding step of encoder and whole cataloged procedure.
Specific embodiment
Below in conjunction with the accompanying drawings presently preferred embodiments of the present invention is elaborated, so that advantages and features of the invention can be more
It is easy to be readily appreciated by one skilled in the art, thus protection scope of the present invention is made apparent clearly defining.
The row weight of circular matrix and row heavy phase are same, are denoted as w.If w=0, then this circular matrix is full null matrix.If
W=1, then this circular matrix is replaceable, referred to as permutation matrix, it can be by positions some to unit matrix i ring shift right
Obtain.The check matrix h of qc-ldpc code is by c × t b × b rank circular matrix hj,k(1≤j≤c, 1≤k≤t, t=e+c)
The following array constituting:
Under normal circumstances, the arbitrary circular matrix in check matrix h is full null matrix (w=0) or being displacement square
Battle array (w=1).Make circular matrix hj,kFirst trip hj,k=(hj,k,1,hj,k,2,…,hj,k,b) it is its generator polynomial, wherein hj,k,m
=0 or 1 (1≤m≤b).Because h is sparse, hj,kOnly 1 ' 1 ', even without ' 1 '.
The front e block row of h are corresponding to be information vector a, and rear c block row are corresponding to be the vectorial p of verification, code word v=(a, p).With b
Bit is one section, and information vector a is divided into e section, i.e. a=(a1,a2,…,ae);The vectorial p of verification is divided into c section, i.e. p=
(p1,p2,…,pc).The matrix that the front e block row of h and rear c block row are constituted is denoted as c and d respectively, then
H=[c d] (3)
C is to be made up of c × e b × b rank circular matrix, and d is to be made up of c × c b × b rank circular matrix.By formula (3) and
Code word v=(a, p) substitutes into hvτ=0, arrangement can obtain
pτ=φτcaτ(4)
Wherein, φt=d–1, subscripttWith–1Represent transposition and inverse of a matrix respectively, d must full rank.It is known that Cyclic Moment
Battle array inverse, product and remain circular matrix.Therefore, φ is also the array being made up of circular matrix.But although matrix d is
Sparse, but φ is generally no longer sparse but highdensity.
Make st=catAnd pt=φtst, then p=s φ.Calculate the multiplication that s is related to sparse matrix and vector using c, using φ
Calculate the multiplication that p is related to vector and high-density matrix.From the above discussion, a kind of qc- based on two-level pipeline can be provided
Ldpc cataloged procedure, as shown in Figure 1.
Make s=(s1,s2,…,sc), then sj tIt is jth block row and a of matrix ctProduct, that is,
Wherein, 1≤i≤e, 1≤j≤c.sjThe n-th bit sj,n(1≤n≤b) is
Wherein, subscriptrs(n–1)Withls(n–1)Represent ring shift right n 1 and ring shift left n 1 respectively.Since arbitrary circulation
Matrix generator polynomial hj,iOnly a small amount of ' 1 ' even complete zero, then the inner product in formula (6) can be by posting to ring shift left
The tap of storage is sued for peace and to be realized, the multiplier of sparse matrix as shown in Figure 2 and vector.Sparse matrix and vectorial multiplier
By t b bit register r1,1,r1,2,…,r1,tWith c multi input XOR gate x1,1,x1,2,…,x1,cComposition.Depositor r1,1,
r1,2,…,r1,eFor loading and ring shift left message segment a1,a2,…,ae, depositor r1,e+1,r1,e+2,…,r1,tFor storing s
Array section s1,s2,…,sc.Partially connected in Fig. 2 depends on all circular matrix generator polynomials in matrix c.If
hj,i,m=1 (1≤m≤b), then message segment aiM bit be connected to XOR gate x1,j.Therefore, depositor r1,iAll take out
Head is depending on the nonzero element position of all circular matrix generator polynomials in i-th piece of row of matrix c, and multi input XOR gate
x1,jInput depend on matrix c jth block row in all circular matrix generator polynomials nonzero element position.If in c
All circular matrix generator polynomials have α ' 1 ', then sparse matrix needs use (α c) individual with the multiplier of vector
Two input XOR gates calculate s simultaneously1,n,s2,n,…,sc,n.S can calculate within b clock cycle and finish.Using sparse matrix with
The step that the multiplier of vector calculates vectorial s is as follows:
1st step, input information section a1,a2,…,ae, they are stored in respectively depositor r1,1,r1,2,…,r1,eIn;
2nd step, depositor r1,1,r1,2,…,r1,eRing shift left 1 time simultaneously, XOR gate x1,1,x1,2,…,x1,cRespectively will
XOR result moves to left into depositor r1,e+1,r1,e+2,…,r1,tIn;
3rd step, repeats the 2nd step b-1 time, after the completion of, depositor r1,e+1,r1,e+2,…,r1,tStorage content be respectively to
Amount section s1,s2,…,sc, they constitute vectorial s.
pt=φtstIt is equivalent to p=s φ.φ is by c × c b × b rank circular matrix φj,u(1≤j≤c,1≤u≤c)
The array constituting.Make circular matrix φj,uFirst trip gj,uIt is its generator polynomial.From p=s φ, u section verification vector is full
Foot
pu=s1φ1,u+s2φ2,u+…+sjφj,u+…+scφc,u(7)
Make generator polynomial gj,u=(gj,u,1,gj,u,2,…,gj,u,b), then φj,uCan be considered unit matrix ring shift right version
This weighted sum, that is,
φj,u=gj,u,1ir(0)+gj,u,2ir(1)+…+gj,u,bir(b-1)(8)
Wherein, subscriptr()Represent ring shift right.So, the jth item on the right of formula (7) equal sign is deployable is
Formula (9) is one and moves to right-the process of-multiply-add-storage, its realization adds accumulator (type- with ii type shift register
Iishift-register-adder-accumulator, sraa-ii) circuit.Fig. 3 is the functional block diagram of sraa-ii circuit, to
Amount s sends into this circuit with b bit parallel for one section.When with sraa-ii circuit to verification section puWhen (1≤u≤c) is encoded,
Generator polynomial look-up table prestores all generator polynomials of the u block row of matrix φ, and accumulator is cleared initialization.When
When 1st clock cycle arrives, array section s1Move into shift register, generator polynomial look-up table export the 1st piece of row of φ, the
Generator polynomial φ of u block row1,uThe 1st bit g1,u,1, and the content with shift registerCarry out scalar multiplication, productAdd with content 0 mould 2 of accumulator, andIt is stored back to accumulator.When arriving the 2nd clock cycle, shift LD
Device ring shift right 1, content is changed intoGenerator polynomial look-up table exports φ1,uThe 2nd bit g1,u,2, and post with displacement
The content of storageCarry out scalar multiplication, productContent with accumulatorMould 2 adds, and
It is stored back to accumulator.Above-mentioned move to right-- multiply-add-storing process proceeds down.At the end of b-th clock cycle, generate multinomial
Formula look-up table has exported φ1,uLast bit g1,u,b, now accumulator storage is part and s1φ1,u, this is vector
Section s1To puContribution.When arriving the b+1 clock cycle, array section s2Move into shift register, repeat above-mentioned move to right-take advantage of-
Plus-storing process.When generator polynomial look-up table has exported φ2,uLast bit g2,u,bWhen, accumulator storage is portion
Divide and s1φ1,u+s2φ2,u.Repeat said process, until entirely vectorial s all moves into circuit parallel.Now, accumulator stores
It is verification section pu.
Fig. 4 is given a kind of the input based on part parallel being made up of c sraa-ii circuit and moves to right cumulative vector and height
Density matrix multiplier, by shift register, generator polynomial look-up table, b position binary multiplier, b position binary adder
With five kinds of functional module compositions of accumulator.Shift register is to array section sj(1≤j≤c) ring shift right.Generator polynomial is searched
Table l1,l2,…,lcPrestore matrix φ the 1,2nd respectively ..., all circular matrix generator polynomials in c block row.Generator polynomial
Look-up table l1,l2,…,lcThe generator polynomial bit of output carries out scalar multiplication with the content of shift register respectively, this c mark
Amount multiplication passes through b position binary multiplier m respectively1,m2,…,mcComplete.B position binary multiplier m1,m2,…,mcProduct divide
Not and accumulator r1,r2,…,rcContent be added, this c nodulo-2 addition is respectively by b position binary adder a1,a2,…,ac
Complete.B position binary adder a1,a2,…,acAnd be stored in accumulator r respectively1,r2,…,rc.
Generator polynomial look-up table l1,l2,…,lcCircular matrix generator polynomial in storage matrix φ.Generator polynomial
Look-up table l1~lcAll generator polynomials in 1~c block row of storage φ, for any block row, store the 1st successively respectively,
2 ..., the corresponding generator polynomial of c block row.Generator polynomial look-up table l1~lcThe bit of Serial output generator polynomial.
The step calculating the vectorial p of verification using the multiplier of vector and high-density matrix is as follows:
1st step, resets accumulator r1,r2,…,rc;
2nd step, shift register input vector section sj(1≤j≤c);
3rd step, generator polynomial look-up table l1,l2,…,lcRespectively the 1,2nd in output matrix φ jth block row ..., c block arranges
Generator polynomial bit, these generator polynomial bits respectively pass through b position binary multiplier m1,m2,…,mcPost with displacement
The content of storage carries out scalar multiplication, b position binary multiplier m1,m2,…,mcProduct respectively pass through b position binary adder
a1,a2,…,acWith accumulator r1,r2,…,rcContent be added, b position binary adder a1,a2,…,acAnd be stored in respectively
Accumulator r1,r2,…,rc;
4th step, shift register ring shift right one, repeats the 3rd step b-1 time;
5th step, is incremented by, with 1 for step-length, the value changing j, repeats the 2nd~4 step c-1 time, until entirely vectorial s has inputted
Finish, now, accumulator r1,r2,…,rcStorage is verification section p respectively1,p2,…,pc, they constitute the vectorial p=of verification
(p1,p2,…,pc).
The invention provides a kind of qc-ldpc coded method based on two-level pipeline is it is adaptable to qc- in communication system
Ldpc code, its coding step is described as follows:
1st step, calculates vectorial s using the multiplier of sparse matrix and vector;
2nd step, calculates the vectorial p of verification using the multiplier of vector and high-density matrix.
When Fig. 5 summarizes the hardware resource consumption needed for each coding step of encoder and whole cataloged procedure and processes
Between.
It is not difficult to find out from Fig. 5, when streamline is full of, whole cataloged procedure needs max (t c+b, cb)=cb clock week altogether
Phase, as c, < during e, required time is less than the e × b clock cycle needed for serial encoding method based on c sraa-i circuit.
In communication system, the existing solution of qc-ldpc encoder needs e × c × b bit rom, and the present invention needs
c2B bit rom.As c, < during e, the present invention needs less rom.
As fully visible, as c, < during e, compared with traditional serial sraa method, the present invention has that coding rate is fast, memorizer disappears
The advantages of consumption is few.
The above, only one of specific embodiment of the present invention, but protection scope of the present invention is not limited thereto,
Any those of ordinary skill in the art disclosed herein technical scope in, the change that can expect without creative work
Change or replace, all should be included within the scope of the present invention.Therefore, protection scope of the present invention should be with claims
The protection domain being limited is defined.
Claims (4)
1. a kind of qc-ldpc encoder based on two-level pipeline, the check matrix h of qc-ldpc code is by c × t b × b rank
The array that circular matrix is constituted, wherein, c, t and b are all positive integer, t=e+c, and check matrix h can be divided into 2 submatrixs, h
=[c d], c are to be made up of c × e b × b rank circular matrix, and d is to be made up of c × c b × b rank circular matrix, φt=d–1,
Wherein, subscriptτWith-1Represent transposition and inverse, matrix c corresponding informance vector a, the vectorial p of the corresponding verification of matrix d respectively, with b bit be
One section, information vector a is divided into e section, i.e. a=(a1,a2,…,ae), the vectorial p of verification is divided into c section, i.e. p=(p1,
p2,…,pc), st=cat, p=s φ, vectorial s is divided into c section, i.e. s=(s1,s2,…,sc) it is characterised in that described volume
Code device includes with lower component:
Sparse matrix and vectorial multiplier, by t b bit register r1,1,r1,2,…,r1,tWith c multi input XOR gate
x1,1,x1,2,…,x1,cComposition, for calculating vectorial s;
Vector and the multiplier of high-density matrix, move to right cumulative mechanism based on part parallel input, many by shift register, generation
Item formula look-up table, b position binary multiplier, b position binary adder and accumulator composition, for calculating the vectorial p of verification, shift
Register pair array section sjRing shift right, generator polynomial look-up table l1,l2,…,lcPrestore matrix φ the 1,2nd respectively ..., c block
All circular matrix generator polynomials in row, generator polynomial look-up table l1,l2,…,lcThe generator polynomial bit of output divides
Other and shift register content carries out scalar multiplication, and this c scalar multiplication passes through b position binary multiplier m respectively1,m2,…,mc
Complete, b position binary multiplier m1,m2,…,mcProduct respectively with accumulator r1,r2,…,rcContent be added, this c mould 2
Addition passes through b position binary adder a respectively1,a2,…,acComplete, b position binary adder a1,a2,…,acAnd deposit respectively
Enter accumulator r1,r2,…,rc, wherein, 1≤j≤c.
2. a kind of qc-ldpc encoder based on two-level pipeline according to claim 1 is it is characterised in that described dilute
Thin matrix is as follows with the step of the vectorial s of multiplier calculating of vector:
1st step, input information section a1,a2,…,ae, they are stored in respectively depositor r1,1,r1,2,…,r1,eIn;
2nd step, depositor r1,1,r1,2,…,r1,eRing shift left 1 time simultaneously, XOR gate x1,1,x1,2,…,x1,cRespectively by XOR
Result moves to left into depositor r1,e+1,r1,e+2,…,r1,tIn;
3rd step, repeats the 2nd step b-1 time, after the completion of, depositor r1,e+1,r1,e+2,…,r1,tThe content of storage is array section respectively
s1,s2,…,sc, they constitute vectorial s.
3. a kind of qc-ldpc encoder based on two-level pipeline according to claim 1 it is characterised in that described to
Amount is as follows with the step of the vectorial p of multiplier calculating verification of high-density matrix:
1st step, resets accumulator r1,r2,…,rc;
2nd step, shift register input vector section sj, wherein, 1≤j≤c;
3rd step, generator polynomial look-up table l1,l2,…,lcRespectively the 1,2nd in output matrix φ jth block row ..., the life of c block row
Become multinomial bit, these generator polynomial bits pass through b position binary multiplier m respectively1,m2,…,mcWith shift register
Content carry out scalar multiplication, b position binary multiplier m1,m2,…,mcProduct respectively pass through b position binary adder a1,
a2,…,acWith accumulator r1,r2,…,rcContent be added, b position binary adder a1,a2,…,acAnd respectively be stored in cumulative
Device r1,r2,…,rc;
4th step, shift register ring shift right one, repeats the 3rd step b-1 time;
5th step, is incremented by, with 1 for step-length, the value changing j, repeats the 2nd~4 step c-1 time, until entirely vectorial s input finishes, this
When, accumulator r1,r2,…,rcStorage is verification section p respectively1,p2,…,pc, they constitute the vectorial p=(p of verification1,
p2,…,pc).
4. a kind of qc-ldpc coded method based on two-level pipeline, the check matrix h of qc-ldpc code is by c × t b × b
The array that rank circular matrix is constituted, wherein, c, t and b are all positive integer, t=e+c, and check matrix h can be divided into 2 submatrixs,
H=[c d], c are to be made up of c × e b × b rank circular matrix, and d is to be made up of c × c b × b rank circular matrix, φt=d–1,
Wherein, subscriptτWith-1Represent transposition and inverse, matrix c corresponding informance vector a, the vectorial p of the corresponding verification of matrix d respectively, with b bit be
One section, information vector a is divided into e section, i.e. a=(a1,a2,…,ae), the vectorial p of verification is divided into c section, i.e. p=(p1,
p2,…,pc), st=cat, p=s φ, vectorial s is divided into c section, i.e. s=(s1,s2,…,sc) it is characterised in that described volume
Code method comprises the following steps:
1st step, calculates vectorial s using the multiplier of sparse matrix and vector;
2nd step, calculates the vectorial p of verification using the multiplier of vector and high-density matrix.
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