CN106452457A - Two-level full parallel input ring-shift-left LDPC (Low-Density Parity-Check) encoder in WPAN - Google Patents

Abstract

The invention provides a QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) encoder based on two levels of pipelines in WPAN. The encoder comprises a multiplier for a sparse matrix and a vector and a multiplier for a vector and a high-density matrix. The multiplier for the sparse matrix and the vector implements multiplication of the sparse matrix and the vector; and the multiplier for the vector and the high-density matrix adopts a full parallel input ring-shift-left mechanism, and implements multiplication of the vector and the high-density matrix. The entire encoding process is partitioned into two levels of pipelines. The 7/8 code rate QC-LDPC encoder in a WPAN system has the advantages of high working efficiency, large throughput and the like.

Description

The LDPC encoder of two grades of full parellel input ring shift lefts in WPAN

Technical field

The present invention relates to two grades of full parellel input ring shift lefts in field of channel coding, more particularly to a kind of WPAN system QC-LDPC encoder.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The life of QC-LDPC code It is all the array being made up of circular matrix to become matrix G and check matrix H, have the characteristics that stages cycle, therefore is referred to as QC-LDPC Code.The first trip of circular matrix is the result of footline ring shift right 1, and remaining each row is all the knot of its lastrow ring shift right 1 Really, therefore, circular matrix is characterized by its first trip completely.Generally, the first trip of circular matrix is referred to as its generator polynomial.

Communication system is generally using the QC-LDPC code of system form, and the left-half of its generator matrix G is a unit square Battle array, right half part be by e × c b × b rank circular matrix G_i,j(1≤i≤e,e<J≤t, t=e+c) array that constitutes, as follows Shown：

Wherein, I is b × b rank unit matrix, and 0 is b × b rank full null matrix.The continuous b row of G and b row are known respectively as block Row and block row.From formula (1), G has e block row and t block row.Information vector a=(a₁,a₂,…,a_e×b).WPAN standard is employed A kind of QC-LDPC code of code check η=7/8, for the code, t=32, e=28, c=4, b=21.

In WPAN standard, the existing full parellel input solution of 7/8 code check QC-LDPC encoder is as shown in figure 1, the party The major defect of case is that modulo 2 adder has e × b input, and the time delay of additive operation is long, can cause the operating frequency of encoder Low, handling capacity is little.

Content of the invention

In WPAN system, the existing implementation of 7/8 code check QC-LDPC encoder has that operating frequency is low, handling capacity is little Shortcoming, for these technical problems, the invention provides a kind of QC-LDPC encoder based on two-level pipeline.

As shown in Fig. 2 the QC-LDPC encoder in WPAN system based on two-level pipeline is mainly made up of 2 parts：Sparse The multiplier of multiplier and vector and high-density matrix of the matrix with vector.Cataloged procedure divides 2 steps to complete：1st step, using sparse Matrix calculates vector s with the multiplier of vector；2nd step, calculates verification vector p using multiplier of the vector with high-density matrix.

Advantage and method with regard to the present invention can be further understood by following detailed description and accompanying drawings.

Description of the drawings

Fig. 1 is existing full parellel input QC-LDPC encoder；

Fig. 2 is the QC-LDPC cataloged procedure based on two-level pipeline；

Fig. 3 is the multiplier of sparse matrix and vector；

Fig. 4 is a kind of vector based on full parellel input ring shift left and high-density matrix multiplier.

Specific embodiment

Below in conjunction with the accompanying drawings presently preferred embodiments of the present invention is elaborated, so that advantages and features of the invention can be more It is easy to be readily appreciated by one skilled in the art, apparent clearly defines so as to make to protection scope of the present invention.

The row weight of circular matrix and row heavy phase are same, are denoted as w.If w=0, then the circular matrix is full null matrix.If W=1, then the circular matrix is replaceable, referred to as permutation matrix, and it can be by some positions of unit matrix I ring shift right Obtain.The check matrix H of QC-LDPC code be by c × t b × b rank circular matrix H_j,k(1≤j≤c, 1≤k≤t, t=e+c) The following array for constituting：

Under normal circumstances, the arbitrary circular matrix in check matrix H is full null matrix (w=0) or being displacement square Battle array (w=1).Make circular matrix H_j,kFirst trip h_j,k=(h_j,k,1,h_j,k,2,…,h_j,k,b) it is its generator polynomial, wherein h_j,k,m =0 or 1 (1≤m≤b).Because H is sparse, h_j,kOnly 1 ' 1 ', even without ' 1 '.

It is information vector a that the front e block row of H are corresponding, and it is verification vector p that rear c block row are corresponding, code word v=(a, p).With b Bit is one section, and information vector a is divided into e section, i.e. a=(a₁,a₂,…,a_e)；Verification vector p is divided into c section, i.e. p= (p₁,p₂,…,p_c).The matrix that the front e block row of H and rear c block row are constituted is denoted as C and D respectively, then

H=[C D] (3)

C is made up of c × e b × b rank circular matrix, and D is made up of c × c b × b rank circular matrix.By formula (3) and Code word v=(a, p) substitutes into Hv^T=0, arrangement can be obtained

p^T=Φ^TCa^T(4)

Wherein, Φ^T=D^–1, subscript^TWith^–1Represent transposition and inverse of a matrix respectively, D must full rank.It is well known that Cyclic Moment Battle array inverse, product and remain circular matrix.Therefore, Φ is also the array being made up of circular matrix.But, although matrix D is Sparse, but Φ is generally no longer sparse but highdensity.

Make s^T=Ca^TAnd p^T=Φ^Ts^T, then p=s Φ.Calculate, using C, the multiplication that s is related to sparse matrix and vector, using Φ Calculate the multiplication that p is related to vector and high-density matrix.From the above discussion, a kind of QC- based on two-level pipeline can be given LDPC cataloged procedure, as shown in Figure 2.

Make s=(s₁,s₂,…,s_c), then s_j ^TIt is jth block row and a of Matrix C^TProduct, i.e.,

Wherein, 1≤i≤e, 1≤j≤c.s_jThe n-th bit s_j,n(1≤n≤b) is

Wherein, subscript^rs(n–1)With^ls(n–1)Represent ring shift right n 1 and ring shift left n 1 respectively.Since arbitrary circulation Matrix generator polynomial h_j,iOnly a small amount of ' 1 ' even complete zero, then the inner product in formula (6) can be by posting to ring shift left The tap of storage sues for peace to realize, the multiplier of sparse matrix as shown in Figure 3 and vector.Sparse matrix and vectorial multiplier By t b bit register R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition.Depositor R_1,1, R_1,2,…,R_1,eFor loading and ring shift left message segment a₁,a₂,…,a_e, depositor R_1,e+1,R_1,e+2,…,R_1,tFor storing s Array section s₁,s₂,…,s_c.Partially connected in Fig. 3 is depending on all circular matrix generator polynomials in Matrix C.If h_j,i,m=1 (1≤m≤b), then message segment a_iM bit be connected to XOR gate X_1,j.Therefore, depositor R_1,iAll take out Head is depending on the nonzero element position of all circular matrix generator polynomials in i-th piece of row of Matrix C, and multi input XOR gate X_1,jInput depending on all circular matrix generator polynomials in Matrix C jth block row nonzero element position.If in C All circular matrix generator polynomials have α ' 1 ', then sparse matrix needs to use (α c) individual with the multiplier of vector Two input XOR gates are while calculate s_1,n,s_2,n,…,s_c,n.S can be calculated within b clock cycle and be finished.Using sparse matrix with The step of multiplier of vector calculates vector s is as follows：

1st step, input information section a₁,a₂,…,a_e, they are stored in depositor R respectively_1,1,R_1,2,…,R_1,eIn；

2nd step, depositor R_1,1,R_1,2,…,R_1,eWhile ring shift left 1 time, XOR gate X_1,1,X_1,2,…,X_1,cRespectively will XOR result is moved to left into depositor R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 time, after the completion of, depositor R_1,e+1,R_1,e+2,…,R_1,tThe content of storage be respectively to Amount section s₁,s₂,…,s_c, they constitute vectorial s.

p^T=Φ^Ts^TIt is equivalent to p=s Φ.Φ be by c × c b × b rank circular matrix Φ_j,u(1≤j≤c,1≤u≤c) The array of composition.Make circular matrix Φ_j,uFirst trip g_j,uIt is its generator polynomial.From p=s Φ, u section verification vector is full Foot

p_u=s₁Φ_1,u+s₂Φ_2,u+…+s_jΦ_j,u+…+s_cΦ_c,u(7)

Make generator polynomial g_j,u=(g_j,u,1,g_j,u,2,…,g_j,u,b), then Φ_j,uCan be considered unit matrix ring shift right version This weighted sum, i.e.,

Φ_j,u=g_j,u,1I^r(0)+g_j,u,2I^r(1)+…+g_j,u,bI^r(b-1)(8)

Wherein, subscript^r()Represent ring shift right.So, jth item on the right of formula (7) equal sign is deployable to be

Since by s_jRing shift right n position is equivalent to its ring shift left b-n position, i.e.,Wherein, subscript^l()Table Show ring shift left, then formula (9) is rewritable to be

Formula (10) is substituted into formula (7), arrangement can be obtained

Formula (11) is the process of a-multiply-add-move to left-store, and can derive and a kind of be input into ring shift left based on full parellel Vector and high-density matrix multiplier.Fig. 4 is its functional block diagram, by generator polynomial look-up table, b position binary multiplier, (c+1) position binary adder and four kinds of functional module compositions of shift register.Generator polynomial look-up table L₁,L₂,…,L_cPoint Do not prestore matrix Φ the 1,2nd ..., all circular matrix generator polynomials in c block row.Generator polynomial look-up table L₁,L₂,…, L_cThe generator polynomial bit of output respectively with array section s₁,s₂,…,s_cScalar multiplication is carried out, this c scalar multiplication passes through b respectively Position binary multiplier M₁,M₂,…,M_cComplete.B position binary multiplier M₁,M₂,…,M_cProduct and shift register R in Hold and be added, the addition is by b (c+1) position binary adder A₁,A₂,…,A_bComplete.(c+1) position binary adder A₁, A₂,…,A_bAnd shift register R is stored in by the result after ring shift left 1.

Generator polynomial look-up table L₁,L₂,…,L_cPrestore the circular matrix generator polynomial of matrix Φ.Generator polynomial is looked into Look for table L₁～L_cAll generator polynomials in 1～c block row of storage Φ, for any block row, store the 1st successively respectively, 2 ..., c block arranges corresponding generator polynomial.Generator polynomial look-up table L₁～L_cThe bit of Serial output generator polynomial.

The step of verification vector p being calculated using vector and the multiplier of high-density matrix is as follows：

1st step, full parellel input vector s；

2nd step, resets shift register R；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1st in output matrix Φ u (1≤u≤c) block row, The generator polynomial bit of 2 ..., c block row, these generator polynomial bits pass through b position binary multiplier M respectively₁,M₂,…, M_cWith message segment s₁,s₂,…,s_cCarry out scalar multiplication, b position binary multiplier M₁,M₂,…,M_cProduct by b (c+1) position Binary adder A₁,A₂,…,A_bIt is added with the content of shift register R, (c+1) position binary adder A₁,A₂,…,A_b's Shift register R is stored in result after ring shift left 1；

4th step, repeats the 3rd step b-1 time, and now, shift register R storage is verification section p_u；

5th step, is incremented by, with 1 as step-length, the value for changing u, repeats the 2nd～4 step c-1 time, and shift register R is obtained successively Be verification section p₁,p₂,…,p_c, they constitute verification vector p=(p₁,p₂,…,p_c).

The invention provides a kind of QC-LDPC coded method based on two-level pipeline, it is adaptable to 7/8 in WPAN system Code check QC-LDPC code, its coding step is described as follows：

1st step, calculates vector s using multiplier of the sparse matrix with vector；

2nd step, calculates verification vector p using multiplier of the vector with high-density matrix.

Existing solution needs 1 e × b position modulo 2 adder, and the second level circuit of the present invention is average by nodulo-2 addition It is allocated to b (c+1) position modulo 2 adder.For 7/8 code check QC-LDPC encoder in WPAN standard, (c+1) is far smaller than e ×b.It can be seen that, the adder time delay of the present invention is much smaller than existing solution.

As fully visible, for 7/8 code check QC-LDPC encoder in WPAN standard, compared with existing solution, the present invention The time delay of logic circuit is highly shortened, big have the advantages that operating frequency height, handling capacity.

The above, only one of specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, Any those of ordinary skill in the art disclosed herein technical scope in, the change that can expect without creative work Change or replace, should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with claims The protection domain for being limited is defined.

Claims (4)

1. the QC-LDPC encoder in a kind of WPAN based on two-level pipeline, the check matrix H of 7/8 code check QC-LDPC code be by The array that c × t b × b rank circular matrix is constituted, wherein, c=4, t=32, b=21, e=t-c=28, check matrix H can be drawn Be divided into 2 submatrixs, H=[C D], C is made up of c × e b × b rank circular matrix, D be by c × c b × b rank Cyclic Moment Battle array is constituted, Φ^T=D^–1, wherein, subscript^TWith^-1Represent transposition and inverse, Matrix C corresponding informance vector a respectively, matrix D corresponds to verification Vectorial p, with b bit as one section, information vector a is divided into e section, i.e. a=(a₁,a₂,…,a_e), verification vector p is divided into c Section, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s is divided into c section, i.e. s=(s₁,s₂,…,s_c), its feature It is, the encoder is included with lower component：

Sparse matrix and vectorial multiplier, by t b bit register R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition, for calculating vectorial s；

Vector and the multiplier of high-density matrix, are input into ring shift left mechanism based on full parellel, by generator polynomial look-up table, b Position binary multiplier, (c+1) position binary adder and shift register composition, for calculating verification vector p, generate multinomial Formula look-up table L₁,L₂,…,L_cThe all circular matrix generator polynomials for being prestored in matrix Φ the 1st, 2 ..., c block row respectively, generate Multinomial look-up table L₁,L₂,…,L_cThe generator polynomial bit of output respectively with array section s₁,s₂,…,s_cScalar multiplication is carried out, this C scalar multiplication passes through b position binary multiplier M respectively₁,M₂,…,M_cComplete, b position binary multiplier M₁,M₂,…,M_c's Product is added with the content of shift register R, and the addition is by b (c+1) position binary adder A₁,A₂,…,A_bComplete, (c + 1) position binary adder A₁,A₂,…,A_bAnd shift register R is stored in by the result after ring shift left 1.

2. the QC-LDPC encoder in a kind of WPAN according to claim 1 based on two-level pipeline, it is characterised in that The step of sparse matrix calculates vector s with the multiplier of vector is as follows：

1st step, input information section a₁,a₂,…,a_e, they are stored in depositor R respectively_1,1,R_1,2,…,R_1,eIn；

2nd step, depositor R_1,1,R_1,2,…,R_1,eWhile ring shift left 1 time, XOR gate X_1,1,X_1,2,…,X_1,cRespectively by XOR As a result move to left into depositor R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 time, after the completion of, depositor R_1,e+1,R_1,e+2,…,R_1,tThe content of storage is array section respectively s₁,s₂,…,s_c, they constitute vectorial s.

3. the QC-LDPC encoder in a kind of WPAN according to claim 1 based on two-level pipeline, it is characterised in that The step of vector calculates verification vector p with the multiplier of high-density matrix is as follows：

1st step, full parellel input vector s；

2nd step, resets shift register R；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ u (1≤u≤c) block row ..., The generator polynomial bit of c block row, these generator polynomial bits pass through b position binary multiplier M respectively₁,M₂,…,M_cWith letter Breath section s₁,s₂,…,s_cCarry out scalar multiplication, b position binary multiplier M₁,M₂,…,M_cProduct by b (c+1) position binary system Adder A₁,A₂,…,A_bIt is added with the content of shift register R, (c+1) position binary adder A₁,A₂,…,A_bAnd followed Ring moves to left the result after 1 and is stored in shift register R；

4th step, repeats the 3rd step b-1 time, and now, shift register R storage is verification section p_u；

5th step, is incremented by, with 1 as step-length, the value for changing u, repeats the 2nd～4 step c-1 time, and what shift register R was obtained successively is Verification section p₁,p₂,…,p_c, they constitute verification vector p=(p₁,p₂,…,p_c).

4. the QC-LDPC coded method in a kind of WPAN based on two-level pipeline, the check matrix H of 7/8 code check QC-LDPC code is The array being made up of c × t b × b rank circular matrix, wherein, c=4, t=32, b=21, e=t-c=28, check matrix H can 2 submatrixs, H=[C D] are divided into, C is made up of c × e b × b rank circular matrix, D is circulated by c × c b × b rank Matrix is constituted, Φ^T=D^–1, wherein, subscript^TWith^-1Represent transposition and inverse, Matrix C corresponding informance vector a respectively, matrix D corresponds to school Vectorial p is tested, with b bit as one section, information vector a is divided into e section, i.e. a=(a₁,a₂,…,a_e), vector p is halved for verification For c section, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s is divided into c section, i.e. s=(s₁,s₂,…,s_c), which is special Levy and be, the coded method is comprised the following steps：

1st step, calculates vector s using multiplier of the sparse matrix with vector；

2nd step, calculates verification vector p using multiplier of the vector with high-density matrix.