CN103236859B - Share the quasi-cyclic LDPC serial encoder of memory mechanism - Google Patents

Abstract

The invention provides a kind of quasi-cyclic LDPC serial encoder based on shared memory mechanism, this encoder comprise 1 prestore the generator polynomial look-up table of all circular matrix generator polynomials in generator matrix, the c position delayer of 1 slip store information bits, the b digit buffer of a c buffer memory generator polynomial, c carries out the b position binary multiplier of scalar multiplication to information bit and generator polynomial, c carries out to sum of products shift register content b position binary adder that mould 2 adds, a c storage be recycled move to left 1 and b bit shift register.Finally, checking data is contained in c shift register.Serial encoder provided by the invention has that power consumption is little, structure is simple, memory consumption is few, low cost and other advantages.

Description

Share the quasi-cyclic LDPC serial encoder of memory mechanism

Technical field

The present invention relates to field of channel coding, particularly the serial encoder of quasi-cyclic LDPC code in a kind of communication system.

Background technology

Low-density checksum (Low-DensityParity-Check, LDPC) code is one of efficient channel coding technology, and quasi-cyclic LDPC (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code.The generator matrix G of QC-LDPC code and check matrix H are all the arrays be made up of circular matrix, have the feature of stages cycle, therefore are called as quasi-cyclic LDPC code.The first trip of circular matrix is the result of footline ring shift right 1, and all the other each provisional capitals are results of its lastrow ring shift right 1, and therefore, circular matrix is characterized by its first trip completely.Usually, the first trip of circular matrix is called as its generator polynomial.

Communication system adopts the QC-LDPC code of system form usually, and the left-half of its generator matrix G is a unit matrix, and right half part is by a × c b × b rank circular matrix G _{i, j}the array that (0≤i<a, a≤j<t, t=a+c) is formed, as follows:

Wherein, I is b × b rank unit matrixs, and 0 is the full null matrix in b × b rank.The continuous b of G capable and b row are called as the capable and block row of block respectively.From formula (1), G has a block capable and t block row.Make g _i,jcircular matrix G _i,jgenerator polynomial.

The corresponding code word v=(s, p) of generator matrix G, that the front a block row of G are corresponding is information vector s=(e ₀, e ₁..., e _{a × b-1}), that rear c block row are corresponding is the vectorial p=(d of verification ₀, d ₁..., d _{c × b-1}).Be one section with b bit, information vector s is divided into a section, i.e. s=(s ₀, s ₁..., s _a-1); Verify vectorial p and be divided into c section, be i.e. p=(p ₀, p ₁..., p _c-1).From v=sG, jth-a section verification vector meets

p _j-a＝s ₀G _0,j+s ₁G _1,j+…+s _iG _i,j+…+s _a-1G _a-1,j(c)

Wherein, 0≤i<a, a≤j<t, t=a+c.Order with generator polynomial g respectively _i,jthe result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.So, i-th on the right of formula (c) equal sign deployable is

$s_i{G}_{i,j}=e_{i\&times;b}{g}_{i,j}^{r\left(0\right)}+e_{i\&times;b+1}{g}_{i,j}^{r\left(1\right)}+\&CenterDot;\&CenterDot;\&CenterDot;+e_{i\&times;b+b-1}{g}_{i,j}^{r(b-1)}---\left(3\right)$

At present, what QC-LDPC serial code extensively adopted is the scheme adding accumulator (Type-IShift-Register-Adder-Accumulator, SRAA-I) circuit based on c I type shift register.Fig. 1 is the functional block diagram of single SRAA-I circuit, and information vector s by turn serial sends into this circuit.When with SRAA-I circuit to verification section p _j-awhen (a≤j<t) encodes, generator polynomial look-up table prestores all generator polynomials of the jth block row of generator matrix G, and accumulator is cleared initialization.When the 0th clock cycle arrives, shift register loads the 0th piece of row of G, the generator polynomial of jth block row from generator polynomial look-up table information bit e ₀move into circuit, and with the content of shift register carry out scalar multiplication, product add with content 0 mould 2 of accumulator, and deposit back accumulator.When the 1st clock cycle arrives, shift register ring shift right 1, content becomes information bit e ₁move into circuit, and with the content of shift register carry out scalar multiplication, product with the content of accumulator mould 2 adds, and deposit back accumulator.Above-mentioned-the Jia that moves to right-take advantage of-storing process proceeds down.At the end of b-1 clock cycle, information bit e _b-1move into circuit, that now accumulator stores is part and s ₀g _{0, j}, this is message segment s ₀to p _j-acontribution.When b clock cycle arrives, shift register loads the 1st piece of row of G, the generator polynomial of jth block row from generator polynomial look-up table repeat the above-mentioned-Jia that moves to right-take advantage of-storing process.As message segment s ₁when moving into circuit completely, that accumulator stores is part and s ₀g _{0, j}+ s ₁g _{1, j}.Repeat said process, until the whole serial of whole information vector s moves into circuit.Now, that accumulator stores is verification section p _j-a.Use the serial encoder shown in c SRAA-I circuit energy pie graph 2, it obtains c verification section within a × b clock cycle simultaneously.The program needs 2 × c × b register, c × b two inputs to input XOR gate with door and c × b individual two, also needs c a × b bit ROM to store the generator polynomial of circular matrix.

In communication system, the existing solution of QC-LDPC serial code is based on c SRAA-I circuit, the program has two shortcomings: one is that shift register is in each clock cycle or load new generator polynomial, ring shift right 1, cause the storage content of single register constantly to change, and then cause the power consumption of circuit large; Two is that the generator polynomial of circular matrix is dispersed in multiple ROM, as everyone knows, when realizing ROM with the memory in FPGA sheet, inevitably cause the waste of memory, the more wastes of ROM number are more serious, certainly will cause that the memory of circuit is large, cost is high.

Summary of the invention

In communication system there is the shortcoming that power consumption is high, memory is large, cost is high in the existing implementation of QC-LDPC serial code, for these technical problems, the invention provides a kind of serial encoder based on shared memory mechanism.

As shown in Figure 4, in communication system, the serial encoder of QC-LDPC code forms primarily of 6 parts: generator polynomial look-up table, buffer, b position binary multiplier, b position binary adder, shift register and delayer.Cataloged procedure divides 5 steps to complete: the 1st step, resets delayer D and shift register R ₀, R ₁..., R _c-1, buffer B _j-aload the generator polynomial g of generator matrix G i-th piece of row, jth block row from generator polynomial look-up table when i-th × b+j-a clock cycle arrives _i,j, and remain unchanged in other moment; 2nd step, when a kth clock cycle arrives, delayer D input information bits e _k(0≤k<a × b), buffer B ₀, B ₁..., B _c-1in generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _c-1with the data bit D in delayer D ₀, D ₁..., D _c-1carry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M _c-1product respectively by b position binary adder A ₀, A ₁..., A _c-1with shift register R ₀, R ₁..., R _c-1content be added, b position binary adder A ₀, A ₁..., A _c-1and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁..., R _c-1; 3rd step, with 1 for step-length increases progressively the value changing k, repetition the 2nd step a × b time, until whole information vector s inputs complete; 4th step, when the clock cycle arrives, delayer D inputs filling bit 0, buffer B ₀, B ₁..., B _c-1in generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _c-1with the data bit D in delayer D ₀, D ₁..., D _c-1carry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M _c-1product respectively by b position binary adder A ₀, A ₁..., A _c-1with shift register R ₀, R ₁..., R _c-1content be added, b position binary adder A ₀, A ₁..., A _c-1and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁..., R _c-1; 5th step, repeats the 4th step c time, until c filling bit 0 inputs complete, now, and shift register R ₀, R ₁..., R _c-1that store is verification section p respectively ₀, p ₁..., p _c-1, they constitute the vectorial p=(p of verification ₀, p ₁..., p _c-1).

Serial encoder structure provided by the invention is simple, under substantially keeping coding rate and logical resource to expend constant condition, can reduce power consumption, reduce storage requirement, cost-saving.

Be further understood by detailed description and accompanying drawings below about advantage of the present invention and method.

Accompanying drawing explanation

Fig. 1 is the functional block diagram that I type shift register adds accumulator SRAA-I circuit;

Fig. 2 is the QC-LDPC serial encoder be made up of c SRAA-I circuit;

Fig. 3 is the functional block diagram that buffer adds shift register BASR circuit;

Fig. 4 is a kind of QC-LDPC serial encoder based on shared memory mechanism be made up of c BASR circuit.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment of the present invention is elaborated, can be easier to make advantages and features of the invention be readily appreciated by one skilled in the art, thus more explicit defining is made to protection scope of the present invention.

Since by the generator polynomial g of circular matrix _i,jring shift right n position is equivalent to its ring shift left b-n position, namely $g_{i,j}^{r\left(n\right)}=g_{i,j}^{l(b-n)},$ So formula (3) can be rewritten as

$s_i{G}_{i,j}=e_{i\&times;b}{g}_{i,j}^{l\left(b\right)}+e_{i\&times;b+1}{g}_{i,j}^{l(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+e_{i\&times;b+b-1}{g}_{i,j}^{l\left(1\right)}$

$={\left(e_{i\&times;b}{g}_{i,j}\right)}^{l\left(b\right)}+{\left(e_{i\&times;b+1}{g}_{i,j}\right)}^{l(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+{\left(e_{i\&times;b+b-1}{g}_{i,j}\right)}^{l\left(1\right)}$

$={(0+e_{i\&times;b}{g}_{i,j})}^{l\left(b\right)}+{\left(e_{i\&times;b+1}{g}_{i,j}\right)}^{l(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+{\left(e_{i\&times;b+b-1}{g}_{i,j}\right)}^{l\left(1\right)}---\left(4\right)$

$={({(0+e_{i\&times;b}{g}_{i,j})}^{l\left(1\right)}+e_{i\&times;b+1}{g}_{i,j})}^{l(b-1)}+\&CenterDot;\&CenterDot;\&CenterDot;+{\left(e_{i\&times;b+b-1}{g}_{i,j}\right)}^{l\left(1\right)}$

$={(\&CenterDot;\&CenterDot;\&CenterDot;{({(0+e_{i\&times;b}{g}_{i,j})}^{l\left(1\right)}+e_{i\&times;b+1}{g}_{i,j})}^{l\left(1\right)}+\&CenterDot;\&CenterDot;\&CenterDot;+e_{i\&times;b+b-1}{g}_{i,j})}^{l\left(1\right)}$

Formula (4) is a process taking advantage of-Jia-move to left-store, and its realization buffer adds shift register (Buffer-Adder-Shift-Register, BASR) circuit.Fig. 3 is the functional block diagram of BASR circuit, and information vector s is sent into this circuit by serial by turn.When with BASR circuit to verification section p _j-awhen (0≤j<c) encodes, generator polynomial look-up table prestores all generator polynomials of the jth block row of generator matrix G, and shift register is cleared initialization.When the 0th clock cycle arrives, buffer loads the 0th piece of row of G, the generator polynomial g of jth block row from generator polynomial look-up table _{0, j}, information bit e ₀move into circuit, and with the content g of buffer _{0, j}carry out scalar multiplication, product e ₀g _{0, j}add with content 0 mould 2 of shift register, and e ₀g _{0, j}result (the 0+e of ring shift left 1 ₀g _{0, j}) ^{l (1)}deposit travelling backwards bit register.When the 1st clock cycle arrives, the content of buffer remains unchanged, information bit e ₁move into circuit, and with the content g of buffer _{0, j}carry out scalar multiplication, product e ₁g _{0, j}with the content (0+e of shift register ₀g _{0, j}) ^{l (1)}mould 2 adds, and (0+e ₀g _{0, j}) ^{l (1)}+ e ₁g _{0, j}the result ((0+e of ring shift left 1 ₀g _{0, j}) ^{l (1)}+ e ₁g _{0, j}) ^{l (1)}deposit travelling backwards bit register.Above-mentioned-the Jia of taking advantage of-move to left-storing process proceeds down.At the end of b-1 clock cycle, information bit e _b-1move into circuit, that now shift register stores is part and s ₀g _{0, j}, this is message segment s ₀to p _j-acontribution.When b clock cycle arrives, buffer loads the 1st piece of row of G, the generator polynomial g of jth block row from generator polynomial look-up table _{1, j}, repeat that the above-mentioned-Jia of taking advantage of-move to left-storing process.As message segment s ₁when moving into circuit completely, that shift register stores is part and s ₀g _{0, j}+ s ₁g _{1, j}.Repeat said process, until the whole serial of whole information vector s moves into circuit.Now, that shift register stores is verification section p _j-a.

Fig. 4 gives a kind of QC-LDPC serial encoder based on shared memory mechanism be made up of c BASR circuit, is made up of generator polynomial look-up table, buffer, b position binary multiplier, b position binary adder, shift register and delayer six kinds of functional modules.Generator polynomial look-up table is for storing the generator polynomial of all circular matrixes, and c BASR circuit shares this look-up table, and timesharing therefrom reads generator polynomial.Buffer B ₀, B ₁..., B _c-1buffer memory a, a+1 respectively ..., the generator polynomial of circular matrix in t-1 block row.Buffer B ₀, B ₁..., B _c-1in generator polynomial respectively with the data bit D in delayer D ₀, D ₁..., D _c-1carry out scalar multiplication, this c scalar multiplication is respectively by b position binary multiplier M ₀, M ₁..., M _c-1complete.B position binary multiplier M ₀, M ₁..., M _c-1product respectively with shift register R ₀, R ₁..., R _c-1content be added, this c nodulo-2 addition is respectively by b position binary adder A ₀, A ₁..., A _c-1complete.B position binary adder A ₀, A ₁..., A _c-1and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁..., R _c-1.Data bit D in delayer D ₀~ D _c-1slide and store c bit information.

Generator polynomial look-up table stores all circular matrix generator polynomials in QC-LDPC code generator matrix, first stores a, a+1 in the 0th piece of row successively,, the generator polynomial that t-1 block row are corresponding, then store a in the 1st piece of row successively, a+1,, the generator polynomial that t-1 block row are corresponding, the rest may be inferred, last store successively a-1 block capable in a, a+1 ..., the generator polynomial that t-1 block row are corresponding.

The invention provides a kind of QC-LDPC serial encoding method based on shared memory mechanism, be applicable to the QC-LDPC code in communication system, its coding step is described below:

1st step, resets delayer D and shift register R ₀, R ₁..., R _c-1, buffer B _j-aload the generator polynomial g of generator matrix G i-th piece of row, jth block row from generator polynomial look-up table when i-th × b+j-a clock cycle arrives _i,j, and remain unchanged in other moment;

2nd step, when a kth clock cycle arrives, delayer D input information bits e _k(0≤k<a × b), buffer B ₀, B ₁..., B _c-1in generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _c-1with the data bit D in delayer D ₀, D ₁..., D _c-1carry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M _c-1product respectively by b position binary adder A ₀, A ₁..., A _c-1with shift register R ₀, R ₁..., R _c-1content be added, b position binary adder A ₀, A ₁..., A _c-1and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁..., R _c-1;

3rd step, with 1 for step-length increases progressively the value changing k, repetition the 2nd step a × b time, until whole information vector s inputs complete;

4th step, when the clock cycle arrives, delayer D inputs filling bit 0, buffer B ₀, B ₁..., B _c-1in generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _c-1with the data bit D in delayer D ₀, D ₁..., D _c-1carry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M _c-1product respectively by b position binary adder A ₀, A ₁..., A _c-1with shift register R ₀, R ₁..., R _c-1content be added, b position binary adder A ₀, A ₁..., A _c-1and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁..., R _c-1;

5th step, repeats the 4th step c time, until c filling bit 0 inputs complete, now, and shift register R ₀, R ₁..., R _c-1that store is verification section p respectively ₀, p ₁..., p _c-1, they constitute the vectorial p=(p of verification ₀, p ₁..., p _c-1).

Be not difficult to find out from above step, whole cataloged procedure needs a × b+c clock cycle altogether, more than the existing serial encoding method based on c SRAA-I circuit c clock cycle.Usually, c, much smaller than a × b, can ignore.Visible, the speed of two kinds of coding methods is substantially identical.

In communication system, the existing solution of QC-LDPC serial code needs 2 × c × b register, c × b two inputs and door and c × b individual two to input XOR gate, and the present invention needs 2 × c × b+c register, c × b two inputs to input XOR gate with door and c × b individual two.Two kinds of coding methods expend equal number with door and XOR gate, the present invention is multiplex c register.Usually, c, much smaller than 2 × c × b, can ignore.Visible, the register that two kinds of coding methods expend is also substantially identical.

To sum up, two kinds of coding methods have almost identical coding rate and logical resource to expend.But the present invention has two clear superiorities, overcome the shortcoming of the existing solution of QC-LDPC serial code in communication system.In existing solution, shift register is in each clock cycle or load new generator polynomial, ring shift right 1, the storage content of single register constantly changes and causes the power consumption of circuit large, and the present invention uses the generator polynomial of buffer load circular matrix, without the need to loopy moving, the every b of its content clock cycle change once, significantly reduces power consumption.This is first advantage of the present invention.Second advantage adopts to share memory mechanism, single ROM and same data/address bus is used to realize generator polynomial look-up table, overcome that the waste that in existing solution, multiple ROM brings is many, memory is large, cost high shortcoming, enormously simplify the project organization of generator polynomial look-up table, farthest save memory space, reduce cost.

In brief, for the serial code of QC-LDPC code in communication system, compared with existing solution, the present invention maintains identical coding rate substantially and logical resource expends, and has that power consumption is little, structure is simple, memory consumption is few, low cost and other advantages.

The above; be only one of the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the technical scope disclosed by the present invention; the change can expected without creative work or replacement, all should be encompassed within protection scope of the present invention.Therefore, the protection range that protection scope of the present invention should limit with claims is as the criterion.

Claims (3)

1. a quasi-cyclic LDPC serial encoder for shared memory mechanism, the generator matrix G of quasi-cyclic LDPC code is divided into the capable and t block row of a block, and the part generator matrix that rear c block row are corresponding is by a × c b × b rank circular matrix G _i,jthe array formed, g _i,jcircular matrix G _i,jgenerator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<a, a≤j<t, the corresponding code word v=(s, p) of generator matrix G, that the front a block row of G are corresponding is information vector s=(e ₀, e ₁..., e _{a × b-1}), that rear c block row are corresponding is the vectorial p of verification, is one section, verifies vectorial p and be divided into c section, be i.e. p=(p with b bit ₀, p ₁..., p _c-1), it is characterized in that, described encoder comprises following parts:

Generator polynomial lookup table memories, for storing the generator polynomial of circular matrix in all generator matrix G;

Delayer D, its data bit D ₀, D ₁..., D _c-1slide and store c bit information;

Buffer B ₀, B ₁..., B _c-1, share generator polynomial lookup table memories, timesharing therefrom reads generator polynomial, buffer B _j-aload the generator polynomial g of generator matrix G i-th piece of row, jth block row from generator polynomial lookup table memories when i-th × b+j-a clock cycle arrives _i,j, and remain unchanged in other moment;

B position binary multiplier M ₀, M ₁..., M _c-1, respectively to data bit D ₀, D ₁..., D _c-1with buffer B ₀, B ₁..., B _c-1in generator polynomial carry out scalar multiplication;

B position binary adder A ₀, A ₁..., A _c-1, respectively to b position binary multiplier M ₀, M ₁..., M _c-1sum of products shift register R ₀, R ₁..., R _c-1content carry out mould 2 and add;

Shift register R ₀, R ₁..., R _c-1, store b position binary adder A respectively ₀, A ₁..., A _c-1and be recycled the move to left result after 1 and final verification section p ₀, p ₁..., p _c-1.

2. the quasi-cyclic LDPC serial encoder of a kind of shared memory mechanism according to claim 1, it is characterized in that, described generator polynomial lookup table memories stores all circular matrix generator polynomials in quasi-cyclic LDPC code generator matrix, first store a in the 0th piece of row successively, a+1,, the generator polynomial that t-1 block row are corresponding, then store a in the 1st piece of row successively, a+1,, the generator polynomial that t-1 block row are corresponding, the rest may be inferred, last store successively a-1 block capable in a, a+1 ..., the generator polynomial that t-1 block row are corresponding.

3. a quasi-cyclic LDPC serial encoding method for shared memory mechanism, the generator matrix G of quasi-cyclic LDPC code is divided into the capable and t block row of a block, and the part generator matrix that rear c block row are corresponding is by a × c b × b rank circular matrix G _i,jthe array formed, g _i,jcircular matrix G _i,jgenerator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<a, a≤j<t, the corresponding code word v=(s, p) of generator matrix G, that the front a block row of G are corresponding is information vector s=(e ₀, e ₁..., e _{a × b-1}), that rear c block row are corresponding is the vectorial p of verification, is one section, verifies vectorial p and be divided into c section, be i.e. p=(p with b bit ₀, p ₁..., p _c-1), it is characterized in that, described coding method comprises the following steps:

1st step, resets delayer D and shift register R ₀, R ₁..., R _c-1, buffer B ₀, B ₁..., B _c-1share generator polynomial lookup table memories, timesharing therefrom reads generator polynomial, buffer B _j-aload the generator polynomial g of generator matrix G i-th piece of row, jth block row from generator polynomial lookup table memories when i-th × b+j-a clock cycle arrives _i,j, and remain unchanged in other moment;

2nd step, when a kth clock cycle arrives, delayer D input information bits e _k, buffer B ₀, B ₁..., B _c-1in generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _c-1with the data bit D in delayer D ₀, D ₁..., D _c-1carry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M _c-1product respectively by b position binary adder A ₀, A ₁..., A _c-1with shift register R ₀, R ₁..., R _c-1content be added, b position binary adder A ₀, A ₁..., A _c-1and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁..., R _c-1, wherein, 0≤k<a × b;

3rd step, with 1 for step-length increases progressively the value changing k, repetition the 2nd step a × b time, until whole information vector s inputs complete;

4th step, when the clock cycle arrives, delayer D inputs filling bit 0, buffer B ₀, B ₁..., B _c-1in generator polynomial respectively by b position binary multiplier M ₀, M ₁..., M _c-1with the data bit D in delayer D ₀, D ₁..., D _c-1carry out scalar multiplication, b position binary multiplier M ₀, M ₁..., M _c-1product respectively by b position binary adder A ₀, A ₁..., A _c-1with shift register R ₀, R ₁..., R _c-1content be added, b position binary adder A ₀, A ₁..., A _c-1and be recycled the result after 1 that moves to left respectively stored in shift register R ₀, R ₁..., R _c-1;

5th step, repeats the 4th step c time, until c filling bit 0 inputs complete, now, and shift register R ₀, R ₁..., R _c-1that store is verification section p respectively ₀, p ₁..., p _c-1, they constitute the vectorial p=(p of verification ₀, p ₁..., p _c-1).