CN107196663A - Second part inputs the cumulative LDPC encoder moved to left parallel in CDR - Google Patents

Abstract

The invention provides the QC LDPC encoders based on two-level pipeline in a kind of CDR, the encoder includes the multiplier and 1 vector and the multiplier of high-density matrix of 1 sparse matrix and vector.The multiplier of sparse matrix and vector realizes sparse matrix and vectorial multiplying, and the vectorial multiplier with high-density matrix is added up using part parallel input moves to left mechanism, realization vector and the multiplying of high-density matrix.Whole cataloged procedure is divided into 2 level production lines.3/4 code check QC LDPC encoders have the advantages that cost is low, handling capacity is big in the CDR systems that the present invention is provided.

Description

Second part inputs the cumulative LDPC encoder moved to left parallel in CDR

Technical field

The present invention relates to field of channel coding, second part inputs cumulative move to left parallel in more particularly to a kind of CDR systems QC-LDPC encoders.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The life of QC-LDPC codes All it is the array being made up of circular matrix into matrix G and check matrix H, the characteristics of with stages cycle, therefore is referred to as QC-LDPC Code.The first trip of circular matrix is the result of footline ring shift right 1, and remaining each row is all the knot of its lastrow ring shift right 1 Really, therefore, circular matrix is characterized by its first trip completely.Generally, the first trip of circular matrix is referred to as its generator polynomial.

CDR standards employ the QC-LDPC codes of system form, and its generator matrix G left-half is a unit matrix, Right half part is by e × c b × b rank circular matrixes G_i,j(1≤i≤e,e<J≤t, t=e+c) constitute array, following institute Show：

Wherein, I is b × b rank unit matrixs, and 0 is b × b rank full null matrix.G continuous b rows and b row are known respectively as block Row and block row.From formula (1), G has e blocks row and t blocks row.CDR standards employ a kind of QC-LDPC codes of code check η=3/4, For the code, t=36, e=27, c=9, b=256.

In CDR standards the existing solution of 3/4 code check QC-LDPC encoders be added based on c I type shift register it is tired Plus the serial encoder of device (Type-I Shift-Register-Adder-Accumulator, SRAA-I) circuit.By c The serial encoder that SRAA-I circuits are constituted, completes coding within e × b clock cycle.The program needs 2 × c × b deposit Device, c × b two inputs and door and c × b two input XOR gate, in addition it is also necessary to which e × c × b bits ROM stores the life of circular matrix Into multinomial.The program has two shortcomings：One is to need a large amount of memories, causes circuit cost high；Two be serial input information Bit, coding rate is slow.

The content of the invention

In CDR systems the existing implementation of 3/4 code check QC-LDPC encoders have that cost is high, coding rate lacking slowly Point, for these technical problems, the invention provides a kind of QC-LDPC encoders based on two-level pipeline.

As shown in figure 1, the QC-LDPC encoders based on two-level pipeline are mainly made up of 2 parts in CDR systems：It is sparse The multiplier and vector and the multiplier of high-density matrix of matrix and vector.2 steps of cataloged procedure point are completed：1st step, using sparse The multiplier of matrix and vector calculates vector s；2nd step, verification vector p is calculated using the multiplier of vector and high-density matrix.

Advantage on the present invention can be further understood with method by following detailed description and accompanying drawings.

Brief description of the drawings

Fig. 1 is the QC-LDPC cataloged procedures based on two-level pipeline；

Fig. 2 is the multiplier of sparse matrix and vector；

Fig. 3 is the functional block diagram of the multiply-add shift register MASR circuits inputted parallel；

What Fig. 4 was that the MASR circuits inputted parallel by c are constituted a kind of inputs the cumulative vector moved to left based on part parallel With high-density matrix multiplier；

Fig. 5 summarizes the hardware resource and processing time needed for each coding step of encoder and whole cataloged procedure.

Embodiment

Presently preferred embodiments of the present invention is elaborated below in conjunction with the accompanying drawings, so that advantages and features of the invention can be more It is easy to be readily appreciated by one skilled in the art, apparent is clearly defined so as to be made to protection scope of the present invention.

The row weight and row heavy phase of circular matrix are same, are denoted as w.If w=0, then the circular matrix is full null matrix.If W=1, then the circular matrix is replaceable, referred to as permutation matrix, and it can be by some positions of unit matrix I ring shift rights Obtain.The check matrix H of QC-LDPC codes is by c × t b × b rank circular matrixes H_j,k(1≤j≤c, 1≤k≤t, t=e+c) The following array constituted：

Under normal circumstances, any circular matrix in check matrix H is either full null matrix (w=0) or is displacement square Battle array (w=1).Make circular matrix H_j,kFirst trip h_j,k=(h_j,k,1,h_j,k,2,…,h_j,k,b) it is its generator polynomial, wherein h_j,k,m =0 or 1 (1≤m≤b).Because H is sparse, h_j,kOnly 1 ' 1 ', even without ' 1 '.

Corresponding H preceding e blocks row are information vector a, and corresponding rear c blocks row are verification vector p, code word v=(a, p).With b Bit is one section, and information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e)；Verification vector p is divided into c sections, i.e. p= (p₁,p₂,…,p_c).H preceding e blocks row and rear c blocks are arranged to the matrix constituted and are denoted as C and D respectively, then

H=[C D] (3)

C is made up of c × e b × b rank circular matrix, and D is made up of c × c b × b rank circular matrix.By formula (3) and Code word v=(a, p) substitutes into Hv^T=0, arrangement can be obtained

p^T=Φ^TCa^T (4)

Wherein, Φ^T=D^–1, subscript^TWith^–1Transposition and inverse of a matrix are represented respectively, and D must full rank.It is well known that Cyclic Moment The inverse, product of battle array and be still circular matrix.Therefore, Φ is also the array being made up of circular matrix.But, although matrix D is Sparse, but Φ is generally no longer sparse but highdensity.

Make s^T=Ca^TAnd p^T=Φ^Ts^T, then p=s Φ.The multiplication that s is related to sparse matrix and vector is calculated using C, Φ is used Calculate p and be related to vector and the multiplication of high-density matrix.From the above discussion, a kind of QC- based on two-level pipeline can be provided LDPC cataloged procedures, as shown in Figure 1.

Make s=(s₁,s₂,…,s_c), then s_j ^TIt is the jth block row and a of Matrix C^TProduct, i.e.,

Wherein, 1≤i≤e, 1≤j≤c.s_jThe n-th bit s_j,n(1≤n≤b) is

Wherein, subscript^rs(n–1)With^ls(n–1)Ring shift right n -1 and ring shift left n -1 are represented respectively.Since any circulation Matrix generator polynomial h_j,iOnly a small amount of ' 1 ' even complete zero, then the inner product in formula (6) can be by posting ring shift left The tap of storage sums to realize, sparse matrix and vectorial multiplier as shown in Figure 2.The multiplier of sparse matrix and vector By t b bit registers R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition.Register R_1,1, R_1,2,…,R_1,eFor loading and ring shift left message segment a₁,a₂,…,a_e, register R_1,e+1,R_1,e+2,…,R_1,tFor storing s Array section s₁,s₂,…,s_c.All circular matrix generator polynomials that partially connected in Fig. 2 is depended in Matrix C.If h_j,i,m=1 (1≤m≤b), then message segment a_iM bits be connected to XOR gate X_1,j.Therefore, register R_1,iAll take out Head depends on the nonzero element position of all circular matrix generator polynomials in i-th piece of Matrix C row, and multi input XOR gate X_1,jInput depend on Matrix C jth block row in all circular matrix generator polynomials nonzero element position.If in C All circular matrix generator polynomials have α ' 1 ', then sparse matrix needs to use (α-c) individual with vectorial multiplier Two input XOR gates calculate s simultaneously_1,n,s_2,n,…,s_c,n.S can be calculated within b clock cycle and finished.Using sparse matrix with The step of multiplier of vector calculates vector s is as follows：

1st step, input message segment a₁,a₂,…,a_e, they are stored in register R respectively_1,1,R_1,2,…,R_1,eIn；

2nd step, register R_1,1,R_1,2,…,R_1,eRing shift left 1 time, XOR gate X simultaneously_1,1,X_1,2,…,X_1,cRespectively will XOR result is moved to left into register R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 times, after the completion of, register R_1,e+1,R_1,e+2,…,R_1,tThe content of storage be respectively to Measure section s₁,s₂,…,s_c, they constitute vectorial s.

p^T=Φ^Ts^TIt is equivalent to p=s Φ.Φ is by c × c b × b rank circular matrixes Φ_j,u(1≤j≤c,1≤u≤c) The array of composition.Make circular matrix Φ_j,uFirst trip g_j,uIt is its generator polynomial.From p=s Φ, u sections of verification vectors are full Foot

p_u=s₁Φ_1,u+s₂Φ_2,u+…+s_jΦ_j,u+…+s_cΦ_c,u (7)

Make generator polynomial g_j,u=(g_j,u,1,g_j,u,2,…,g_j,u,b), then Φ_j,uIt can be considered unit matrix ring shift right version This weighted sum, i.e.,

Φ_j,u=g_j,u,1I^r(0)+g_j,u,2I^r(1)+…+g_j,u,bI^r(b-1) (8)

Wherein, subscript^r()Represent ring shift right.So, jth on the right of formula (7) equal sign is deployable is

Since by s_jRing shift right n is equivalent to its ring shift left b-n, i.e.,So formula (9) can change It is written as

Formula (10) is that a-multiply-add-moves to left-process stored, and it is realized with the multiply-add shift register inputted parallel (Multiplier-Adder-Shift-Register, MASR) circuit.Fig. 3 is the functional block diagram of the MASR circuits inputted parallel, Vectorial s sends into the circuit parallel using b bits as one section.When with the MASR circuits inputted parallel to verification section p_u(1≤u≤c) enters During row coding, generator polynomial look-up table prestores all generator polynomials of matrix Φ u blocks row, shift register quilt Reset initialization.When the 1st clock cycle arrives, array section s₁Move into circuit, the 1st of generator polynomial look-up table output Φ the The generator polynomial Φ of block row, u blocks row_1,uThe 0th bit g_1,u,1, and with array section s₁Carry out scalar multiplication, product g_1,u,1s₁ Add with the mould 2 of content 0 of shift register, and g_1,u,1s₁Result (the 0+g of ring shift left 1_1,u,1s₁)^l(1)It is stored back to shift LD Device.When the 2nd clock cycle arrives, generator polynomial look-up table output Φ_1,uThe 2nd bit g_1,u,2, and with array section s₁ Carry out scalar multiplication, product g_1,u,2s₁With the content (0+g of shift register_1,u,1s₁)^l(1)Mould 2 adds, and (0+g_1,u,1s₁)^l(1)+ g_1,u,2s₁The result ((0+g of ring shift left 1_1,u,1s₁)^l(1)+g_1,u,2s₁)^l(1)It is stored back to shift register.Above-mentioned-multiply-add-move to left- Storing process proceeds down.At the end of b-th of clock cycle, shift register storage is part and s₁Φ_1,u, this It is array section s₁To p_uContribution.When the b+1 clock cycle arrives, array section s₂Circuit is moved into, above-mentioned-multiply-add-left side is repeated Shifting-storing process.When generator polynomial look-up table has exported Φ_2,uLast bit g_2,u,bWhen, accumulator storage is portion Divide and s₁Φ_1,u+s₂Φ_2,u.Said process is repeated, circuit is moved into until whole vector s is all parallel.Now, accumulator is stored It is verification section p_u。

What Fig. 4 gave that the MASR inputted parallel by c constitute a kind of inputs the cumulative vector moved to left based on part parallel With high-density matrix multiplier, posted by generator polynomial look-up table, b binary multipliers, b binary adders and displacement Four kinds of functional module compositions of storage.Generator polynomial look-up table L₁,L₂,…,L_cPrestore matrix Φ the 1,2nd respectively ..., in c blocks row All circular matrix generator polynomials.Generator polynomial look-up table L₁,L₂,…,L_cThe generator polynomial bit of output respectively with Array section s_j(1≤j≤c) carries out scalar multiplication, and this c scalar multiplication passes through b binary multiplier M respectively₁,M₂,…,M_cIt is complete Into.B binary multiplier M₁,M₂,…,M_cProduct respectively with shift register R₁,R₂,…,R_cContent be added, this c Nodulo-2 addition passes through b binary adder A respectively₁,A₂,…,A_cComplete.B binary adder A₁,A₂,…,A_cAnd by Result after ring shift left 1 is stored in shift register R respectively₁,R₂,…,R_c。

Generator polynomial look-up table L₁,L₂,…,L_cCircular matrix generator polynomial in storage matrix Φ.Generator polynomial Look-up table L₁~L_cAll generator polynomials in storage Φ 1~c blocks row, arrange for any block, the 1st are stored successively respectively, 2 ..., the corresponding generator polynomial of c block rows.Generator polynomial look-up table L₁~L_cThe bit of Serial output generator polynomial.

The step of calculating verification vector p using the multiplier of vector and high-density matrix is as follows：

1st step, resets shift register R₁,R₂,…,R_c；

2nd step, input vector section s_j(1≤j≤c)；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ jth block rows ..., c blocks row Generator polynomial bit, these generator polynomial bits pass through b binary multiplier M respectively₁,M₂,…,M_cWith array section s_jCarry out scalar multiplication, b binary multiplier M₁,M₂,…,M_cProduct pass through b binary adder A respectively₁,A₂,…,A_c With shift register R₁,R₂,…,R_cContent be added, b binary adder A₁,A₂,…,A_cAnd by after ring shift left 1 Result be stored in shift register R respectively₁,R₂,…,R_c；

4th step, repeats the 3rd step b-1 times；

5th step, with 1 value for incrementally changing j for step-length, repeats the 2nd~4 step c-1 times, until whole vector s has been inputted Finish, now, shift register R₁,R₂,…,R_cStorage is verification section p respectively₁,p₂,…,p_c, they constitute verification vector p =(p₁,p₂,…,p_c)。

The invention provides a kind of QC-LDPC coding methods based on two-level pipeline, it is adaptable to 3/4 in CDR systems Code check QC-LDPC codes, its coding step is described as follows：

1st step, vector s is calculated using the multiplier of sparse matrix and vector；

2nd step, verification vector p is calculated using the multiplier of vector and high-density matrix.

When Fig. 5 summarizes hardware resource consumption and the processing needed for each coding step of encoder and whole cataloged procedure Between.

It is not difficult to find out from Fig. 5, when streamline is full of, whole cataloged procedure needs max (t-c+b, cb)=cb clock week altogether Phase, less than the e × b clock cycle needed for the serial encoding method based on c SRAA-I circuit.For 3/4 yard in CDR standards Rate QC-LDPC encoders, coding rate of the invention is 3 times of the latter.

The existing solution of 3/4 code check QC-LDPC encoders needs e × c × b bit ROM in CDR standards, and this hair It is bright to need c²B bits ROM.The present invention needs less ROM, is the 1/3 of existing solution.

As fully visible, for 3/4 code check QC-LDPC encoders in CDR standards, compared with traditional serial SRAA methods, this Invention has the advantages that coding rate is fast, memory consumption lacks.

One of the foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, Any those skilled in the art disclosed herein technical scope in, the change that can be expected without creative work Change or replace, should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with claims The protection domain limited is defined.

Claims (4)

1. the QC-LDPC encoders based on two-level pipeline in a kind of CDR, the check matrix H of 3/4 code check QC-LDPC codes is by c The array that × t b × b ranks circular matrix is constituted, wherein, c=9, t=36, b=256, e=t-c=27, check matrix H can be drawn It is divided into 2 submatrixs, H=[C D], C is made up of c × e b × b rank circular matrix, and D is by c × c b × b rank Cyclic Moment Battle array is constituted, Φ^T=D^–1, wherein, subscript^TWith^-1Transposition and inverse, Matrix C corresponding informance vector a are represented respectively, and matrix D correspondence is verified Vectorial p, using b bits as one section, information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e), verification vector p is divided into c Section, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s are divided into c sections, i.e. s=(s₁,s₂,…,s_c), its feature It is, the encoder is included with lower component：

The multiplier of sparse matrix and vector, by t b bit registers R_1,1,R_1,2,…,R_1,tWith c multi input XOR gate X_1,1,X_1,2,…,X_1,cComposition, for calculating vectorial s；

Vector and the multiplier of high-density matrix, move to left mechanism based on part parallel input is cumulative, by generator polynomial look-up table, B binary multipliers, b binary adders and shift register composition, for calculating verification vector p, generator polynomial Look-up table L₁,L₂,…,L_cPrestore matrix Φ the 1,2nd respectively ..., all circular matrix generator polynomials in c blocks row；Generation is more Item formula look-up table L₁,L₂,…,L_cThe generator polynomial bit of output respectively with array section s_jCarry out scalar multiplication, this c scalar multiplication Method passes through b binary multiplier M respectively₁,M₂,…,M_cComplete；B binary multiplier M₁,M₂,…,M_cProduct respectively with Shift register R₁,R₂,…,R_cContent be added, this c nodulo-2 addition pass through b binary adder A respectively₁,A₂,…,A_c Complete；B binary adder A₁,A₂,…,A_cAnd shift register R is stored in by the result after ring shift left 1 respectively₁, R₂,…,R_c, wherein, 1≤j≤c.

2. the QC-LDPC encoders based on two-level pipeline in a kind of CDR according to claim 1, it is characterised in that institute The step of multiplier for stating sparse matrix and vector calculates vector s is as follows：

1st step, input message segment a₁,a₂,…,a_e, they are stored in register R respectively_1,1,R_1,2,…,R_1,eIn；

2nd step, register R_1,1,R_1,2,…,R_1,eRing shift left 1 time, XOR gate X simultaneously_1,1,X_1,2,…,X_1,cRespectively by XOR As a result move to left into register R_1,e+1,R_1,e+2,…,R_1,tIn；

3rd step, repeats the 2nd step b-1 times, after the completion of, register R_1,e+1,R_1,e+2,…,R_1,tThe content of storage is array section respectively s₁,s₂,…,s_c, they constitute vectorial s.

3. the QC-LDPC encoders based on two-level pipeline in a kind of CDR according to claim 1, it is characterised in that institute The step of multiplier for stating vectorial and high-density matrix calculates verification vector p is as follows：

1st step, resets shift register R₁,R₂,…,R_c；

2nd step, input vector section s_j, wherein, 1≤j≤c；

3rd step, generator polynomial look-up table L₁,L₂,…,L_cRespectively the 1,2nd in output matrix Φ jth block rows ..., the life of c blocks row Into multinomial bit, these generator polynomial bits pass through b binary multiplier M respectively₁,M₂,…,M_cWith array section s_jEnter Row scalar multiplication, b binary multiplier M₁,M₂,…,M_cProduct pass through b binary adder A respectively₁,A₂,…,A_cWith shifting Bit register R₁,R₂,…,R_cContent be added, b binary adder A₁,A₂,…,A_cAnd by the knot after ring shift left 1 Fruit is stored in shift register R respectively₁,R₂,…,R_c；

4th step, repeats the 3rd step b-1 times；

5th step, with 1 value for incrementally changing j for step-length, repeats the 2nd~4 step c-1 times, is finished until whole vector s is inputted, this When, shift register R₁,R₂,…,R_cStorage is verification section p respectively₁,p₂,…,p_c, they constitute verification vector p=(p₁, p₂,…,p_c)。

4. the QC-LDPC coding methods based on two-level pipeline in a kind of CDR, the check matrix H of 3/4 code check QC-LDPC codes is The array being made up of c × t b × b rank circular matrix, wherein, c=9, t=36, b=256, e=t-c=27, check matrix H 2 submatrixs, H=[C D] can be divided into, C is made up of c × e b × b rank circular matrix, and D is followed by c × c b × b rank Ring matrix is constituted, Φ^T=D^–1, wherein, subscript^TWith^-1Transposition and inverse, Matrix C corresponding informance vector a, matrix D correspondence are represented respectively Vector p is verified, using b bits as one section, information vector a is divided into e sections, i.e. a=(a₁,a₂,…,a_e), verification vector p by etc. It is divided into c sections, i.e. p=(p₁,p₂,…,p_c), s^T=Ca^T, p=s Φ, vectorial s are divided into c sections, i.e. s=(s₁,s₂,…,s_c), its It is characterised by, the coding method comprises the following steps：

1st step, vector s is calculated using the multiplier of sparse matrix and vector；

2nd step, verification vector p is calculated using the multiplier of vector and high-density matrix.