CN104579366A - High-speed QC (quasi-cyclic)-LDPC (low-density parity-check) encoder on basis of three levels of flow lines in WPAN (wireless personal area network) - Google Patents

Abstract

The invention provides a high-speed QC (quasi-cyclic)-LDPC (low-density parity-check) encoder on the basis of three-level assembly lines in a WPAN (wireless personal area network). The high-speed QC-LDPC encoder comprises a sparse matrix and vector multiplier, a type-I backward iterative circuit and a type-II backward iterative circuit. Sparse matrix and vector multiply operation can be implemented by the aid of the sparse matrix and vector multiplier, and backward iterative operation can be implemented by the aid of the type-I backward iterative circuit and the type-II backward iterative circuit. Each integral encoding procedure is divided into the three levels of flow lines. The high-speed QC-LDPC encoder with the 1/2 code rate in a WPAN system has the advantages of simple structure, low cost, high throughput and the like.

Description

High-speed QC-LDPC encoder based on three-stage pipeline in WPAN

Technical Field

The invention relates to the field of channel coding, in particular to a high-speed QC-LDPC encoder based on a three-level pipeline in a WPAN system.

Background

A Low-Density Parity-Check (LDPC) code is one of the efficient channel coding techniques, and a Quasi-Cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a special LDPC code. The generation matrix G and the check matrix H of the QC-LDPC code are both arrays formed by cyclic matrixes, have the characteristic of segmented circulation, and are called the QC-LDPC code. The first row of the circulant matrix is the result of the cyclic right shift of the last row by 1 bit, and the remaining rows are the result of the cyclic right shift of the last row by 1 bit, so that the circulant matrix is completely characterized by its first row. Typically, the first row of the circulant matrix is referred to as its generator polynomial.

The communication system usually adopts QC-LDPC code of system form, its left half of generating matrix G is a identity matrix, the right half is by e x c b x b rank cyclic matrix G_i,j(0≤i<e,e≤j<t, t ═ e + c), as follows:

where I is a b × b order identity matrix and 0 is a b × b order all-zero matrix. Successive b rows and b columns of G are referred to as block rows and block columns, respectively. From equation (1), G has e block rows and t block columns. The WPAN standard uses a QC-LDPC code with code rate η of 1/2 for which t is 32, e is 16, c is 16, and b is 21.

The existing solution for the 1/2 code rate QC-LDPC encoder in the WPAN standard is a serial encoder based on 16 Type-I Shift-Register-Adder-Accumulator (SRAA-I) circuits. The serial encoder, which consists of 16 SRAA-I circuits, completes the encoding within 336 clock cycles. This scheme requires 672 registers, 336 two-input and gates and 336 two-input xor gates, and also requires 5376-bit ROM to store the generator polynomial of the circulant matrix. This solution has two drawbacks: firstly, a large amount of memory is needed, resulting in high circuit cost; and secondly, information bits are input serially, so that the encoding speed is low.

Disclosure of Invention

The invention provides a high-speed QC-LDPC encoder based on a three-stage pipeline, aiming at the technical problems that the existing implementation scheme of an 1/2 code rate QC-LDPC encoder in a WPAN system has the defects of high cost and low encoding speed.

As shown in fig. 2, the high-speed QC-LDPC encoder based on three-stage pipeline in WPAN system is mainly composed of 3 parts: a sparse matrix and vector multiplier, a type I backward iteration circuit and a type II backward iteration circuit. The encoding process is completed in 3 steps: step 1, calculating vectors f and w by using a sparse matrix and a vector multiplier; step 2, calculating vectors q and x by using an I-type backward iterative circuit to obtain a partial check vector p_xX; and 3, calculating the vector y by using a II type backward iterative circuit, and performing exclusive OR on the vector y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。

The 1/2 code rate high-speed QC-LDPC encoder in the WPAN system provided by the invention has a simple structure, does not need a memory, and can obviously improve the encoding speed, thereby reducing the cost and improving the throughput.

The advantages and methods of the present invention will be further understood by reference to the following detailed description and drawings.

Drawings

FIG. 1 is a schematic diagram of an approximate lower triangular check matrix after row-column swapping;

FIG. 2 is a QC-LDPC encoding process based on a three-stage pipeline;

FIG. 3 is a sparse matrix and vector multiplier;

FIG. 4 shows the connection relationship between each multi-input XOR gate and the register in the multiplier of the sparse matrix and the vector;

FIG. 5 is a type I backward iteration circuit;

FIG. 6 shows the block positions of the non-zero circulant matrix in the matrix Q and the circulant right-shift number thereof;

FIG. 7 is a type II backward iteration circuit;

FIG. 8 shows the block positions of the non-zero circulant matrix in matrix Y and its circulant right shift;

fig. 9 summarizes the hardware resources and processing time required for each encoding step of the encoder and the entire encoding process.

Detailed Description

The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.

The row weight and column weight of the circulant matrix are the same and denoted as w. If w is 0, then the circulant matrix is an all-zero matrix. If w is 1, the circulant matrix is replaceable, called the permutation matrix, which can be obtained by right-shifting the identity matrix I cyclically by a few bits. The check matrix H of the QC-LDPC code is a cyclic matrix H of order b x b formed by c x t_j,k(1. ltoreq. j. ltoreq. c, 1. ltoreq. k. ltoreq. t, t. e + c) in the following array:

in general, any cyclic matrix in the check matrix H is either an all-zero matrix (w ═ 0) or a permutation matrix (w ═ 1). Let the cyclic matrix H_j,kFirst line g of_j,k＝(g_j,k,1,g_j,k,2,…,g_j,k,b) Is its generator polynomial of which g_j,k,m0 or 1 (1. ltoreq. m. ltoreq. b). Since H is sparse, g_j,kThere are only 1 ' and even no ' 1 '.

For the QC-LDPC code with 1/2 code rates in the WPAN system, the first 16 block columns of H correspond to an information vector a, and the last 16 block columns of H correspond to a check vector p. With b bits as one segment, the information vector a is equally divided into 16 segments, i.e. a ═ a₁,a₂,…,a₁₆) (ii) a The check vector p is equally divided into 16 segments, i.e. p ═ p (p)₁,p₂,…,p₁₆)。

Performing row exchange and column exchange operation on the check matrix H, and converting the check matrix H into an approximate lower triangular shape H_ALTAs shown in fig. 1. The process of the line-column exchange is as follows: step 1, exchanging block columns, keeping the first 18 block columns unchanged, and reordering the last 14 block columns, wherein the first 18 block columns correspond to the original 31 st, 30 th, 25 th, 28 th, 19 th, 20 th, 29 th, 32 th, 23 th, 22 th, 27 th, 26 th, 24 th and 21 st block columns respectively; step 2, performing block line exchange on all block lines, wherein the block lines correspond to the 5 th, 7 th, 14 th, 16 th, 4 th, 1 th, 6 th, 8 th, 11 th, 10 th, 13 th, 15 th, 12 th, 9 th, 3 th and 2 nd original block lines respectively; and step 3, circularly right-shifting the permutation matrixes in the 16 rows by 7, 10, 4, 9, 5, 19, 17, 4, 5, 19, 12, 4, 20 and 7 bits respectively.

In fig. 1, all matrices have the unit of b 21 bits instead of 1 bit. A is constituted by 14 × 16B × B-order cyclic matrices, B is constituted by 14 × 02B × 1B-order cyclic matrices, T is constituted by 14 × 14B × B-order cyclic matrices, C is constituted by 2 × 16B × B-order cyclic matrices, D is constituted by 2 × 2B × B-order cyclic matrices, and E is constituted by 2 × 14B × B-order cyclic matrices. T is a lower triangular matrix, and u-2 reflects a check matrix H_ALTProximity to the lower triangular matrix. In fig. 1, the matrices a and C correspond to the information vector a, and the matrices B and D correspond to a portion of the check vector p_x＝(p₁,p₂) The matrices T and E correspond to the remaining check vectors p_y＝(p₃,p₄,…,p₁₆)。p＝(p_x,p_y). The matrix and the vector satisfy the following relations:

p_x ^Τ＝Φ(ET^-1Aa^Τ+Ca^Τ) (3)

p_y ^Τ＝T^-1(Aa^Τ+Bp_x ^Τ) (4)

wherein Φ is (ET)^-1B+D)^-1Upper label of^ΤAnd^-1respectively representing transpose and inverse. As is well known, the inverse, product, and sum of the circulant matrix remains a circulant matrix. Thus, Φ is also an array consisting of a circulant matrix.

When Φ is equal to the identity matrix, i.e., Φ ═ I, equation (3) can be simplified to p_x ^Τ＝ET^-1Aa^Τ+Ca^Τ. Let f^T＝Aa^T，q^T＝T^–1f^T，w^T＝Ca^T，x^T＝Eq^T+w^T，p_x ^T＝x^T，y^T＝T^–1Bp_x ^TAnd p_y ^T＝q^T+y^T. Vectors f and w can be calculated by:

${\left[\begin{array}{cc}f& w\end{array}\right]}^T=\left[\begin{array}{c}A\\ C\end{array}\right]a^T={\mathrm{Fa}}^T---\left(5\right)$

wherein,

$F=\left[\begin{array}{c}A\\ C\end{array}\right]---\left(6\right)$

q^T＝T^–1f^Tand x^T＝Eq^T+w^TThe following matrix equation can be constructed:

$\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]{\left[\begin{array}{cc}q& x\end{array}\right]}^T={Q\left[\begin{array}{cc}q& x\end{array}\right]}^T={\left[\begin{array}{cc}f& w\end{array}\right]}^T---\left(7\right)$

wherein,

$Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]---\left(8\right)$

once p is calculated_x，y^T＝T^–1Bp_x ^TRewritable as follows:

[B T][p_xy]^Τ＝Y[p_xy]^Τ＝0 (9)

wherein,

Y＝[B T](10)

since Q and Y are lower triangular matrices as well as T, both [ Q x ] in equation (7) and Y in equation (9) can be calculated in backward iteration.

F relates to the multiplication of the sparse matrix with the vector, while Q and Y relate to backward iterative computations. From the above discussion, a three-stage pipeline based QC-LDPC encoding process can be presented, as shown in FIG. 2.

Let f be (f)₁,f₂,…,f₁₄) And w ═ f₁₅,f₁₆) Then [ f w ]]＝(f₁,f₂,…,f₁₆). According to formula (5), f_jIs the jth block row of the matrix F and a^TProduct of, i.e.

$f_j=H_{j,1}{a}_1^T+H_{j,2}{a}_2^T+...+H_{j,i}{a}_i^T+...+H_{j,16}{a}_{16}^T---\left(11\right)$

Wherein i is more than or equal to 1 and less than or equal to 16, and j is more than or equal to 1 and less than or equal to 16. f. of_jN bit f of_j,n(1. ltoreq. n. ltoreq. b) is

$\begin{array}{c}{f}_{j,n}=g_{j,1}^{\mathrm{rs}(n-1)}{a}_1+g_{j,2}^{\mathrm{rs}(n-1)}{a}_2+...+g_{j,i}^{\mathrm{rs}(n-1)}{a}_i+...+g_{j,16}^{\mathrm{rs}(n-1)}{a}_{16}\\ =g_{j,1}{a}_1^{\mathrm{ls}(n-1)}+g_{j,2}{a}_2^{\mathrm{ls}(n-1)}+...+g_{j,i}{a}_i^{\mathrm{ls}(n-1)}+...+g_{j,16}{a}_{16}^{\mathrm{ls}(n-1)}\end{array}---\left(12\right)$

Wherein, the upper label^rs(n–1)And^ls(n–1)respectively representing a cyclic right shift by n-1 bits and a cyclic left shift by n-1 bits. Since any circulant matrix generates a polynomial g_j,iWith only a small number of '1's, or even all zeros, the inner product in equation (12) can be achieved by summing the taps of the circular left shift register, as shown in the sparse matrix and vector multiplier of fig. 3. The sparse matrix and vector multiplier consists of 32 b-bit registers R_1,1,R_1,2,…,R_1,32And 16 multiple-input XOR gates X_1,1,X_1,2,…,X_1,16And (4) forming. Register R_1,1,R_1,2,…,R_1,16For loading and looping left-shifting information segments a₁,a₂,…,a₁₆Register R_1,17,R_1,18,…,R_1,32For storing [ f w]Vector segment f of₁,f₂,…,f₁₆. The sparse connection in fig. 3 depends on all circulant matrix generator polynomials in the matrix F. If g is_j,i,m1 (1. ltoreq. m. ltoreq. b), then the information section a_iIs connected to the exclusive or gate X_1,j. Thus, register R_1,iDepends on the position of the non-zero elements of all circulant matrix generator polynomials in the ith block column of the matrix F, and is multi-inputGo into exclusive or gate X_1,jDepends on the position of the non-zero elements of all circulant matrix generator polynomials in the jth block row of the matrix F. Fig. 4 shows the connection relationship between each multi-input exclusive or gate and a register in the multiplier of the sparse matrix and the vector. Since all cyclic matrix generator polynomials in F have a total of 64 '1', the sparse matrix and vector multiplier needs to compute F simultaneously using 48 two-input xor gates (α -c)_1,n,f_2,n,…,f_16,n. f and w may be counted in 21 clock cycles. The steps of calculating vectors f and w using a sparse matrix and vector multiplier are as follows:

step 1, input information segment a₁,a₂,…,a₁₆Store them in the register R respectively_1,1,R_1,2,…,R_1,16Performing the following steps;

step 2, register R_1,1,R_1,2,…,R_1,16Simultaneously circulating left for 1 time, XOR gate X_1,1,X_1,2,…,X_1,16Shift the XOR result to the left into register R, respectively_1,17,R_1,18,…,R_1,32Performing the following steps;

step 3, repeating step 2 for b times, and after the step is completed, using a register R_1,17,R_1,18,…,R_1,32The contents of the memory are respectively vector segments f₁,f₂,…,f₁₆They constitute vectors f and w.

Equation (7) implies a backward iterative operation, and the vectors q and x must be solved segment by segment. Definition [ q x]＝(q₁,q₂,…,q₁₆) And initialized to all zeros. First, q is₁Exactly equal to f₁. Secondly, q is₂Is the 2 nd block row and vector [ Q x ] of the matrix Q]^TProduct of f₂And (2) of (1). Then, q₃Is block 3 row and vector [ Q x ] of matrix Q]^TProduct of f₃And (2) of (1). Repeating the above process until q is calculated₁₆A type I backward iterative circuit as shown in fig. 5. The I-type backward iterative circuit consists of 16 b-bit registers R_2,1,R_2,2,…,R_2,16And 15 multiple input modulo-2 adders A_2,2,A_2,3,…,A_2,16And (4) forming.

To calculate q_j(j is not less than 1 and not more than 16) as an example. The non-zero circulant matrix in the check matrix H is typically a circularly right shifted version of the identity matrix. Suppose there are N non-zero circulants in the jth block row of the matrix Q, and their cyclic right shift numbers are s respectively_j,k1,s_j,k2,…,s_j,kN(1≤k1,k2,…,kN<j) In that respect Then the process of the first step is carried out,

$\begin{array}{c}{q}_j=f_j+I^{\mathrm{rs}\left(s_{j,k1}\right)}{q}_{k1}+I^{\mathrm{rs}\left(s_{j,k2}\right)}{q}_{k2}+...+I^{\mathrm{rs}\left(s_{j,\mathrm{kN}}\right)}{q}_{\mathrm{kN}}\\ =f_j+q_{k1}^{\mathrm{ls}\left(s_{j,k1}\right)}+q_{k2}^{\mathrm{ls}\left(s_{j,k2}\right)}+...+q_{\mathrm{kN}}^{\mathrm{ls}\left(s_{j,\mathrm{kN}}\right)}\end{array}---\left(13\right)$

since N is small, equation (13) can be computed by a multiple input modulo-2 adder that shifts the input cycle to the left in 1 clock cycle. Therefore, 16 clock cycles are required to compute vector [ q x ]. Since the matrix Q has 38 non-zero circulant matrices, the I-type backward iterative circuit uses 462 two-input xor gates (β -c).

The matrix Q is a circulant matrix Q of order 16 × 16 b × b_j,k(j is more than or equal to 1 and less than or equal to 16, and k is more than or equal to 1 and less than or equal to 16). Non-zero circulant matrix Q_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,k，0≤s_j,k<b. For the convenience of description, the cyclic right shift number of the all-zero circulant matrix with respect to the b × b order circulant matrix is denoted as s_j,k'-'. In FIG. 5, a non-zero circulant matrix Q_j,kCorresponding vector segment q_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_2,jSegment f of the neutralization vector_jTo carry outXOR operation, the vector segment corresponding to the all-zero circulant matrix does not participate in XOR operation, A_2,jIs calculated as q_jIs stored in a register R_2,jIn (1). Fig. 6 shows the block positions of the non-zero circulant matrix in the matrix Q and its circulant right-shift number. The steps for computing the vectors q and x using a type I backward iterative circuit are as follows:

step 1, inputting vector segment f₁Dividing the vector segment q₁＝f₁Into a register R_2,1Performing the following steps;

step 2, inputting vector segment f_jNon-zero circulant matrix Q_j,kCorresponding vector segment q_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_2,jSegment f of the neutralization vector_jPerforming XOR operation to obtain result q_jIs stored in a register R_2,jWherein j is more than or equal to 2 and less than or equal to 16, and k is more than or equal to 1<j，0≤s_j,k<21；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for 15 times, and finally, obtaining a register R_2,1,R_2,2,…,R_2,16Stored are respectively vector segments q₁,q₂,…,q₁₆They constitute vectors q and x.

Equation (9) also implies a backward iterative operation, and the vector y must be solved segment by segment. Definition y ═ (y)₁,y₂,…,y₁₄) And initialized to all zeros. First, y₁Is the 1 st block row of matrix Y and vector p_xy]^TThe product of the two. Second, y₂Is the 2 nd block row of matrix Y and vector p_xy]^TThe product of the two. Repeating the above process until y is calculated₁₄Up to the type II backward iteration circuit as shown in fig. 7. The type II backward iterative circuit consists of 16 b-bit registers R_3,1,R_3,2,…,R_3,16And 14 multiple input modulo-2 adders A_3,1,A_3,2,…,A_3,14And (4) forming. The calculation of vector y takes 14 clock cycles. Since the matrix Y shares xi-38 non-zero circulant matrices, (xi-2 c +2u) b-210 two-input xor gates are used in the type II backward iterative circuit. The matrix Y is a circulant matrix Y of order b x b of 14 x 16_j,k(j is more than or equal to 1 and less than or equal to 14, and k is more than or equal to 1 and less than or equal to 16). Non-zero circulant matrix Y_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,k，0≤s_j,k<b. Fig. 8 shows the block positions of the non-zero circulant matrix in matrix Y and its circulant right-shift number. The steps for computing the vector y using a type II backward iterative circuit are as follows:

step 1, inputting a check segment p₁And p₂Store them in the register R respectively_3,15And R_3,16Performing the following steps;

step 2, non-zero circulant matrix Y_j,kCorresponding vector segment p_kOr y_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_3,jIn the process, an XOR operation is performed, and the result y of the XOR operation_jIs stored in a register R_3,jWherein j is more than or equal to 1 and less than or equal to 14, and k is more than or equal to 1<2+j，0≤s_j,k<21；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for 14 times, and finally, obtaining a register R_3,1,R_3,2,…,R_3,14Stored are respectively vector segments y₁,y₂,…,y₁₄They constitute a vector y.

The invention provides a high-speed QC-LDPC encoding method based on a three-level pipeline, which is suitable for 1/2 code rate QC-LDPC codes in a WPAN system, and the encoding steps are described as follows:

step 1, calculating vectors f and w by using a sparse matrix and a vector multiplier;

step 2, calculating vectors q and x by using an I-type backward iterative circuit to obtain a partial check vector p_x＝x；

And 3, calculating the vector y by using a II type backward iterative circuit, and performing exclusive OR on the vector y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。

Fig. 9 summarizes the hardware resource consumption and processing time required by each encoding step of the encoder and the entire encoding process.

As can be seen from fig. 9, when the pipeline is full, the whole encoding process takes 37 clock cycles, which is less than 336 clock cycles required by the serial encoding method based on 16 SRAA-I circuits. The former has an encoding speed 9 times faster than the latter.

The existing solution of the 1/2 code rate QC-LDPC encoder in the WPAN standard requires 672 registers, 336 two-input AND gates and 336 two-input XOR gates, and further requires 5376 bit ROM to store the generator polynomial of the circulant matrix. The present invention requires 1344 registers, 0 two-input and gates, and 720 two-input xor gates, without requiring ROM.

In conclusion, compared with the conventional serial SRAA method, the method has the advantages of high coding speed, no need of a memory and the like.

The above description is only one embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can change or replace the present invention within the technical scope of the present invention without creative efforts, and the present invention shall be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope defined by the claims.

Claims (6)

1. A high-speed QC-LDPC encoder based on three-stage pipeline in WPAN, a check matrix H of 1/2 code rate QC-LDPC code is an array formed by c x t b-order cyclic matrixes, wherein c is 16, t is 32, b is 21, e is t-c is 16, the check matrix H is transformed into an approximate lower triangular shape by row-column exchange and can be divided into 6 sub-matrixes, $H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right],$ a is a cyclic matrix of 14 × 16B × B steps, B is a cyclic matrix of 14 × 02B × 1B steps, T is a cyclic matrix of 14 × 14B × B steps, C is a cyclic matrix of 2 × 16B × B steps, D is a cyclic matrix of 2 × 2B × B steps, E is a cyclic matrix of 2 × 14B × B steps, and Φ is (ET)^-1B+D)^-1Is a 42 × 42 unit matrix, in which superscripts are applied^ΤAnd^-1the transpose and the inverse are indicated separately, $Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]$ is composed of 16 × 16 b × b order cyclic matrices Q_j,kWherein I is an identity matrix, 0 is an all-zero matrix, 1 is equal to or more than j is equal to or less than 16,1 is equal to or more than k is equal to or less than 16, and a non-zero cyclic matrix Q_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<b，Y＝[B T]Is composed of 14 × 16 b × b order cyclic matrices Y_j,kWherein j is more than or equal to 1 and less than or equal to 14, k is more than or equal to 1 and less than or equal to 16, and a non-zero cyclic matrix Y_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<B, A and C correspond to the information vector a, and the matrixes B and D correspond to a part of the check vector p_xThe matrices T and E correspond to the remaining check vectors p_yCheck vector p ═ p (p)_x,p_y) The information vector a is equally divided into 16 segments with b bits as one segment, i.e. a ═ a₁,a₂,…,a₁₆) The check vector p is equally divided into 16 segments, i.e. p ═ p (p)₁,p₂,…,p₁₆)，p_x＝(p₁,p₂)，p_y＝(p₃,p₄,…,p₁₆) The vector f is equally divided into 14 segments, i.e. f ═ f (f)₁,f₂,…,f₁₄) The vector w is equally divided into 2 segments, i.e. w ═ f₁₅,f₁₆)，[f w]＝(f₁,f₂,…,f₁₆) The vector q is equally divided into 14 segments, i.e. q ═ q (q)₁,q₂,…,q₁₄) The vector x is equally divided into 2 segments, i.e. x ═ q (q)₁₅,q₁₆)，[q x]＝(q₁,q₂,…,q₁₆) The vector y is equally divided into 14 segments, i.e. y ═ y (y)₁,y₂,…,y₁₄) Characterised in that the encoder comprises the following components:

the sparse matrix and vector multiplier consists of 32 b-bit registers R_1,1,R_1,2,…,R_1,32And 16 multiple-input XOR gates X_1,1,X_1,2,…,X_1,16A component for calculating vectors f and w;

the I-type backward iterative circuit consists of 16 b-bit registers R_2,1,R_2,2,…,R_2,16And 15 multiple input modulo-2 adders A_2,2,A_2,3,…,A_2,16Composition for calculating vectors q and x to find partial check vector p_x＝x；

A type II backward iterative circuit consisting of 16 b-bit registers R_3,1,R_3,2,…,R_3,16And 14 multiple input modulo-2 adders A_3,1,A_3,2,…,A_3,14Composition for calculating the XOR of the vector y, y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。

2. The high-speed QC-LDPC encoder based on three-stage pipeline in WPAN according to claim 1, wherein the row column switching process is as follows:

step 1, exchanging block columns, keeping the first 18 block columns unchanged, and reordering the last 14 block columns, wherein the first 18 block columns correspond to the original 31 st, 30 th, 25 th, 28 th, 19 th, 20 th, 29 th, 32 th, 23 th, 22 th, 27 th, 26 th, 24 th and 21 st block columns respectively;

step 2, performing block line exchange on all block lines, wherein the block lines correspond to the 5 th, 7 th, 14 th, 16 th, 4 th, 1 th, 6 th, 8 th, 11 th, 10 th, 13 th, 15 th, 12 th, 9 th, 3 th and 2 nd original block lines respectively;

and step 3, circularly right-shifting the permutation matrixes in the 16 rows by 7, 10, 4, 9, 5, 19, 17, 4, 5, 19, 12, 4, 20 and 7 bits respectively.

3. The high-speed QC-LDPC encoder based on three-stage pipeline in WPAN according to claim 1, wherein the step of calculating vectors f and w by the sparse matrix and vector multiplier is as follows:

step 1, input information segment a₁,a₂,…,a₁₆Store them in the register R respectively_1,1,R_1,2,…,R_1,16Performing the following steps;

step 2, register R_1,1,R_1,2,…,R_1,16Simultaneously circulating left for 1 time, XOR gate X_1,1,X_1,2,…,X_1,16Shift the XOR result to the left into register R, respectively_1,17,R_1,18,…,R_1,32Performing the following steps;

step 3, repeating step 2 for b times, and after the step is completed, using a register R_1,17,R_1,18,…,R_1,32The contents of the memory are respectively vector segments f₁,f₂,…,f₁₆They constitute vectors f and w.

4. The high-speed QC-LDPC encoder based on three-stage pipeline according to claim 1, wherein said type I backward iterative circuit calculates vectors q and x as follows:

step 1, inputting vector segment f₁Dividing the vector segment q₁＝f₁Into a register R_2,1Performing the following steps;

step 2, inputting vector segment f_jNon-zero circulant matrix Q_j,kCorresponding vector segment q_kIs circulatedLeft shift of ring s_j,kBit-wise input to a multiple-input modulo-2 adder A_2,jSegment f of the neutralization vector_jPerforming XOR operation to obtain result q_jIs stored in a register R_2,jWherein j is more than or equal to 2 and less than or equal to 16, and k is more than or equal to 1<j，0≤s_j,k<21；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for 15 times, and finally, obtaining a register R_2,1,R_2,2,…,R_2,16Stored are respectively vector segments q₁,q₂,…,q₁₆They constitute vectors q and x.

5. The high-speed QC-LDPC encoder based on three-stage pipeline in WPAN according to claim 1, wherein the type II backward iterative circuit calculates vector y as follows:

step 1, inputting a check segment p₁And p₂Store them in the register R respectively_3,15And R_3,16Performing the following steps;

step 2, non-zero circulant matrix Y_j,kCorresponding vector segment p_kOr y_kIs circularly moved to the left by s_j,kBit-wise input to a multiple-input modulo-2 adder A_3,jIn the process, an XOR operation is performed, and the result y of the XOR operation_jIs stored in a register R_3,jWherein j is more than or equal to 1 and less than or equal to 14, and k is more than or equal to 1<2+j，0≤s_j,k<21；

Step 3, gradually changing the value of j by taking 1 as a step length, repeating the step 2 for 14 times, and finally, obtaining a register R_3,1,R_3,2,…,R_3,14Stored are respectively vector segments y₁,y₂,…,y₁₄They constitute a vector y.

6. A high-speed QC-LDPC coding method based on three-stage pipeline in WPAN, the check matrix H of 1/2 code rate QC-LDPC code is an array formed by c x t b-order cyclic matrixes, wherein c is 16, t is 32, b is 21, e is t-c is 16, the check matrix H is transformed into approximate lower triangular shape by row-column exchange and can be divided into 6 sub-matrixes, $H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right],$ a is a cyclic matrix of 14 × 16B × B steps, B is a cyclic matrix of 14 × 02B × 1B steps, T is a cyclic matrix of 14 × 14B × B steps, C is a cyclic matrix of 2 × 16B × B steps, D is a cyclic matrix of 2 × 2B × B steps, E is a cyclic matrix of 2 × 14B × B steps, and Φ is (ET)^-1B+D)^-1Is a 42 × 42 unit matrix, in which superscripts are applied^ΤAnd^-1the transpose and the inverse are indicated separately, $Q=\left[\begin{array}{cc}T& 0\\ E& I\end{array}\right]$ is composed of 16 × 16 b × b order cyclic matrices Q_j,kWherein I is an identity matrix, 0 is an all-zero matrix, 1 is equal to or more than j is equal to or less than 16,1 is equal to or more than k is equal to or less than 16, and a non-zero cyclic matrix Q_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<b，Y＝[B T]Is composed of 14 × 16 b × b order cyclic matrices Y_j,kWherein j is more than or equal to 1 and less than or equal to 14, k is more than or equal to 1 and less than or equal to 16, and a non-zero cyclic matrix Y_j,kThe number of cyclic right shifts relative to the b x b order identity matrix is s_j,kWherein 0 is less than or equal to s_j,k<B, A and C correspond to the information vector a, and the matrixes B and D correspond to a part of the check vector p_xThe matrices T and E correspond to the remaining check vectors p_yCheck vector p ═ p (p)_x,p_y) The information vector a is equally divided into 16 segments with b bits as one segment, i.e. a ═ a₁,a₂,…,a₁₆) The check vector p is equally divided into 16 segments, i.e. p ═ p (p)₁,p₂,…,p₁₆)，p_x＝(p₁,p₂)，p_y＝(p₃,p₄,…,p₁₆) The vector f is equally divided into 14 segments, i.e. f ═ f (f)₁,f₂,…,f₁₄) The vector w is equally divided into 2 segments, i.e. w ═ f₁₅,f₁₆)，[f w]＝(f₁,f₂,…,f₁₆) The vector q is equally divided into 14 segments, i.e. q ═ q (q)₁,q₂,…,q₁₄) The vector x is equally divided into 2 segments, i.e. x ═ q (q)₁₅,q₁₆)，[q x]＝(q₁,q₂,…,q₁₆) The vector y is equally divided into 14 segments, i.e. y ═ y (y)₁,y₂,…,y₁₄) Characterized in that said coding method comprises the following steps:

step 1, calculating vectors f and w by using a sparse matrix and a vector multiplier;

step 2, calculating vectors q and x by using an I-type backward iterative circuit to obtain a partial check vector p_x＝x；

And 3, calculating the vector y by using a II type backward iterative circuit, and performing exclusive OR on the vector y and the vector q to obtain a partial check vector p_ySo as to obtain check vector p ═ p (p)_x,p_y)。3 -->