CN109639289A - A kind of QC-LDPC encryption algorithm and implementation method - Google Patents

A kind of QC-LDPC encryption algorithm and implementation method Download PDF

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CN109639289A
CN109639289A CN201811509804.9A CN201811509804A CN109639289A CN 109639289 A CN109639289 A CN 109639289A CN 201811509804 A CN201811509804 A CN 201811509804A CN 109639289 A CN109639289 A CN 109639289A
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length
sparse
calculating
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CN109639289B (en
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廖彬彬
周天游
王荣生
廖莎
黄益人
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Hangzhou Amam Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses a kind of QC-LDPC encryption algorithm and implementation methods.It is by using part generator matrix G and part check matrix H, to calculate check bit p from original information bits u；Specifically: original information bits u makes the length of original information bits u for the integral multiple of QC length by fills unit；The performance of LDPC encoder is improved using two cachings of table tennis by the original information bits u of fills unit；Densifying loops matrix and rarefaction cycles matrix are configured, is entered in dense/sparse matrix parameter, for controlling in each calculating clock cycle, which dense or sparse calculation engine participates in calculating；According to the configuration information of matrix parameter, the accumulation function in matrix multiplication, final output check bit p are realized by exclusive or.The beneficial effects of the present invention are: only needing using a small amount of memory space, calculating speed is fast；According to the performance requirement flexible customization circuit of user, the optimization between performance, power consumption and circuit area is realized.

Description

A kind of QC-LDPC encryption algorithm and implementation method
Technical field
The present invention relates to data encoding correlative technology fields in solid-state storage, refer in particular to a kind of QC-LDPC encryption algorithm And implementation method.
Background technique
Low density parity check code (Low-Density Parity Check Code, LDPC) is a kind of efficient coding Technology, but since check matrix has erratic behavior, reading difficulty, encoder complexity height etc., which are stored in, there are check matrix asks Topic, is relatively difficult to realize.
Quasi-cyclic low-density parity check codes (Quasi-Cyslic Low-Density Parity-Check Code, QC- LDPC) i.e. quasi-cyclic LDPC code.Quasi-cyclic LDPC code is the important subset of structured LDPC code, generator matrix G (Generate Matrix) and check matrix H (cHeck matrix) is all have circular matrix constitute array.The every a line of circular matrix is all by upper A line ring shift right one obtains, and wherein the lastrow of the first row is last line.
The submatrix of QC-LDPC code check matrix has a characteristic that (1) each submatrix is a square matrix.(2) it recycles Any row (column) of submatrix is all that lastrow (column) moves right one and obtains, particularly, the first row (column) of matrix by Last row (column) ring shift right one obtains.(3) circular matrix can be determined completely by its first row or first row.
For following check matrix H, it is assumed that QC size is c, i.e. a QC block is matrix of the c multiplied by c.
Wherein, HijIt is c multiplied by the circular matrix, that is, full 0 matrix or cyclic permutation matrices of c, m is the length of check bit multiplied by c Degree, n is multiplied by the total length that c is that original information bits add check bit.
Generator matrix G can be with is defined as:
G=(I | Gp)
Wherein: I is unit matrix.Check bit can be obtained are as follows:
P=Gpu
Wherein, p is check bit, and u is original information bits, that is, user data.Pass through matrix Gp, can be from original information bits u Calculate check bit p.But GpNeed to occupy a large amount of memory space, so that increased costs, and it is low to calculate throughput.
Summary of the invention
The present invention be in order to overcome the above deficiencies in the prior art, provide one kind can reduce memory space and Improve the QC-LDPC encryption algorithm and implementation method of calculating speed.
To achieve the goals above, the invention adopts the following technical scheme:
A kind of QC-LDPC encryption algorithm, by constructing and selecting the check matrix H of special shape, the form of check matrix H It is as follows:
Wherein, BlkU is the length of original information bits u, and BlkP is the length of check bit p, and check bit p points are three parts [P1 P2 P3], P1Partial length is blkm, P3Length be blkn, P2Length be BlkP-blkm-blkn, codeword structure It is defined as [uP1 P2 P3]；
According to verification principle, H × [uP1 P2 P3]T=0, solution obtains,
(H′311+H313 H′21+(H312+H313 H22)H′11)uT+(H″311+H313 H″21+(H312+H313 H22)H″11)P1 T= 0；
Wherein, H11=[H '11 H″11], H21=[H '21 H″21], H311=[H '311 H″311]；
Define L=H '311+H313 H′21+(H312+H313H22)H′11,
Define J=H "311+H313 H″21+(H312+H313 H22)H″11；
The form of check matrix H is adjusted to,
According to verification principle, H × [uP1 P2 P3]T=0, available check bit is,
P1=G0×uT
P2=H11×[u P1]T
P3=[H21 H22]×[u P1 P2]T
Wherein (G0=J-1× L), it is densifying loops matrix, H11, H21And H22For rarefaction cycles matrix.
The present invention proposes that one kind by using part generator matrix G and part check matrix H, is counted from original information bits u Calculate check bit p.The algorithm is only needed using a small amount of memory space, and calculating speed is fast.
The present invention also provides a kind of implementation methods of QC-LDPC encryption algorithm, specifically include following part:
Fills unit: when the length of original information bits u is not the integral multiple of QC length, 0 is filled in original information bits u Or 1, make that the length is the integral multiples of QC length；When original information bits u length is the integral multiple of QC length, then do not need to fill out It fills；
Information bit caching: the performance of LDPC encoder is improved using two cachings of table tennis, if user is to LDPC performance It is of less demanding, then using one of caching in table tennis；
Dense/sparse matrix parameter: saving the calculating parameter of dense matrix and sparse matrix, in LDPC cataloged procedure, For controlling in each calculating clock cycle, which dense or sparse calculation engine participates in calculating；
Dense computing engines: each computing engines complete a dense QC multiplication of matrices within a calculating clock cycle It calculates；
Sparse calculation engine: each computing engines complete a sparse QC multiplication of matrices within a calculating clock cycle It calculates；
Exclusive or computing unit: the accumulation calculating function in matrix multiplication is completed using XOR operation；
Specific steps are as follows:
(1) original information bits u makes the length of original information bits u for the integral multiple of QC length by fills unit；
(2) performance for being improved LDPC encoder using two cachings of table tennis by the information bit u of fills unit, is entered In dense computing engines and dense computing engines；
(3) simultaneously, densifying loops matrix and rarefaction cycles matrix are configured, enters in dense/sparse matrix parameter, is used to It controls in each calculating clock cycle, which dense or sparse calculation engine participates in calculating；
(4) information bit u combination densifying loops matrix and rarefaction cycles matrix complete dense QC square by dense computing engines The multiplication of battle array calculates, and completes sparse QC multiplication of matrices by rarefaction cycles matrix and calculates；
(5) it after entering exclusive or computing unit, according to the configuration information of matrix parameter, is realized in matrix multiplication by exclusive or Accumulation function, final output check bit p.
The present invention also proposes a kind of implementation method of algorithm, can according to the performance requirement flexible customization circuit of user, Realize the optimization between performance, power consumption and circuit area.Matrix parameter is curable to save circuit area, also dynamically configurable To meet different usage scenarios.
Preferably, customizing the number of dense computing engines, the optimization between performance, power consumption and circuit area is realized.
Preferably, the number of customization sparse calculation engine, realizes the optimization between performance, power consumption and circuit area.
Preferably, matrix parameter includes dense matrix information table, sparse matrix information table, control letter in step (5) Table is ceased,
Dense matrix information table: the first trip information of each list item preservation matrix；
Sparse matrix information table: the location information of each list item preservation matrix first trip non-zero value；
Control information table: each list item corresponds to each calculating clock cycle in control information table, and content includes dense matrix Information table allocation index and its significance bit, sparse matrix information table allocation index and its significance bit, information bit allocation index calculate End mark position.
The beneficial effects of the present invention are: only needing using a small amount of memory space, calculating speed is fast；It can be according to the property of user Energy demand flexible customization circuit, realizes the optimization between performance, power consumption and circuit area；Matrix parameter is curable to save electricity Road surface product, it is also dynamically configurable to meet different usage scenarios.
Detailed description of the invention
Fig. 1 is implementation method schematic diagram of the invention；
Fig. 2 is the implementation method schematic diagram of specific example one of the present invention；
Fig. 3 is the implementation method schematic diagram of specific example two of the present invention.
Specific embodiment
The present invention will be further described with reference to the accompanying drawings and detailed description.
A kind of QC-LDPC encryption algorithm, by constructing and selecting the check matrix H of special shape, the form of check matrix H It is as follows:
Wherein, BlkU is the length of original information bits u, and BlkP is the length of check bit p, and check bit p points are three parts [P1 P2 P3], P1Partial length is blkm, P3Length be blkn, P2Length be BlkP-blkm-blkn, codeword structure It is defined as [uP1 P2 P3]；
According to verification principle, H × [uP1 P2 P3]T=0, solution obtains,
(H″311+H313 H″21+(H312+H313 H22)H″11)uT+(H″311+H313 H″21+(H312+H313 H22)H″11)P1 T= 0；
Wherein, H11=[H '11 H″11], H21=[H '21 H″21], H311=[H '311 H″311]；
Define L=H '311+H313 H′21+(H312+H313 H22)H′11,
Define J=H "311+H313 H″21+(H312+H313 H22)H″11；
The form of check matrix H is adjusted to,
According to verification principle, H × [uP1 P2 P3]T=0, available check bit is,
P1=G0×uT
P2=H11×[u P1]T
P3=[H21 H22]×[u P1 P2]T
Wherein (G0=J-1× L), it is densifying loops matrix, H11, H21And H22For rarefaction cycles matrix.
As shown in Figure 1, a kind of implementation method of QC-LDPC encryption algorithm, specifically includes following part: fills unit: when When the length of original information bits u is not the integral multiple of QC length, 0 or 1 is filled in original information bits u, makes that the length is QC The integral multiple of length；When original information bits u length is the integral multiple of QC length, then do not need to fill；
Information bit caching: the performance of LDPC encoder is improved using two cachings of table tennis, if user is to LDPC performance It is of less demanding, then using one of caching in table tennis；
Dense/sparse matrix parameter: saving the calculating parameter of dense matrix and sparse matrix, in LDPC cataloged procedure, For controlling in each calculating clock cycle, which dense or sparse calculation engine participates in calculating；
Dense computing engines: each computing engines complete a dense QC multiplication of matrices within a calculating clock cycle It calculates；The number of dense computing engines can be customized, realizes the optimization between performance, power consumption and circuit area；
Sparse calculation engine: each computing engines complete a sparse QC multiplication of matrices within a calculating clock cycle It calculates；The number of sparse calculation engine can be customized, realizes the optimization between performance, power consumption and circuit area；
Exclusive or computing unit: the accumulation calculating function in matrix multiplication is completed using XOR operation；
Specific steps are as follows:
(1) original information bits u makes the length of original information bits u for the integral multiple of QC length by fills unit；
(2) performance for being improved LDPC encoder using two cachings of table tennis by the information bit u of fills unit, is entered In dense computing engines and dense computing engines；
(3) simultaneously, densifying loops matrix and rarefaction cycles matrix are configured, enters in dense/sparse matrix parameter, is used to It controls in each calculating clock cycle, which dense or sparse calculation engine participates in calculating；
(4) information bit u combination densifying loops matrix and rarefaction cycles matrix complete dense QC square by dense computing engines The multiplication of battle array calculates, and completes sparse QC multiplication of matrices by rarefaction cycles matrix and calculates；
(5) it after entering exclusive or computing unit, according to the configuration information of matrix parameter, is realized in matrix multiplication by exclusive or Accumulation function, final output check bit p；Matrix parameter includes dense matrix information table, sparse matrix information table, control information Table,
Dense matrix information table: the first trip information of each list item preservation matrix；
Sparse matrix information table: the location information of each list item preservation matrix first trip non-zero value；
Control information table: each list item corresponds to each calculating clock cycle in control information table, and content includes dense matrix Information table allocation index and its significance bit, sparse matrix information table allocation index and its significance bit, information bit allocation index calculate End mark position.
Assuming that the length of QC matrix is 128bit, the length of original information bits is 128 QC length, and the length of check bit is 16 QC length, wherein the length blkm of the part check bit p1 is 3 QC length, and the length blkn of p3 is 1 QC length, p2's Length is 12 QC length.The maximum column of check matrix is vertical to be no more than 5.Matrix form is as shown below,
Below according under above-mentioned supposed premise, providing two kinds of specific implementation examples, but the present invention is not limited to both implementations Example.
Specific example one:
User is of less demanding to single encoder throughput.Implementation in the design as shown in Fig. 2, will use single at this time A original information bits caching, using 1 dense matrix computing engines, uses 1 sparse matrix computing engines.
Specific example two:
For single encoder, user needs to reach highest coding throughput.Implementation is as shown in figure 3, originally at this time Two original information bits of table tennis will be used to cache in design, and using 3 dense matrix computing engines, use 5 sparse matrix meters Calculate engine.
For using 1 dense matrix computing engines and 1 sparse matrix computing engines, it is given below a kind of dense/dilute The specific implementation example of matrix parameter is dredged, but the present invention is not limited to the embodiment.
Comprising dense matrix information table, sparse matrix information table controls information table.
Dense matrix information table: for dense matrix, since other each rows of matrix can shift to obtain by first trip, only The first trip information of preservation matrix is needed, so each list item is 128bit in dense matrix information table.
Sparse matrix information table: for sparse matrix, other each rows of matrix can shift to obtain by first trip, and every There was only 1 non-zero value in a line, therefore only need the location information of preservation matrix first trip non-zero value, so the letter of sparse matrix Ceasing each list item in table is 7bit location information.
Control information table: each list item corresponds to each calculating clock cycle in control information table, and content includes dense matrix Information table allocation index and its significance bit, sparse matrix information table allocation index and its significance bit, information bit allocation index calculate End mark position.
This programme proposes that one kind by using part generator matrix G and part check matrix H, is counted from original information bits u The algorithm of check bit p is calculated, which only needs using a small amount of memory space, and calculating speed is fast.Also propose one kind algorithm Implementation method can be realized optimal between performance, power consumption and circuit area according to the performance requirement flexible customization circuit of user Change.Matrix parameter is curable to save circuit area, also dynamically configurable to meet different usage scenarios.

Claims (5)

1. a kind of QC-LDPC encryption algorithm, characterized in that by constructing and selecting the check matrix H of special shape, check matrix The form of H is as follows:
Wherein, BlkU is the length of information bit u, and BlkP is the length of check bit p, and check bit p points are three part [P1 P2 P3], P1Partial length is blkm, P3Length be blkn, P2Length be BlkP-blkm-blkn, codeword structure is defined as [u P1 P2 P3]；
According to verification principle, H × [uP1 P2 P3]T=0, solution obtains,
(H′311+H313H′21+(H312+H313H22))H′11)uT+(H″311+H313H″21+(H312+H313H22)H″11)P1 T=0；
Wherein, H11=[H'11 H”11], H21=[H'21 H”21], H311=[H'311 H”311]；
Define L=H '311+H313H′21+(H312+H313H22)H′11,
Define J=H "311+H313H″21+(H312+H313H22)H″11；
The form of check matrix H is adjusted to,
According to verification principle, H × [uP1 P2 P3]T=0, available check bit is,
P1=G0×uT
P2=H11×[u P1]T
P3=[H21 H22]×[u P1 P2]T
Wherein (G0=J-1× L), it is densifying loops matrix, H11, H21And H22For rarefaction cycles matrix.
2. a kind of implementation method of QC-LDPC encryption algorithm according to claim 1, characterized in that specifically include as follows Part:
Fills unit: when the length of original information bits u is not the integral multiple of QC length, in original information bits u fill 0 or 1, make that the length is the integral multiples of QC length；When original information bits u length is the integral multiple of QC length, then do not need to fill；
Information bit caching: the performance of LDPC encoder is improved using two cachings of table tennis, if user is to LDPC performance requirement It is not high, then using one of caching in table tennis；
Dense/sparse matrix parameter: the calculating parameter for saving dense matrix and sparse matrix is used in LDPC cataloged procedure It controls in each calculating clock cycle, which dense or sparse calculation engine participates in calculating；
Dense computing engines: each computing engines complete a dense QC multiplication of matrices meter within a calculating clock cycle It calculates；
Sparse calculation engine: each computing engines complete a sparse QC multiplication of matrices meter within a calculating clock cycle It calculates；
Exclusive or computing unit: the accumulation calculating function in matrix multiplication is completed using XOR operation；
Specific steps are as follows:
(1) original information bits u makes the length of original information bits u for the integral multiple of QC length by fills unit；
(2) performance for being improved LDPC encoder using two cachings of table tennis by the information bit u of fills unit, is entered dense In computing engines and dense computing engines；
(3) simultaneously, densifying loops matrix and rarefaction cycles matrix are configured, is entered in dense/sparse matrix parameter, for controlling In each calculating clock cycle, which dense or sparse calculation engine participates in calculating；
(4) information bit u combination densifying loops matrix and rarefaction cycles matrix complete dense QC matrix by dense computing engines Multiplication calculates, and completes sparse QC multiplication of matrices by rarefaction cycles matrix and calculates；
(5) it after entering exclusive or computing unit, according to the configuration information of matrix parameter, is realized by exclusive or tired in matrix multiplication Add function, final output check bit p.
3. a kind of implementation method of QC-LDPC encryption algorithm according to claim 2, characterized in that customize dense calculating The number of engine realizes the optimization between performance, power consumption and circuit area.
4. a kind of implementation method of QC-LDPC encryption algorithm according to claim 2, characterized in that customization sparse calculation The number of engine realizes the optimization between performance, power consumption and circuit area.
5. a kind of implementation method of QC-LDPC encryption algorithm according to claim 2, characterized in that in step (5), Matrix parameter includes dense matrix information table, sparse matrix information table, control information table, dense matrix information table: each list item The first trip information of preservation matrix；
Sparse matrix information table: the location information of each list item preservation matrix first trip non-zero value；
Control information table: each list item corresponds to each calculating clock cycle in control information table, and content includes dense matrix information Table address index and its significance bit, sparse matrix information table allocation index and its significance bit, information bit allocation index, calculating terminate Flag bit.
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CN106571830A (en) * 2016-11-04 2017-04-19 荣成市鼎通电子信息科技有限公司 LDPC encoder for secondary level full parallel input ring shift left in deep space communication
CN106656206A (en) * 2016-11-04 2017-05-10 荣成市鼎通电子信息科技有限公司 Two-level full parallel input ring left shift LDPC encoder in CDR

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014117836A1 (en) * 2013-01-31 2014-08-07 Intracom S.A. Telecom Solutions Ldpc code design and encoding apparatus enabling the adjustment of code rate and codelength
US20140298129A1 (en) * 2013-03-26 2014-10-02 Lsi Corporation Generating Partially Sparse Generator Matrix for a Quasi-Cyclic Low-Density Parity-Check Encoder
CN106571830A (en) * 2016-11-04 2017-04-19 荣成市鼎通电子信息科技有限公司 LDPC encoder for secondary level full parallel input ring shift left in deep space communication
CN106656206A (en) * 2016-11-04 2017-05-10 荣成市鼎通电子信息科技有限公司 Two-level full parallel input ring left shift LDPC encoder in CDR

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