CN102882532A - LDPC (low density parity check) encoder in CMMB (China mobile multimedia broadcasting) based on rotate right accumulation and encoding method - Google Patents
LDPC (low density parity check) encoder in CMMB (China mobile multimedia broadcasting) based on rotate right accumulation and encoding method Download PDFInfo
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Abstract
The invention relates to a scheme for encoding two different code rate QC (quasi-cyclic)-LDPC (low density parity check) codes in a CMMB (China mobile multimedia broadcasting) system. The scheme is characterized in that an encoder of QC-LDPC codes of the system is based on the rotate right accumulation mechanism and mainly comprises a controller, a vector storage, a rotate right meter, a rotate right accumulator and a parallel rotate left accumulator. The encoding method is simple in process, highly uniform in step, easy to implement, simplified in backward recursion operation and free of complex operations such as reading out-operating-writing back. The QC-LDPC encoder is compatible with multiple-code-rate and capable of obviously increasing encoding speed and effectively reducing logic resource demand, and has the advantages of easiness to implementation, high encoding speed, low resource consumption, low power consumption, low cost and the like.
Description
Technical field
The present invention relates to filed of mobile multimedia broadcasting, particularly the efficient implementation method of QC-LDPC code coder in a kind of CMMB system.
Background technology
Because the various distortions that exist in transmission channel and noise can produce transmitted signal and disturb, the situation that digital signal produces error code can appear in receiving terminal inevitably.In order to reduce the error rate, need to adopt channel coding technology.
Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with its excellent properties that approaches the Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.
The SRAA method is to utilize generator matrix G
QCEncode.The generator matrix G of QC-LDPC code
QCBy a * t b * b rank circular matrix G
I, j(1≤i≤a, the array that 1≤j≤t) consists of, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with the verification vector is high-density matrix.Serial SRAA method is finished first encoding needs ab+t clock cycle, needs (t+c) b register, cb two input and door and cb two input XOR gate.In addition, also need the first trip of acb bit ROM storage circular matrix.
The CMMB standard adopted 1/2 with the LDPC code of 3/4 two kinds of different code check η, by the ranks exchange, check matrix H can be transformed the circulation form H that is as the criterion
QC, H
QCCorresponding accurate circulation generator matrix G
QCFor these two kinds of QC-LDPC codes, t=36 and b=256 are arranged all.Fig. 1 has provided parameter a and the c under the different code check η.
The existing solution of QC-LDPC coding is to adopt serial SRAA method in the CMMB standard, and 2 kinds of required scramble times of code check are respectively 4644 and 6948 clock cycle.Logical resource needs 13824 registers, 4608 two inputs and door and 4608 two input XOR gate, and this is that parameter by code check η=1/2 correspondence determines.In addition, two kinds of code checks need 145,152 bit ROM to store the first trip of circular matrix altogether.When adopting hardware to realize, so large storage demand meeting increases equipment cost, and the scramble time is longer.
Summary of the invention
What exist in the existing implementation for the multi code Rate of Chinese character QC-LDPC of CMMB system coding needs mass storage and the slow shortcoming of coding rate, the invention provides a kind of high efficient coding method that adds up based on ring shift right, when obviously improving coding rate, effectively reduce the demand of memory and logical resource.
As shown in Figure 5, the encoder based on multi code Rate of Chinese character QC-LDPC code in the cumulative CMMB standard of ring shift right mainly is comprised of 5 parts: controller, vector memory, ring shift right table, ring shift right accumulator and the cardiopulmonary bypass in beating heart accumulator (parallel C LSA) that moves to left.Whole cataloged procedure divided for 5 steps finished: the 1st step, zero clearing part verification vector p
x, input message vector s; In the 2nd step, the ring shift right accumulator uses whole ring shift right table calculating section verification vector p line by line
yWith vectorial q; In the 3rd step, use parallel C LSA calculating section verification vector p
xIn the 4th step, the ring shift right accumulator uses the capable calculating section verification vector of the front c-u of ring shift right table p line by line
yThe 5th step, output codons v.Above-mentioned cataloged procedure is simple, and the step consistency is strong, is easy to realize, has simplified the backward recursion computing, need not to read-computing-write back this complex operations.
The compatible multi code Rate of Chinese character of QC-LDPC encoder provided by the invention can effectively reduce memory and logical resource demand, thereby reach the purpose that reduces hardware cost and power consumption when obviously improving coding rate.
Can be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 is parameter a, c, u and the ρ that has provided under the different code check η;
Fig. 2 is near lower triangular check matrix H after the ranks exchange
QCStructural representation;
Fig. 3 is code check η=1/2 o'clock QC-LDPC code H
QCThe piece at permutation matrix place row number and ring shift right figure place during each piece is capable;
Fig. 4 is code check η=3/4 o'clock QC-LDPC code H
QCThe piece at permutation matrix place row number and ring shift right figure place during each piece is capable;
Fig. 5 is the QC-LDPC code coder overall structure of compatible 2 kinds of code checks in the CMMB standard;
Fig. 6 has provided code check η=1/2 o'clock H
ZeroThe piece at the quantity of permutation matrix, place row number and ring shift right figure place during each piece is capable;
Fig. 7 has provided code check η=3/4 o'clock H
ZeroThe piece at the quantity of permutation matrix, place row number and ring shift right figure place during each piece is capable;
Fig. 8 has provided H under the different code checks
ZeroDuring all pieces are capable the total α of permutation matrix and front c-u piece capable in the total β of permutation matrix;
Fig. 9 is the structural representation of ring shift right accumulator;
Figure 10 is the structural representation of parallel C LSA;
Figure 11 is the hardware resource consumption of each part of encoder and whole circuit;
Figure 12 is each coding step and required processing time of whole cataloged procedure;
Figure 13 has compared traditional serial SRAA method and coding rate of the present invention and resource consumption.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
The QC-LDPC code is the special LDPC code of a class, its generator matrix G
QCAnd check matrix H
QCAll be the array that is consisted of by circular matrix, have segmentation circulation characteristics, so be called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of one of lastrow (first trip is footline) ring shift right; From the angle of row, each row of circular matrix all are that previous column (first is terminal column) circulation moves down one result.The set that the row vector of circular matrix consists of is identical with the set of column vector formation, therefore, circular matrix fully can by it first trip or first characterize.The row of circular matrix is heavy identical with column weight, is denoted as w.If w=0, this circular matrix is full null matrix so.If w=1, this circular matrix is replaceable so, is called permutation matrix, and it can be by obtaining the some positions of unit matrix I ring shift right.The check matrix H of QC-LDPC code
QCBy c * t b * b rank circular matrix H
I, j(1≤i≤c, the following array that 1≤j≤t) consists of:
Check matrix H
QCThe capable and b of continuous b row be called as respectively the capable and piece row of piece.
The CMMB standard adopted 1/2 with the LDPC code of 3/4 two kinds of different code check η, by the ranks exchange, check matrix H can be transformed to the accurate circulation form H of near lower triangular
QCCheck matrix H
QCCorresponding code word v=(s, p), H
QCFront a piece row corresponding be information vector s, that rear c piece row are corresponding is verification vector p.Take the b bit as one section, information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a); Verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c).The CMMB standard has adopted the QC-LDPC code of 2 kinds of different code checks, and Fig. 1 has provided parameter a and the c under the different code check η.For these 2 kinds of QC-LDPC codes, check matrix H
QCIn all circular matrixes are full null matrix (w=0) or are permutation matrix (w=1), and t=36 and b=256.
For CMMB standard, check matrix H
QCThe near lower triangular shape is arranged, as shown in Figure 2.In Fig. 2, the unit of all submatrixs all is b bit rather than 1 bit.T is lower triangular matrix, and u has reflected H
QCWith the degree of closeness of lower triangular matrix, H
QCEvery row in ρ permutation matrix arranged, Fig. 1 has provided parameters u and the ρ under 2 kinds of code checks.Fig. 3 and 4 has provided respectively η=1/2 and 3/4 o'clock H
QCThe piece at permutation matrix place row number and ring shift right figure place during each piece is capable.
In check matrix H shown in Figure 2
QCCorresponding code word v=(s, p)=(s, p
x, p
y) in, matrix A and C corresponding informance vector s, the corresponding a part of verification vector of matrix B and D p
x=(p
1, p
2..., p
u), matrix T and E be corresponding remaining verification vector p then
y=(p
U+1, p
U+2..., p
c).Above-mentioned matrix and vector satisfy following relation:
p
x T=Φ(ET
-1As
T+Cs
T)(2)
p
y T=T
-1(As
T+Bp
x T)(3)
Wherein, Φ=(ET
-1B+D)
-1, subscript
TWith
-1Represent respectively transposition and contrary.As everyone knows, contrary, the product of circular matrix and remain circular matrix.Therefore, Φ also is the array that is made of circular matrix.Yet although matrix E, T, B and D are sparse matrixes, Φ is no longer sparse but highdensity.
According to formula (2) and (3), can obtain the general coding flow process of QC-LDPC code, may further comprise the steps:
(1) input message vector s, zero clearing part verification vector p
x
(2) calculating section verification vector p
y T=T
-1(As
T+ Bp
x T) and vectorial q
T=CS
T+ Ep
y T
(3) calculating section verification vector p
x T=Φ q
T
(4) calculating section verification vector p
y T=T
-1(As
T+ Bp
x T).
(5) parallel output code word v=(s, p
x, p
y).
According to above-mentioned coding flow process, Fig. 5 has provided the encoder that is applicable to 2 kinds of code check QC-LDPC codes in the CMMB standard, it is based on the cumulative mechanism of ring shift right, mainly is comprised of controller, vector memory, ring shift right table, ring shift right accumulator and cardiopulmonary bypass in beating heart five functional modules of accumulator (parallel C LSA) that move to left.Vector memory is stored vectorial q and code word v=(v
1, v
2..., v
t), its bit wide is the b bit, the code section v of v can be used in the space of vector memory
1, v
2..., v
tIdentify.The ring shift right figure place of ring shift right table storage circular matrix and the piece at place row number.The ring shift right accumulator utilizes ring shift right table compute vector q and part verification vector p
yParallel C LSA is used for calculating section verification vector p
x
When making the ring shift right table, need to be to check matrix H
QCFurther process and obtain H
ZeroSpecific as follows: with the unit matrix zero clearing on the lower triangular matrix T diagonal, with the matrix D zero clearing.On this basis, statistics H
ZeroThe quantity Number[i of permutation matrix during the piece of the i(1≤i≤c) is capable] (Number[i]≤11), and the ring shift right figure place Offset[i of each permutation matrix] [j] (1≤j≤Number[i], 0≤Offset[i] the piece row Column[i at [j]＜b) and place] [j] (1≤j≤Number[i], 1≤Column[i] [j]≤t).Fig. 6 and 7 has provided respectively η=1/2 and 3/4 o'clock H
ZeroThe piece at the quantity of permutation matrix, place row number and ring shift right figure place during each piece is capable, Fig. 8 has provided H under the different code checks
ZeroDuring all pieces are capable the total α of permutation matrix and front c-u piece capable in the total β of permutation matrix.The ring shift right figure place Offset[i of each unit storage permutation matrix of ring shift right table] the piece row Column[i at [j] and place] [j], they represent with 8 bits and 6 bits respectively, so the bit wide of each unit of ring shift right table is 14 bits.
Fig. 9 is the structural representation of ring shift right accumulator, and it mainly is comprised of ring shift right device and accumulator, uses ring shift right table compute vector q and part verification vector p
yWith ring shift right table the i(1≤i≤when c) the capable data of piece were calculated, accumulator initialization was 0.At the j(1≤j≤Number[i]) the individual clock cycle, the ring shift right device was to the code section v of input when arriving
Column[i] [j]Ring shift right Offset[i] [j] position, acquired results and accumulator are cumulative.Aforesaid operations repeats Number[i] inferior, the content of accumulator stores v into
iIn the corresponding vector memory space.Vector memory space v
A+u+1~ v
tThe data of middle storage have consisted of part verification vector p
y, and v
A+1~ v
A+uThe data of middle storage have consisted of vectorial q.
Figure 10 is the structural representation of parallel C LSA, and it is mainly by register R
1～R
10, b position two input and a door M
I, j(1≤i, j≤5) and b position two input XOR gate A
I, j(1≤i, j≤5) form, and are used for calculating section verification vector p
xWhen initial, register R
1～R
uThat store is vectorial q.When each clock arrives, register R
1～R
5Serial moves to left 1 time separately, two inputs of b position and door M
I, jCarry out the multiplying of scalar and vector, M
I, 1～M
I, 5Product and register R
I+5The results added that the serial ring shift left is 1 time, and deposit back register R
I+5Repeat said process, b clock cycle of process finished computing.At this moment, register R
6～R
10That store is part verification vector p
xNext, p
xTransfer to vector memory space v
A+1~ v
A+u
The invention provides a kind of high efficient coding method of variable bit rate QC-LDPC code, in conjunction with the encoder (as shown in Figure 5) of multi code Rate of Chinese character QC-LDPC code in the CMMB standard, its coding step is described below:
The 1st step, zero clearing part verification vector p
xCorresponding vector memory space v
A+1~ v
A+u, input message vector s is with message segment s
1~ s
aBe stored in respectively vector memory space v
1~ v
a
In the 2nd step, the ring shift right accumulator uses whole ring shift right table calculating section verification vector p line by line
yWith vectorial q, and they are stored in respectively vector memory space v
A+u+1~ v
tAnd v
A+1~ v
A+u
In the 3rd step, use parallel C LSA calculating section verification vector p
x, and with result store in vector memory space v
A+1~ v
A+u
In the 4th step, the ring shift right accumulator uses the capable calculating section verification vector of the front c-u of ring shift right table p line by line
y, and with result store in vector memory space v
A+u+1~ v
t, note the p that the 2nd step obtained
yResults of intermediate calculations, and the p that this step obtains
yIt is final calculation result;
The 5th step, output codons v=(s, p
x, p
y).
Above-mentioned cataloged procedure is simple, is easy to realize.The 2nd step and the 4th step consistency are strong, have greatly reduced the programing work amount.The backward recursion computing is simplified, and need not to read-computing-write back this complex operations, has shortened the scramble time.
Figure 11 has summed up the hardware resource consumption of each part of encoder and whole circuit.Wherein, the ring shift right device adopts 7 stage pipeline structure.
Figure 12 has summed up each coding step and required processing time of whole cataloged procedure.
Figure 13 has compared traditional serial SRAA method and coding rate of the present invention and resource consumption.No matter can know from figure and see, be coding rate, or logical resource, especially memory, and performance of the present invention all is better than serial SRAA method.Memory required for the present invention only for 8% of serial SRAA method, has used less register, and the amount of expending is 33% of serial SRAA method.For η=1/2 and 3/4, coding rate of the present invention is respectively 9.9 and 14.3 times of serial SRAA method.
As fully visible, compare with traditional serial SRAA method, the present invention has the realization of being easy to, coding rate is fast, resource consumption is few, power consumption is little, low cost and other advantages.
Above-described embodiment is more preferably embodiment of the present invention, and the common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacement all should be included in protection scope of the present invention.
Claims (4)
1. encoder that is suitable for 2 kinds of different code check QC-LDPC codes in the CMMB standard, the near lower triangular check matrix H of QC-LDPC code
QCBe the array that is made of c * t b * b rank circular matrix, u has reflected H
QCDegree of closeness with lower triangular matrix, wherein, c, t, b and u are all positive integer, t=a+c, and 2 kinds of different code check η are respectively 1/2,3/4, for these 2 kinds different code check QC-LDPC codes, t=36 and b=256 are all arranged, and 2 kinds of parameter a corresponding to different code checks are respectively 18,27,2 kind of parameter c corresponding to different code checks is respectively 18,9,2 kinds of parameters u corresponding to different code checks are respectively 5,3, check matrix H
QCCorresponding code word v=(s, p)=(s, p
x, p
y), H
QCFront a piece row corresponding be information vector s, that rear c piece row are corresponding is verification vector p, take the b bit as one section, information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c), v is divided into the t section, i.e. v=(v
1, v
2..., v
t), p
x=(p
1, p
2..., p
u), py=(p
U+1, p
U+2..., p
c), it is characterized in that described encoder comprises following parts:
Controller, the operation of the input of control information vector, the output of code word and other parts;
Vector memory is used for storing vectorial q and code word v, its space code section v of v
1, v
2..., v
tIdentify;
The ring shift right table is used for storage matrix H
ZeroIn the piece row number at the ring shift right figure place of all circular matrixes and place, wherein, H
ZeroWith H
QCThe diagonal of middle lower triangular matrix T and whole matrix D zero clearing obtain;
The ring shift right accumulator is used for compute vector q and part verification vector p
y
The cardiopulmonary bypass in beating heart accumulator that moves to left is used for calculating section verification vector p
x
2. encoder as claimed in claim 1, it is characterized in that, described ring shift right accumulator mainly is comprised of ring shift right device and accumulator, the ring shift right device is to the some positions of code section ring shift right of input, acquired results and accumulator are cumulative, repeat aforesaid operations repeatedly, after computing is complete, the content of accumulator stores in the vector memory space, vector memory space v
A+u+1~ v
tThe data of middle storage have consisted of part verification vector p
y, v
A+1~ v
A+uThe data of middle storage have consisted of vectorial q.
3. encoder as claimed in claim 1 is characterized in that, described cardiopulmonary bypass in beating heart moves to left accumulator mainly by register R
1～R
10, b position two input and a door M
I, jWith b position two input XOR gate A
I, jForm, wherein, 1≤i, j≤5 are used for calculating section verification vector p
x:
When initial, register R
1～R
uThat store is vectorial q;
When each clock arrives, register R
1～R
5Serial moves to left 1 time separately, two inputs of b position and door M
I, jCarry out the multiplying of scalar and vector, M
I, 1～M
I, 5Product and register R
I+5The results added that the serial ring shift left is 1 time, and deposit back register R
I+5
Repeat said process, b clock cycle of process finished computing, register R
6～R
10That store is part verification vector p
x, it is transferred to vector memory space v
A+1~ v
A+u
4. coding method that is suitable for 2 kinds of different code check QC-LDPC codes in the CMMB standard, the near lower triangular check matrix H of QC-LDPC code
QCBe the array that is made of c * t b * b rank circular matrix, u has reflected H
QCDegree of closeness with lower triangular matrix, wherein, c, t, b and u are all positive integer, t=a+c, and 2 kinds of different code check η are respectively 1/2,3/4, for these 2 kinds different code check QC-LDPC codes, t=36 and b=256 are all arranged, and 2 kinds of parameter a corresponding to different code checks are respectively 18,27,2 kind of parameter c corresponding to different code checks is respectively 18,9,2 kinds of parameters u corresponding to different code checks are respectively 5,3, check matrix H
QCCorresponding code word v=(s, p)=(s, p
x, p
y), H
QCFront a piece row corresponding be information vector s, that rear c piece row are corresponding is verification vector p, take the b bit as one section, information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c), v is divided into the t section, i.e. v=(v
1, v
2..., v
t), p
x=(p
1, p
2..., p
u), p
y=(p
U+1, p
U+2..., p
c), it is characterized in that described coding method may further comprise the steps:
The 1st step, zero clearing part verification vector p
xCorresponding vector memory space v
A+1~ v
A+u, input message vector s is with message segment s
1～s
aBe stored in respectively vector memory space v
1~ v
a
In the 2nd step, the ring shift right accumulator uses whole ring shift right table calculating section verification vector p line by line
yWith vectorial q, and they are stored in respectively vector memory space v
A+u+1~ v
tAnd v
A+1~ v
A+u
In the 3rd step, use the cardiopulmonary bypass in beating heart accumulator computes part verification vector p that moves to left
x, and with result store in vector memory space v
A+1~ v
A+u
In the 4th step, the ring shift right accumulator uses the capable calculating section verification vector of the front c-u of ring shift right table p line by line
y, and with result store in vector memory space v
A+u+1~ v
t, note the p that the 2nd step obtained
yResults of intermediate calculations, and the p that this step obtains
yIt is final calculation result;
The 5th step, output codons v=(s, p
x, p
y).
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| CN103236858A (en) * | 2013-04-19 | 2013-08-07 | 荣成市鼎通电子信息科技有限公司 | Rotate left-based quasi-cyclic low density parity check (LDPC) serial encoder in China mobile multimedia broadcasting (CMMB) |
| CN103236853A (en) * | 2013-04-19 | 2013-08-07 | 荣成市鼎通电子信息科技有限公司 | Quasi-cyclic matrix serial multiplier without multiply operation in CMMB (China Mobile Multimedia Broadcasting) |
| CN103257843A (en) * | 2013-04-19 | 2013-08-21 | 荣成市鼎通电子信息科技有限公司 | Quasi cyclic matrix serial multiplier free of multiplication |
| CN103268215A (en) * | 2013-04-19 | 2013-08-28 | 荣成市鼎通电子信息科技有限公司 | Rotate-left-based quasi-cyclic matrix serial multiplier for China mobile multimedia broadcasting (CMMB) |
| CN103269224A (en) * | 2013-04-19 | 2013-08-28 | 荣成市鼎通电子信息科技有限公司 | Quasi-cyclic matrix high speed multiplier in CMMB (China mobile multimedia broadcasting) without memory |
| CN111046334A (en) * | 2019-12-18 | 2020-04-21 | 中国传媒大学 | Cyclic matrix fast generation method based on digital signal processor |
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| CN103236858A (en) * | 2013-04-19 | 2013-08-07 | 荣成市鼎通电子信息科技有限公司 | Rotate left-based quasi-cyclic low density parity check (LDPC) serial encoder in China mobile multimedia broadcasting (CMMB) |
| CN103236853A (en) * | 2013-04-19 | 2013-08-07 | 荣成市鼎通电子信息科技有限公司 | Quasi-cyclic matrix serial multiplier without multiply operation in CMMB (China Mobile Multimedia Broadcasting) |
| CN103257843A (en) * | 2013-04-19 | 2013-08-21 | 荣成市鼎通电子信息科技有限公司 | Quasi cyclic matrix serial multiplier free of multiplication |
| CN103268215A (en) * | 2013-04-19 | 2013-08-28 | 荣成市鼎通电子信息科技有限公司 | Rotate-left-based quasi-cyclic matrix serial multiplier for China mobile multimedia broadcasting (CMMB) |
| CN103269224A (en) * | 2013-04-19 | 2013-08-28 | 荣成市鼎通电子信息科技有限公司 | Quasi-cyclic matrix high speed multiplier in CMMB (China mobile multimedia broadcasting) without memory |
| CN111046334A (en) * | 2019-12-18 | 2020-04-21 | 中国传媒大学 | Cyclic matrix fast generation method based on digital signal processor |
| CN111046334B (en) * | 2019-12-18 | 2023-10-13 | 中国传媒大学 | Method for rapidly generating cyclic matrix based on digital signal processor |
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