CN103236853A - Quasi-cyclic matrix serial multiplier without multiply operation in CMMB (China Mobile Multimedia Broadcasting) - Google Patents

Abstract

The invention provides a quasi-cyclic matrix serial multiplier without multiply operation in CMMB (China Mobile Multimedia Broadcasting), which is used for realizing multiply operation of a vector m and a quasi-cyclic matrix F in triangular encoding under the approximation of CMMB standard multi-code rate QC-LDPC (Quasi-Low Density Parity-Check). The multiplier comprises five generator polynomial lookup tables for storing cyclic matrix generator polynomials and 256-bit zero vector in all code rate matrixes F in advance, five 256-bit binary adders for carrying out modulo-two sum on the output of the generator polynomial lookup tables and the content of a shift register, and five 256-bit shift registers for storing the sum of 1-bit ring shift left. The quasi-cyclic matrix serial multiplier provided by the invention is compatible with all code rates, eliminates the multiply operation, and has the advantages of being little in logical resource, simple in structure, small in power consumption, low in cost and the like.

Description

Accurate circular matrix serial multiplier among the CMMB of no multiplying

Technical field

The present invention relates to field of channel coding, particularly the accurate circular matrix serial multiplier in a kind of CMMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) sign indicating number is one of channel coding technology efficiently, and QC-LDPC(Quasic-LDPC, QC-LDPC) sign indicating number is a kind of special LDPC sign indicating number.Generator matrix G and the check matrix H of QC-LDPC sign indicating number all are the arrays that is made of circular matrix, have the characteristics of segmentation circulation, so be called as the QC-LDPC sign indicating number.The first trip of circular matrix is the result of 1 of footline ring shift right, and all the other each provisional capitals are results of 1 of its lastrow ring shift right, and therefore, circular matrix is characterized by its first trip fully.Usually, the first trip of circular matrix is called as its generator polynomial.

When adopting the near lower triangular coding method that the QC-LDPC sign indicating number is encoded, by the ranks exchange, check matrix H is transformed near lower triangular shape H _ALT, it is composed as follows by 6 sub-matrixes:

$H_{\mathrm{ALT}}=\left[\begin{array}{ccc}A& B& L\\ C& D& E\end{array}\right]---\left(1\right)$

Wherein, L is lower triangular matrix.H _ALTCorresponding code word v _ALT=(s, p, q), and matrix A and C corresponding informance vector s, the corresponding a part of verification vector of matrix B and D p, matrix L and E be corresponding remaining verification vector q then.The method of calculating section verification vector p is as follows:

p＝s(C+EL ^-1A) ^Τ((D+EL ^-1B) ^-1) ^Τ (2)

Wherein, subscript ^-1With ^ΤRepresent respectively matrix inversion and transposition.Order

m＝s(C+EL ^-1A) ^Τ (3)

F＝((D+EL ^-1B) ^-1) ^Τ (4)

Then vectorial m and matrix F satisfy following relation:

p＝mF (5)

Matrix F is by following u * u b * b rank circular matrix F _{I, j}(0≤i＜u, the accurate circular matrix that 0≤j＜u) constitutes:

Capable and the b of the continuous b of F row are called as the capable and piece row of piece respectively.By formula (6) as can be known, F has the capable and u piece row of u piece.Make f _{I, j}Be circular matrix F _{I, j}Generator polynomial.

Make vectorial m=(e ₀, e ₁..., e _{U * b-1}), part verification vector p=(d ₀, d ₁..., d _{U * b-1}).Be one section with the b bit, vectorial m and part verification vector p all are divided into the u section, i.e. m=(m ₀, m ₁..., m _U-1) and p=(p ₀, p ₁..., p _U-1).By formula (5) as can be known, the j section p of part verification vector _jSatisfy

p _j＝m ₀F _0,j+m ₁F _1,j+…+m _iF _i,j+…+m _u-1F _u-1,j (7)

Wherein, 0≤i＜u, 0≤j＜u.Order

With

Be respectively generator polynomial f _{I, j}The result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.So, the i item on formula (7) equal sign the right is deployable is

$m_i{F}_{i,j}=e_{i\×b}{f}_{i,j}^{r\left(0\right)}+e_{i\×b+1}{f}_{i,j}^{r\left(1\right)}+\·\·\·+e_{i\×b+b-1}{f}_{i,j}^{r(b-1)}---\left(8\right)$

Formula (5) relates to the multiplication of vector and accurate circular matrix, and u the I type shift register that be based on that extensively adopts adds accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) scheme of circuit at present.Fig. 1 is the functional block diagram of single SRAA-I circuit, and vectorial m serial by turn sends into this circuit.When using SRAA-I circuit calculation check section p _j(during 0≤j＜u), the generator polynomial look-up table is stored all generator polynomials of the j piece row of accurate circular matrix F in advance, and accumulator is cleared initialization.When the 0th clock cycle arrived, shift register loaded the 0th row of F, the generator polynomial of j piece row from the generator polynomial look-up table

, bit e ₀Move into circuit, and with the content of shift register

Carry out scalar and take advantage of product Add with content 0 mould 2 of accumulator and

Deposit back accumulator.When the 1st clock cycle arrives, 1 of shift register ring shift right, content becomes

, bit e ₁Move into circuit, and with the content of shift register Carry out scalar and take advantage of product

Content with accumulator

Mould 2 add and

Deposit back accumulator.Above-mentioned moving to right-take advantage of-Jia-storing process is proceeded down.When b-1 clock cycle finishes, bit e _B-1Moved into circuit, that cumulative adder stores is part and m at this moment ₀F _{0, j}, this is array section m ₀To p _jContribution.When b clock cycle arrived, shift register loaded the 1st row of F, the generator polynomial of j piece row from the generator polynomial look-up table

, repeat above-mentioned moving to right-take advantage of-Jia-storing process.As array section m ₁When moving into circuit fully, cumulative adder stores be the part and m ₀F _{0, j}+ m ₁F _{1, j}Repeat said process, move into circuit up to the whole serials of whole vectorial m.At this moment, that cumulative adder stores is verification section p _jUse u SRAA-I circuit can constitute accurate circular matrix serial multiplier shown in Figure 2, it obtains u verification section simultaneously in u * b clock cycle.This scheme needs 2 * u * b register, u * b two input and door and u * b two input XOR gate, also needs the generator polynomial of u u * b bit ROM storage circular matrix.

The CMMB standard has adopted code check η=0.5 and 0.75 two kind of QC-LDPC sign indicating number, and b=256 is all arranged.Be respectively 5 and 3 for code check η=0.5 and 0.75, u.

Be compatible 2 kinds of code checks, the existing solution of accurate circular matrix serial multiplication is based on 5 SRAA-I circuit in the CMMB standard QC-LDPC near lower triangular coding, need 2560 registers, 1280 two inputs and door and 1280 two input XOR gate, the circular matrix generator polynomial that also needs the ROM of 3 2048 bits to store the 0th, 1,2 row of 2 kinds of accurate circular matrix F of code check respectively, the circular matrix generator polynomial of the 3rd, 4 row of the ROM storage η=0.5 code check F of 2 1280 bits.The shortcoming of this scheme is that register quantity is big, needs to finish multiplying with door in a large number, and so many logical resource will certainly cause that the power consumption of circuit is big, cost is high.

Summary of the invention

There is the shortcoming that power consumption is big, cost is high in the existing implementation of accurate circular matrix serial multiplication in the CMMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding, at these technical problems, the invention provides a kind of accurate circular matrix serial multiplier that does not have multiplying.

As shown in Figure 4, the accurate circular matrix serial multiplier in the CMMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding mainly is made up of 3 parts: generator polynomial look-up table, b position binary adder and shift register.Multiplication process divided for 3 steps finished: the 1st step, zero clearing shift register R ₀, R ₁..., R ₄The 2nd step, input bit e _k(0≤k＜u * b), generator polynomial look-up table L ₀, L ₁..., L ₄According to e _k=the 1 or 0 accurate circular matrix F of bit rate output η i=[k/b respectively] (symbol [k/b] expression is not more than the maximum integer of k/b) during piece is capable the 0th, 1 ..., the generator polynomial of 4 row or b position null vector, generator polynomial look-up table L ₀, L ₁..., L ₄Output respectively by b position binary adder A ₀, A ₁..., A ₄With shift register R ₀, R ₁..., R ₄The content addition, b position binary adder A ₀, A ₁..., A ₄And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R ₄The 3rd step be that step-length increases progressively the value that changes k with 1, repeated the 2nd step u * b time, import up to whole vectorial m to finish, at this moment, shift register R ₀, R ₁..., R _U-1That store is respectively verification section p ₀, p ₁..., p _U-1, they have constituted part verification vector p=(p ₀, p ₁..., p _U-1).

Accurate circular matrix serial multiplier provided by the invention is simple in structure, and the QC-LDPC sign indicating number of all code checks in the compatible CMMB standard is removed multiplying, reduces logical resource, reduces power consumption, saves cost.

Can be further understood by following detailed description and accompanying drawings about advantage of the present invention and method.

Description of drawings

Fig. 1 is the functional block diagram that I type shift register adds accumulator SRAA-I circuit;

Fig. 2 is the accurate circular matrix serial multiplier that is made of u SRAA-I circuit;

Fig. 3 is the functional block diagram of selecting to add shift register SASR circuit;

Fig. 4 is a kind of accurate circular matrix serial multiplier that does not have multiplying that is made of 5 SASR circuit.

Embodiment

Below in conjunction with accompanying drawing preferred embodiment of the present invention is elaborated, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that protection scope of the present invention is made more explicit defining.

Since the generator polynomial f with circular matrix _{I, j}Ring shift right n position is equivalent to its ring shift left b-n position, namely Formula (8) can be rewritten as so

$m_i{F}_{i,j}=e_{i\×b}{f}_{i,j}^{l\left(b\right)}+e_{i\×b+1}{f}_{i,j}^{l(b-1)}+\·\·\·+e_{i\×b+b-1}{f}_{i,j}^{l\left(1\right)}$

$={\left(e_{i\×b}{f}_{i,j}\right)}^{l\left(b\right)}+{\left(e_{i\×b+1}{f}_{i,j}\right)}^{l(b-1)}+\·\·\·+{\left(e_{i\×b+b-1}{f}_{i,j}\right)}^{l\left(1\right)}$

$={({(0+e_{i\×b}{f}_{i,j})}^{l\left(1\right)}+e_{i\×b+1}{f}_{i,j})}^{l(b-1)}+\·\·\·+{\left(e_{i\×b+b-1}{f}_{i,j}\right)}^{l\left(1\right)}---\left(9\right)$

$={({(0+e_{i\×b}{f}_{i,j})}^{l\left(1\right)}+e_{i\×b+1}{f}_{i,j})}^{l(b-1)}+\·\·\·+{\left(e_{i\×b+b-1}{f}_{i,j}\right)}^{l\left(1\right)}$

$={(\·\·\·{({(0+e_{i\×b}{f}_{i,j})}^{l\left(1\right)}+e_{i\×b+1}{f}_{i,j})}^{l\left(1\right)}+\·\·\·+e_{i\×b+b-1}{f}_{i,j})}^{l\left(1\right)}$

Compare with formula (8), the remarkable advantage of formula (9) is generator polynomial f _{I, j}Need not ring shift right.Product term in the very big simplified style (9) of this characteristics energy: with e _{I * b}f _{I, j}Be example, if e _{I * b}=1, e so _{I * b}f _{I, j}=f _{I, j}Otherwise product is b position null vector.Obviously, this is the operation principle of a typical alternative selector, and its input is f _{I, j}With b position null vector, control end is e _{I * b}So just removed the multiplying in the formula (9).Formula (9) is simplified to the process of a selection-Jia-move to left-store, and it realizes adding shift register (Selecter-Adder-Shift-Register, SASR) circuit with selection.Fig. 3 is the functional block diagram of SASR circuit, and vectorial m is sent into this circuit by serial by turn.When using SASR circuit calculation check section p _j(during 0≤j＜u), the generator polynomial look-up table is stored all generator polynomials and 1 b position null vector of the j piece row of accurate circular matrix F in advance, and shift register is cleared initialization.When the 0th clock cycle arrives, bit e ₀Move into circuit, the generator polynomial look-up table is according to e ₀The generator polynomial f of the 0th row of=1 or 0 output F, j piece row _{0, j}Or b position null vector, the output of generator polynomial look-up table and the content of shift register 0 mould 2 add, and e ₀f _{0, j}Result (the 0+e that ring shift left is 1 ₀f _{0, j}) ^{L (1)}Deposit the travelling backwards bit register.When the 1st clock cycle arrives, bit e ₁Move into circuit, the generator polynomial look-up table is according to e ₁=1 or 0 output f _{0, j}Or b position null vector, the content (0+e of the output of generator polynomial look-up table and shift register ₀f _{0, j}) ^{L (1)}Mould 2 adds and (0+e ₀f _{0, j}) ^{L (1)}+ e ₁f _{0, j}The result ((0+e that ring shift left is 1 ₀f _{0, j}) ^{L (1)}+ e ₁f _{0, j}) ^{L (1)}Deposit the travelling backwards bit register.Above-mentioned selection-Jia-move to left-storing process is proceeded down.When b-1 clock cycle finishes, bit e _B-1Moved into circuit, that this moment, shift register was stored is part and m ₀F _{0, j}, this is array section m ₀To p _jContribution.When b clock cycle arrived, the generator polynomial look-up table was according to the 1st row of the data bit output F of vectorial m, the generator polynomial f of j piece row _{1, j}Or b position null vector, repeat above-mentioned selection-Jia-move to left-storing process.As array section m ₁When moving into circuit fully, that shift register is stored is part and m ₀F _{0, j}+ m ₁F _{1, j}Repeat said process, move into circuit up to the whole serials of whole vectorial m.At this moment, that the shift register storage is verification section p _j

Fig. 4 has provided a kind of accurate circular matrix serial multiplier that does not have multiplying that is made of 5 SASR circuit, is made up of generator polynomial look-up table, b position binary adder and three kinds of functional modules of shift register.Generator polynomial look-up table L ₀, L ₁..., L ₄The accurate circular matrix F the 0th, 1 of all code checks that prestores respectively ..., circular matrix generator polynomial and b position null vector in 4 row.Generator polynomial look-up table L ₀, L ₁..., L ₄Output respectively with shift register R ₀, R ₁..., R ₄The content addition, these 5 nodulo-2 additions are respectively by b position binary adder A ₀, A ₁..., A ₄Finish.B position binary adder A ₀, A ₁..., A ₄And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R ₄

Generator polynomial look-up table L ₀, L ₁..., L ₄Store circular matrix generator polynomial and b position null vector among the accurate circular matrix F of all code checks.Generator polynomial look-up table L ₀～L ₂Store all generator polynomials and b position null vector in the 0th～2 row of two kinds of code check F respectively, for arbitrary row, store the 0th, 1 successively ..., the generator polynomial of the capable correspondence of u-1 piece is stored 1 b position null vector at last.Generator polynomial look-up table L ₃, L ₄Store all generator polynomials and b position null vector in the 3rd, 4 row of η=0.5 code check F respectively, for arbitrary row, store the 0th, 1 successively ..., the generator polynomial of the capable correspondence of u-1 piece is stored 1 b position null vector at last.

The invention provides a kind of accurate circular matrix serial multiplication that does not have multiplying, 2 kinds of code check QC-LDPC sign indicating numbers in its compatible CMMB standard, its multiplication step is described below:

The 1st step, zero clearing shift register R ₀, R ₁..., R ₄

The 2nd step, input bit e _k(0≤k＜u * b), generator polynomial look-up table L ₀, L ₁..., L ₄According to e _k=the 1 or 0 accurate circular matrix F of bit rate output η i=[k/b respectively] (symbol [k/b] expression is not more than the maximum integer of k/b) during piece is capable the 0th, 1 ..., the generator polynomial of 4 row or b position null vector, generator polynomial look-up table L ₀, L ₁..., L ₄Output respectively by b position binary adder A ₀, A ₁..., A ₄With shift register R ₀, R ₁..., R ₄The content addition, b position binary adder A ₀, A ₁..., A ₄And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R ₄

The 3rd step be that step-length increases progressively the value that changes k with 1, repeated the 2nd step u * b time, import up to whole vectorial m to finish, at this moment, shift register R ₀, R ₁..., R _U-1That store is respectively verification section p ₀, p ₁..., p _U-1, they have constituted part verification vector p=(p ₀, p ₁..., p _U-1).

Be not difficult to find out that from above step whole computational process needs u * b clock cycle altogether, identical with existing multiplication scheme based on 5 SRAA-I circuit.

The circular matrix generator polynomial that the existing solution of accurate circular matrix serial multiplication needs the ROM of 3 2048 bits to store the 0th, 1,2 row of 2 kinds of accurate circular matrix F of code check respectively in the CMMB standard, the circular matrix generator polynomial of the 3rd, 4 row of the ROM storage η=0.5 code check F of 2 1280 bits; And the present invention needs the ROM of 3 2304 bits to store circular matrix generator polynomial and the b position null vector of the 0th, 1,2 row of 2 kinds of accurate circular matrix F of code check respectively, and the ROM of 2 1536 bits stores circular matrix generator polynomial and the b position null vector of the 3rd, 4 row of η=0.5 code check F.Although the present invention has used the ROM of 5 * 256 bits more, if realize the generator polynomial look-up table with the block RAM in the FPGA sheet, owing to inevitably waste, the memory of the actual use of the present invention does not increase so.

The existing solution of accurate circular matrix serial multiplication needs 2560 registers, 1280 two inputs and door and 1280 two input XOR gate in the CMMB standard, and the present invention needs 1280 registers, 0 two input and door and 1280 two input XOR gate.Two kinds of multiplication scheme expend the XOR gate of equal number, and the present invention need not and door, have saved 50% register.

As fully visible, for the accurate circular matrix serial multiplication in the CMMB standard multi code Rate of Chinese character QC-LDPC near lower triangular coding, compare with existing solution, the present invention has kept identical speed, remove multiplying, need not and door, used the register of half, saved a large amount of logical resources, have simple in structure, power consumption is little, low cost and other advantages.

The above; it only is one of the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; variation or the replacement that can expect without creative work all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claims were limited.

Claims (4)

1. accurate circular matrix serial multiplier among the CMMB who does not have a multiplying, when adopting the near lower triangular coding method that CMMB standard multi code Rate of Chinese character QC-LDPC sign indicating number is encoded, relate to the multiplying of vectorial m and accurate circular matrix F, matrix F is divided into the capable and u piece row of u piece, is by u * u b * b rank circular matrix F _{I, j}The array that constitutes, f _{I, j}Be circular matrix F _{I, j}Generator polynomial, wherein, b, i, j and u are nonnegative integer, 0≤i＜u, 0≤j＜u, the CMMB standard has adopted the QC-LDPC sign indicating number of 2 kinds of different code check η, η is respectively 0.5,0.75, for these 2 kinds different code check QC-LDPC sign indicating numbers, b=256 is arranged all, 2 kinds of different code check corresponding parameters u are respectively 5,3, vectorial m=(e ₀, e ₁..., e _{U * b-1}), be one section with the b bit, part verification vector p is divided into the u section, i.e. p=(p ₀, p ₁..., p _U-1), it is characterized in that described multiplier comprises with lower member:

Generator polynomial look-up table L ₀, L ₁..., L ₄, among the accurate circular matrix F of all code checks that prestore respectively the 0th, 1 ..., the circular matrix generator polynomial of 4 row and b position null vector;

B position binary adder A ₀, A ₁..., A ₄, respectively to generator polynomial look-up table L ₀, L ₁..., L ₄Output and shift register R ₀, R ₁..., R ₄Content carry out mould 2 and add;

Shift register R ₀, R ₁..., R ₄, store b position binary adder A respectively ₀, A ₁..., A ₄And be recycled the result that moves to left after 1 and final verification section p ₀, p ₁..., p ₄

2. accurate circular matrix serial multiplier among a kind of CMMB that does not have a multiplying according to claim 1 is characterized in that described generator polynomial look-up table L ₀～L ₂Store all generator polynomials and b position null vector in the 0th～2 row of two kinds of code check F respectively, for arbitrary row, store the 0th, 1 successively ..., the generator polynomial of the capable correspondence of u-1 piece is stored 1 b position null vector at last.

3. accurate circular matrix serial multiplier among a kind of CMMB that does not have a multiplying according to claim 1 is characterized in that described generator polynomial look-up table L ₃, L ₄Store all generator polynomials and b position null vector in the 3rd, 4 row of η=0.5 code check F respectively, for arbitrary row, store the 0th, 1 successively ..., the generator polynomial of the capable correspondence of u-1 piece is stored 1 b position null vector at last.

4. accurate circular matrix serial multiplication method among the CMMB who does not have a multiplying, when adopting the near lower triangular coding method that CMMB standard multi code Rate of Chinese character QC-LDPC sign indicating number is encoded, relate to the multiplying of vectorial m and accurate circular matrix F, matrix F is divided into the capable and u piece row of u piece, is by u * u b * b rank circular matrix F _{I, j}The array that constitutes, f _{I, j}Be circular matrix F _{I, j}Generator polynomial, wherein, b, i, j and u are nonnegative integer, 0≤i＜u, 0≤j＜u, the CMMB standard has adopted the QC-LDPC sign indicating number of 2 kinds of different code check η, η is respectively 0.5,0.75, for these 2 kinds different code check QC-LDPC sign indicating numbers, b=256 is arranged all, 2 kinds of different code check corresponding parameters u are respectively 5,3, vectorial m=(e ₀, e ₁..., e _{U * b-1}), be one section with the b bit, part verification vector p is divided into the u section, i.e. p=(p ₀, p ₁..., p _U-1), it is characterized in that described multiplication method may further comprise the steps:

The 1st step, zero clearing shift register R ₀, R ₁..., R ₄

The 2nd step, input bit e _k, generator polynomial look-up table L ₀, L ₁..., L ₄According to e _k=the 1 or 0 accurate circular matrix F of bit rate output η i=[k/b respectively] during piece is capable the 0th, 1 ..., the generator polynomial of 4 row or b position null vector, generator polynomial look-up table L ₀, L ₁..., L ₄Output respectively by b position binary adder A ₀, A ₁..., A ₄With shift register R ₀, R ₁..., R ₄The content addition, b position binary adder A ₀, A ₁..., A ₄And be recycled the result who moves to left after 1 and deposit shift register R respectively in ₀, R ₁..., R ₄, wherein, 0≤k＜u * b, symbol [k/b] expression is not more than the maximum integer of k/b;

The 3rd step be that step-length increases progressively the value that changes k with 1, repeated the 2nd step u * b time, import up to whole vectorial m to finish, at this moment, shift register R ₀, R ₁..., R _U-1That store is respectively verification section p ₀, p ₁..., p _U-1, they have constituted part verification vector p=(p ₀, p ₁..., p _U-1).

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