CN102882533A - Low density parity check (LDPC) serial encoder in digital terrestrial multimedia broadcasting (DTMB) and based on lookup table and coding method - Google Patents
Low density parity check (LDPC) serial encoder in digital terrestrial multimedia broadcasting (DTMB) and based on lookup table and coding method Download PDFInfo
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Abstract
The invention relates to a scheme for solving a problem of serial coding of quality control-low density parity check (QC-LDPC) in different code rates in a digital terrestrial multimedia broadcasting (DTMB) system. An LDPC serial encoder is characterized in that a serial encoder of QC-LDPC codes of the system is mainly composed of four components including a register, an indexing encoder, a lookup table and a b-bit dual-input exclusive-or gate. The QC-LDPC serial encoder can be compatible to multiple code rates, can effectively reduce resource demands on condition of keeping coding rate to be unchanged, and has advantages of being simple in control, less in resource consumption, small in consumption, low in cost and the like.
Description
Technical field
The present invention relates to the Digital Terrestrial Television Broadcast field, particularly the serial implementation method of QC-LDPC code coder in a kind of DTMB system.
Background technology
Because the various distortions that exist in transmission channel and noise can produce transmitted signal and disturb, the situation that digital signal produces error code can appear in receiving terminal inevitably.In order to reduce the error rate, need to adopt channel coding technology.
Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with its excellent properties that approaches the Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.At present, the QC-LDPC code has been widely used in IEEE802.11n, the standards such as Digital Terrestrial Television Broadcast DTMB of 802.16e and China.
The SRAA method is to utilize generator matrix G to encode.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, j(1≤i≤a, the array that 1≤j≤t) consists of, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with the verification vector is high-density matrix.Serial SRAA method is finished first encoding needs ab+t clock cycle, needs (c+t) b register, cb two input and door and cb two input XOR gate.In addition, also need the first trip of acb bit ROM storage circular matrix.
The DTMB standard has adopted the QC-LDPC code of 3 kinds of different code checks.For these 3 kinds of QC-LDPC codes, t=59 and b=127 are arranged all.Fig. 1 has provided parameter a and the c under the different code check η.
The existing solution of QC-LDPC slow coding is to adopt serial SRAA method in the DTMB standard, and 3 kinds of required scramble times of code check are respectively 3107,4631 and 6155 clock cycle.Logical resource needs 11938 registers, 4445 two inputs and door and 4445 two input XOR gate, and this is that parameter by code check η=0.4 correspondence determines.In addition, 3 kinds of code checks need 278,892 bit ROM to store the first trip of circular matrix altogether.When adopting hardware to realize, need more memory and register, will certainly cause equipment cost high, power consumption is large.
Summary of the invention
The large shortcoming of resources requirement that exists in the existing implementation for the multi code Rate of Chinese character QC-LDPC of DTMB system slow coding the invention provides a kind of serial encoding method based on look-up table, can keep reducing resource requirement under the constant prerequisite of coding rate.
As shown in Figure 2, the serial encoder based on multi code Rate of Chinese character QC-LDPC code in the DTMB standard of look-up table mainly is comprised of 4 parts: register, index encoder, look-up table and b position two input XOR gate.Whole cataloged procedure divided for 4 steps finished: the 1st step, zero clearing register R
1～R
cThe 2nd step, input information bits e
k(0≤k＜ab), register R
C+1～R
tSerial moves to left 1 time, and buffer information vector s is the appropriate code check η of index encoder configuration, and piece line number control end input ρ=[k/b]+1(symbol [k/b] expression is not more than the maximum integer of k/b), look-up table is selected output according to index τ, b position two input XOR gate A
l(1≤l≤c) is with l b position output and the register R of look-up table
lThe results added that the serial ring shift left is 1 time, and deposit back register R
lThe 3rd step take 1 for step-length increases progressively the value that changes k, repeated the 2nd step ab time, until that whole information vector s inputs is complete; The 4th step, parallel output code word v=(p, s).
The compatible multi code Rate of Chinese character of QC-LDPC serial encoder provided by the invention can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thereby reach the purpose that reduces hardware cost and power consumption.
Can be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 has provided parameter a and the c under the different code check η;
Fig. 2 is the QC-LDPC code serial encoder overall structure of compatible 3 kinds of code checks in the DTMB standard;
Fig. 3 has provided the relation between the piece line number ρ of the output τ of index encoder and information bit, code check η and generator matrix G;
Fig. 4 has compared traditional serial SRAA method and resource consumption of the present invention.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
The QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H all are the arrays that is made of circular matrix, has segmentation circulation characteristics, so be called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of one of lastrow (first trip is footline) ring shift right; From the angle of row, each row of circular matrix all are that previous column (first is terminal column) circulation moves down one result.The set that the row vector of circular matrix consists of is identical with the set of column vector formation, therefore, circular matrix fully can by it first trip or first characterize.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, j(1≤i≤a, the array that 1≤j≤t) consists of:
G(or H) the capable and b of continuous b row be called as respectively the capable and piece row of piece.
For the DTMB standard, the corresponding code word v=(p, s) of generator matrix G, that the front c piece row of G are corresponding is verification vector p, that rear a piece row are corresponding is information vector s=(e
0, e
1..., e
Ab-1).Take the b bit as one section, verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c); Information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a).The DTMB standard has adopted the QC-LDPC code of 3 kinds of different code checks, and t=59 and b=127 are all arranged, and Fig. 1 has provided parameter a and the c under the different code check η.
By the characteristics of formula (1) and circular matrix, Fig. 2 has provided the serial encoder that is applicable to 3 kinds of code check QC-LDPC codes in the DTMB standard, and it mainly is comprised of register, index encoder, look-up table and b position four kinds of functional modules of two input XOR gate.Register R
1～R
cBe used for calculating and storage verification vector p=(p
1, p
2..., p
c), register R
C+1～R
tBe used for cache information vector s=(s
1, s
2..., s
a).The index encoder forms the index τ of look-up table, with the use of reduced look-up-table.B position two input XOR gate A
1～A
cThe 1st ~ c b position output valve of look-up table is added to respectively register R
1～R
cIn.
The output τ of index encoder depends on three inputs: and the piece line number ρ of information bit, code check η and generator matrix G (1≤ρ≤a).If the information bit of current input is 0, τ=0 so; Otherwise, calculate τ according to code check η and piece line number ρ.When η=0.4, τ=ρ; When η=0.6, τ=24+ ρ; When η=0.8, τ=60+ ρ.Code check η has 3 kinds, so can represent with 2 bits; The maximum of piece line number ρ is 48, so can represent with 6 bits; The maximum of τ is 108, so can represent with 7 bits.Fig. 3 has provided the output τ of index encoder and the relation between three controlled quentity controlled variables.
Look-up table is exported according to index τ.If τ=0, look-up table output complete zero so; If 1≤τ≤24, so first trip of all circular matrixes in capable, the 1st ~ c piece row of the generator matrix τ piece of look-up table output η=0.4; If 25≤τ≤60, so first trip of all circular matrixes in generator matrix τ-24 row of look-up table output η=0.6, the 1st ~ c piece row; Otherwise, the first trip of all circular matrixes in generator matrix τ-60 row of look-up table output η=0.8, the 1st ~ c piece row.
The invention provides a kind of serial encoding method of variable bit rate QC-LDPC code, in conjunction with the serial encoder (as shown in Figure 2) of multi code Rate of Chinese character QC-LDPC code in the DTMB standard, its coding step is described below:
The 1st step, zero clearing register R
1～R
c
The 2nd step, input information bits e
k(0≤k＜ab), register R
C+1～R
tSerial moves to left 1 time, buffer information vector s; Be the appropriate code check η of index encoder configuration, piece line number control end input ρ=[k/b]+1(symbol [k/b] expression is not more than the maximum integer of k/b); Look-up table is selected output according to index τ, b position two input XOR gate A
l(1≤l≤c) is with l b position output and the register R of look-up table
lThe results added that the serial ring shift left is 1 time, and deposit back register R
l
The 3rd step take 1 for step-length increases progressively the value that changes k, repeated the 2nd step ab time, until that whole information vector s inputs is complete.At this moment, register R
1～R
cThat store is verification vector p=(p
1, p
2..., p
c), register R
C+1～R
tThat store is information vector s=(s
1, s
2..., s
a).
The 4th step, parallel output code word v=(p, s).
Be not difficult to find out that from above step whole cataloged procedure needs ab+t clock cycle altogether, this and traditional serial SRAA method are identical.
Fig. 4 has compared traditional serial SRAA method and resource consumption of the present invention.Notice that the unit of substantially searching with look-up table is considered as one two input and door here.Can know from Fig. 4 and to see, the XOR gate that the present invention uses and identical with door quantity and serial SRAA method, advantage of the present invention is to need not memory, has used less register, the amount of expending is 63% of serial SRAA method.As fully visible, compare with traditional serial SRAA method, the present invention has kept coding rate, has that control is simple, resource consumption is few, power consumption is little, low cost and other advantages.
Above-described embodiment is more preferably embodiment of the present invention, and the common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacement all should be included in protection scope of the present invention.
Claims (4)
1. serial encoder that is suitable for 3 kinds of different code check QC-LDPC codes that the DTMB standard adopts, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, jThe array that consists of, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, 3 kinds of different code check η are respectively 0.4,0.6,0.8, for these 3 kinds different code check QC-LDPC codes, t=59 and b=127 are arranged all, 3 kinds of parameter a corresponding to different code checks are respectively 24,36,48,3 kinds of parameter c corresponding to different code checks are respectively 35,23,11, the corresponding code word v=(p, s) of generator matrix G, that the front c piece row of G are corresponding is verification vector p, and that rear a piece row are corresponding is information vector s=(e
0, e
1..., e
Ab-1), take the b bit as one section, verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c), information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), it is characterized in that described encoder comprises following parts:
Register R
1～R
t, register R
1～R
cBe used for calculating and storage verification vector p=(p
1, p
2..., p
c), register R
C+1～R
tBe used for cache information vector s=(s
1, s
2..., s
a);
The index encoder, the index τ of formation look-up table, with the use of reduced look-up-table, wherein, 0≤τ≤108;
Look-up table, according to index τ export that the ρ piece of a certain code check QC-LDPC code generator matrix is capable, the first trip of all circular matrixes in the 1st ~ c piece row, wherein, 1≤ρ≤a;
B position two input XOR gate A
1～A
c, the 1st ~ c b position output valve of look-up table is added to respectively register R
1～R
cIn.
2. serial encoder as claimed in claim 1 is characterized in that, the output τ of described index encoder depends on three inputs of piece line number ρ of information bit, code check η and generator matrix G: if the information bit of current input is 0, and τ=0 so; Otherwise, calculate τ according to code check η and piece line number ρ, when η=0.4,0.6 and 0.8 the time, τ equals respectively ρ, 24+ ρ and 60+ ρ.
3. serial encoder as claimed in claim 1 is characterized in that, described look-up table is exported according to index τ: if τ=0, look-up table output complete zero so; If 1≤τ≤24, so first trip of all circular matrixes in capable, the 1st ~ c piece row of the generator matrix τ piece of look-up table output η=0.4; If 25≤τ≤60, so first trip of all circular matrixes in generator matrix τ-24 row of look-up table output η=0.6, the 1st ~ c piece row; Otherwise, the first trip of all circular matrixes in generator matrix τ-60 row of look-up table output η=0.8, the 1st ~ c piece row.
4. serial encoding method that is suitable for 3 kinds of different code check QC-LDPC codes that the DTMB standard adopts, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, jThe array that consists of, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, 3 kinds of different code check η are respectively 0.4,0.6,0.8, for these 3 kinds different code check QC-LDPC codes, t=59 and b=127 are arranged all, 3 kinds of parameter a corresponding to different code checks are respectively 24,36,48,3 kinds of parameter c corresponding to different code checks are respectively 35,23,11, the corresponding code word v=(p, s) of generator matrix G, that the front c piece row of G are corresponding is verification vector p, and that rear a piece row are corresponding is information vector s=(e
0, e
1..., e
Ab-1), take the b bit as one section, verification vector p is divided into the c section, i.e. p=(p
1, p
2..., p
c), information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), it is characterized in that described coding method may further comprise the steps:
The 1st step, zero clearing register R
1～R
c
The 2nd step, input information bits e
k, register R
C+1～R
tSerial moves to left 1 time, and buffer information vector s is the appropriate code check η of index encoder configuration, piece line number control end input ρ=[k/b]+1, and look-up table is selected output according to index τ, b position two input XOR gate A
lL b position output and register R with look-up table
lThe results added that the serial ring shift left is 1 time, and deposit back register R
l, wherein, 0≤k＜ab, 1≤l≤c, symbol [k/b] expression is not more than the maximum integer of k/b;
The 3rd step take 1 for step-length increases progressively the value that changes k, repeated the 2nd step ab time, until that whole information vector s inputs is complete, at this moment, register R
1～R
cThat store is verification vector p=(p
1, p
2..., p
c), register R
C+1～R
tThat store is information vector s=(s
1, s
2..., s
a);
The 4th step, parallel output code word v=(p, s).
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| CN103268211A (en) * | 2013-04-19 | 2013-08-28 | 荣成市鼎通电子信息科技有限公司 | Shared storage mechanism-based quasi-cyclic matrix serial multiplier for China mobile multimedia broadcasting (CMMB) |
| CN103269226B (en) * | 2013-04-19 | 2016-02-10 | 荣成市鼎通电子信息科技有限公司 | Share quasi-cyclic LDPC serial encoder in the near-earth communication of memory mechanism |
| CN103236857B (en) * | 2013-04-19 | 2016-03-16 | 荣成市鼎通电子信息科技有限公司 | Without the need to the quasi-cyclic matrix high-speed gear of memory |
| CN103269225B (en) * | 2013-04-19 | 2016-03-16 | 荣成市鼎通电子信息科技有限公司 | Share quasi-cyclic LDPC serial encoder in the deep space communication of memory mechanism |
| CN103236849B (en) * | 2013-04-19 | 2016-03-16 | 荣成市鼎通电子信息科技有限公司 | Based on quasi cyclic matrix serial multiplier in the DTMB of shared memory mechanism |
| CN103269228B (en) * | 2013-04-19 | 2016-04-20 | 荣成市鼎通电子信息科技有限公司 | Share quasi-cyclic LDPC serial encoder in the CMMB of memory mechanism |
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