CN102891687B - Summation array-based QC-LDPC (Quasi-Low-Density Parity-Check) parallel encoder and encoding method - Google Patents

Abstract

The invention relates to a scheme of solving parallel encoding of QC-LDPC (Quasi-Low-Density Parity-Check) codes, in particular to a summation array-based QC-LDPC parallel encoder and an encoding method. The QC-LDPC parallel encoder mainly comprises a register, a summation array, a selector and a b-bit two-input exclusive-OR gate. The QC-LDPC parallel encoder provided by the invention has the capability of effectively reducing resource requirements under the condition of keeping the encoding speed unchanged and has the advantages of simpleness in control, low resource consumption, low power consumption, low cost and the like.

Description

Based on QC-LDPC parallel encoder and the coding method of sum array

Technical field

The present invention relates to the communications field, particularly a kind of Parallel Implementation method of QC-LDPC code coder in communication system.

Background technology

Because the various distortion that exists in transmission channel and noise can produce interference to transmission signal, receiving terminal inevitably digital signal produces the situation of error code.In order to reduce the error rate, need to adopt channel coding technology.

Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with the excellent properties that it approaches Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.

SRAA method utilizes generator matrix G to encode.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array that (1≤i≤a, 1≤j≤t) is formed, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with verification vector is high-density matrix.The SRAA method that walks abreast completes first encoding needs b+t clock cycle, needs (ac+t) b register, acb two inputs to input XOR gate with door and acb individual two.When adopting hardware implementing high spped coding, so many resource requirement means that power consumption is large, cost is high.

Summary of the invention

The large shortcoming of resources requirement existed in existing implementation for QC-LDPC code high spped coding, the invention provides a kind of parallel encoding method based on Summation Matrix, can keep, under the prerequisite that coding rate is constant, reducing resource requirement.

As shown in Figure 1, the parallel encoder of QC-LDPC code forms primarily of 4 kinds of functional modules: register, sum array, selector and b position two input XOR gate.Whole cataloged procedure divides 4 steps to complete: the 1st step, and input information vector s, is saved to register R ₁~ R _a, reset register R _a+1~ R _t; 2nd step, register R ₁~ R _arespective serial loop moves to left 1 time, selector M ₁~ M _cfrom the output of sum array, select b respectively, jointly form vector (s _{1, k}, s _{2, k}..., s _a,k) product of (1≤k≤b) and block first trip matrix F, b position two inputs XOR gate A _l(1≤l≤c) is by the l section b bit of product and register R _a+1serial loop moves to left the results added of 1 time, and deposits back register R _a+1; 3rd step, with 1 for step-length increases progressively the value changing k, repeats the 2nd step b time; 4th step, parallel output code word v=(s, p).

QC-LDPC parallel encoder provided by the invention, can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thus reach the object reducing hardware cost and power consumption.

Be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.

Accompanying drawing explanation

Fig. 1 is the parallel encoder overall structure of QC-LDPC code;

Fig. 2 is the formation schematic diagram of sum array;

Fig. 3 compares traditional parallel SRAA method and resource consumption of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as a limitation of the invention.

QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H are all the arrays be made up of circular matrix, have stages cycle feature, therefore are called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of lastrow (first trip is footline) ring shift right one; From the angle of row, each row of circular matrix are all the results that previous column (first is terminal column) circulation moves down.The set that the row vector of circular matrix is formed is identical with the set that column vector is formed, and therefore, circular matrix can be characterized by its first trip or first completely.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array that (1≤i≤a, 1≤j≤t) is formed:

G(or H) continuous b capable and b row be called as the capable and block row of block respectively.Suppose g _i,j(1≤i≤a, a+1≤j≤t) is circular matrix G _i,jfirst trip, so can define a × bc rank block first trip matrix F in the following manner:

F is made up of the first trip of all circular matrixes during c block after generator matrix G arranges, and can be considered to be made up of bc a dimensional vector.

The corresponding code word v=(s, p) of generator matrix G, that the front a block row of G are corresponding is information vector s, and that rear c block row are corresponding is the vectorial p of verification.Be one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a); Verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c).For i-th (1≤i≤a) segment information vector s _i, have s _i=(s _{i, 1}, s _{i, 2}..., s _i,b).

By the feature of formula (1), (2) and circular matrix, Fig. 1 gives the parallel encoder of QC-LDPC code, and it inputs XOR gate four kinds of functional modules compositions primarily of register, sum array, selector and b position two.

Register R ₁~ R _afor cache information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c).

Sum array is to a position information bit s of parallel input _{1, k}, s _{2, k}..., s _a,k(1≤k≤b) sues for peace, and specifically, is therefrom choose the individual different element of m(1≤m≤a) to carry out mould 2 and add.From permutation and combination knowledge, exhaustively obtain 2 ^a-1 different summation expression formula.2 ^a-1 summation expression formula can with 2 ^a-1 multi input XOR gate is realized.The input number range of multi input XOR gate is 1 ~ a, and when only having an input, single input XOR gate is actually direct-connected line.To sum up, sum array has a input and 2 ^a-1 output, its inside is by 2 ^a-1 multi input XOR gate composition, as shown in Figure 2.

Selector M ₁~ M _con the basis of sum array operation result, complete vector (s _{1, k}, s _{2, k}..., s _a,k) parallel multiplication of (1≤k≤b) and block first trip matrix F.Selector M _l(1≤l≤c) is from 2 of sum array ^ab is selected, to form vector (s in-1 output _{1, k}, s _{2, k}..., s _a,k) with the l section b bit of block first trip matrix F product, selection mode depends on bc the column vector of F completely.

B position two inputs XOR gate A _l(1≤l≤c) is by vector (s _{1, k}, s _{2, k}..., s _a,k) the l section b bit of (1≤k≤b) and block first trip matrix F product is added to register R _a+1in.

The invention provides a kind of parallel encoding method of QC-LDPC code, in conjunction with the parallel encoder (as shown in Figure 1) of QC-LDPC code, its coding step is described below:

1st step, input information vector s, is saved to register R ₁~ R _a, reset register R _a+1~ R _t;

2nd step, register R ₁~ R _arespective serial loop moves to left 1 time, selector M ₁~ M _cfrom the output of sum array, select b respectively, jointly form vector (s _{1, k}, s _{2, k}..., s _a,k) product of (1≤k≤b) and block first trip matrix F, b position two inputs XOR gate A _l(1≤l≤c) is by the l section b bit of product and register R _a+1serial loop moves to left the results added of 1 time, and deposits back register R _a+l;

3rd step, with 1 for step-length increases progressively the value changing k, repeats the 2nd step b time, after completing, and register R ₁~ R _athat store is information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tthat store is the vectorial p=(p of verification ₁, p ₂..., p _c);

4th step, parallel output code word v=(s, p).

Be not difficult to find out from above step, whole cataloged procedure needs b+t clock cycle altogether, and this is identical with traditional parallel SRAA method.

Fig. 3 compares traditional parallel SRAA method and resource consumption of the present invention.Can know from Fig. 3 and see, the present invention without the need to door, employ less register.As fully visible, compared with traditional parallel SRAA method, the present invention maintains coding rate, have control simple, resource consumption is few, power consumption is little, low cost and other advantages.

Above-described embodiment, just the present invention's more preferably embodiment, the usual change that those skilled in the art carries out within the scope of technical solution of the present invention and replacement all should be included in protection scope of the present invention.

Claims (5)

1. a parallel encoder for QC-LDPC code, the generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t, b are positive integers, c=t-a, the corresponding code word v=(s of 1≤i≤a, 1≤j≤t, generator matrix G, p), that the front a block row of G are corresponding is information vector s, and that rear c block row are corresponding is the vectorial p of verification, is one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), the i-th segment information vector s _i=(s _{i, 1}, s _{i, 2}..., s _i,b), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described encoder comprises following parts:

Register R ₁~ R _t, register R ₁~ R _afor cache information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c);

Sum array, to parallel input a position information bit s _{1, k}, s _{2, k}..., s _a,kcarry out combination summation, wherein, 1≤k≤b;

Selector M ₁~ M _c, on the basis of sum array operation result, complete vector (s _{1, k}, s _{2, k}..., s _a,k) with the parallel multiplication of block first trip matrix F;

B position two inputs XOR gate A ₁~ A _c, A _lby vector (s _{1, k}, s _{2, k}..., s _a,k) be added to register R with the l section b bit of block first trip matrix F product _a+lin, wherein, 1≤l≤c.

2. parallel encoder as claimed in claim 1, is characterized in that, described piece of first trip matrix F is made up of the first trip of all circular matrixes in c block row before generator matrix G.

3. parallel encoder as claimed in claim 1, it is characterized in that, described sum array has a input and 2 ^a-1 output, sum array is to a position information bit s of parallel input _{1, k}, s _{2, k}..., s _a,kcarry out combination summation, block first trip matrix F has 2 ^a-1 different non-zero column vector, they and vector (s _{1, k}, s _{2, k}..., s _a,k) inner product correspondence 2 ^a-1 summation expression formula, these summation expression formulas are with 2 ^a-1 multi input XOR gate is realized.

4. parallel encoder as claimed in claim 1, is characterized in that, described selector M _lfrom 2 of sum array ^ab is selected, to form vector (s in-1 output _{1, k}, s _{2, k}..., s _a,k) with the l section b bit of block first trip matrix F product, selection mode depends on b × c the column vector of F completely.

5. a parallel encoding method for QC-LDPC code, the generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t, b are positive integers, c=t-a, the corresponding code word v=(s of 1≤i≤a, 1≤j≤t, generator matrix G, p), that the front a block row of G are corresponding is information vector s, and that rear c block row are corresponding is the vectorial p of verification, is one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), the i-th segment information vector s _i=(s _{i, 1}, s _{i, 2}..., s _i,b), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described coding method comprises the following steps:

1st step, input information vector s, is saved to register R ₁~ R _a, reset register R _a+1~ R _t;

2nd step, register R ₁~ R _arespective serial loop moves to left 1 time, selector M ₁~ M _cfrom the output of sum array, select b respectively, jointly form vector (s _{1, k}, s _{2, k}..., s _a,k) with the product of block first trip matrix F, b position two inputs XOR gate A _lby the l section b bit of product and register R _a+lserial loop moves to left the results added of 1 time, and deposits back register R _a+l, wherein, 0≤k<b, 1≤l≤c;

3rd step, with 1 for step-length increases progressively the value changing k, repeats the 2nd step b time, after completing, and register R ₁~ R _athat store is information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tthat store is the vectorial p=(p of verification ₁, p ₂..., p _c);

4th step, parallel output code word v=(s, p).