CN102932010B - The highly-parallel encoder of QC-LDPC code and coding method - Google Patents

Abstract

The present invention relates to a kind of scheme solving QC-LDPC code highly-parallel coding, it is characterized in that, the highly-parallel encoder of the QC-LDPC code of described system primarily of register, look-up table, bc position two inputs XOR gate and b position two inputs XOR gate four part composition.The compatible multi code Rate of Chinese character of QC-LDPC highly-parallel encoder provided by the invention, the look-up table function in fpga logic resource can be made full use of, keeping effectively reducing resource requirement under the constant condition of coding rate, have control simple, resource consumption is few, power consumption is little, low cost and other advantages.

Description

The highly-parallel encoder of QC-LDPC code and coding method

Technical field

The present invention relates to the communications field, particularly the highly-parallel implementation method of QC-LDPC code coder in a kind of communication system.

Background technology

Because the various distortion that exists in transmission channel and noise can produce interference to transmission signal, receiving terminal inevitably digital signal produces the situation of error code.In order to reduce the error rate, need to adopt channel coding technology.

Low-density checksum (Low-DensityParity-Check, LDPC) code becomes the study hotspot of field of channel coding with the excellent properties that it approaches Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.

SRAA method utilizes generator matrix G to encode.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array that (1≤i≤a, 1≤j≤t) is formed, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with verification vector is high-density matrix.Suppose that b is not prime number, can b=ux be broken down into.Au road highly-parallel SRAA method completes first encoding needs x+t clock cycle, needs (auc+t) b register, aucb two inputs to input XOR gate with door and aucb individual two.When adopting FPGA to realize ultrahigh speed coding, so many resource requirement means that power consumption is large, cost is high.

Summary of the invention

The large shortcoming of resources requirement existed in existing implementation for QC-LDPC code ultrahigh speed coding, the invention provides a kind of highly-parallel coding method based on look-up table, make full use of the look-up table function in fpga logic resource, can keep, under the prerequisite that coding rate is constant, effectively reducing resource requirement.

As shown in Figure 1, the highly-parallel encoder of QC-LDPC code forms primarily of 4 parts: register, look-up table, bc position two input XOR gate and b position two inputs XOR gate.Whole cataloged procedure divides 4 steps to complete: the 1st step, and input information vector s, is saved to register R ₁~ R _a, reset register R _a+1~ R _t; 2nd step, register R ₁~ R _aserial moves to left u position, look-up table L ₁~ L _ainput vector h respectively ₁~ h _awith output vector v ₁~ v _a, bc position two inputs XOR gate B ₁~ B _a-1to vector v ₁~ v _asummation, obtains vector v _a+1, b position two inputs XOR gate A _l(1≤l≤c) is by vector v _a+1l section b bit and register R _a+lserial loop moves to left the results added of u position, and deposits back register R _a+l; 3rd step, repeats the 2nd step x time; 4th step, parallel output code word (s, p).

The compatible multi code Rate of Chinese character of QC-LDPC highly-parallel encoder provided by the invention, can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thus reach the object reducing hardware cost and power consumption.

Be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.

Accompanying drawing explanation

Fig. 1 is the highly-parallel encoder overall structure of QC-LDPC code;

Fig. 2 compares traditional au road highly-parallel SRAA method and resource consumption of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as a limitation of the invention.

QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H are all the arrays be made up of circular matrix, have stages cycle feature, therefore are called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of lastrow (first trip is footline) ring shift right one; From the angle of row, each row of circular matrix are all the results that previous column (first is terminal column) circulation moves down.The set that the row vector of circular matrix is formed is identical with the set that column vector is formed, and therefore, circular matrix can be characterized by its first trip or first completely.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _{i, j}the array that (1≤i≤a, 1≤j≤t) is formed:

G(or H) continuous b capable and b row be called as the capable and block row of block respectively.Suppose that the exponent number b of circular matrix is not prime number, can be broken down into b=ux, wherein, u and x is all the positive integer of non-1.So, in block capable, the rear c block of generator matrix G m(1≤m≤a) row, the front u of all circular matrixes is capable constitutes u × bc rank matrix, is referred to as sub block rows matrix, is denoted as U _m.U _mcan be considered and to be made up of bc u dimensional vector, all U _mconstitute au × bc rank sub-block matrix U.

The corresponding code word (s, p) of generator matrix G, that the front a block row of G are corresponding is information vector s, and that rear c block row are corresponding is the vectorial p of verification.Be one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a); Verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c).For i-th (1≤i≤a) segment information vector s _i, have s _i=(s _{i, 1}, s _{i, 2}..., s _i,b).

By the feature of formula (1), (2) and circular matrix, Fig. 1 gives the highly-parallel encoder of QC-LDPC code, it primarily of register, look-up table, bc position two inputs XOR gate and b position two inputs XOR gate four kinds of functional modules compositions.

Register R ₁~ R _afor cache information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c).

Look-up table L ₁~ L _aall there is u position to input and the output of bc position, complete different u position information bits and sub block rows matrix U respectively ₁~ U _aproduct.The u position information bit s of parallel input _{m, un+1}, s _{m, un+2}..., s _{m, un+u}(1≤m≤a, 0≤n<x) forms vectorial h _m={ s _{m, un+1}, s _{m, un+2}..., s _{m, un+u}.Look-up table L _minput be h _m, it is h that each road exports _mwith sub block rows matrix U _mthe product of respective column, total output constitutes vector v _m.If the unit of substantially searching of look-up table is considered as one two input and door, need acb two input and doors so altogether.

Bc position two inputs XOR gate B ₁~ B _a-1by vector v ₁~ v _abe added together, obtain vector v _a+1.In fact, v _a+1in each element be vector { h ₁, h ₂..., h _awith the product of sub-block matrix U respective column, v _a+1vector { h ₁, h ₂..., h _awith the product of sub-block matrix U.

B position two inputs XOR gate A _l(1≤l≤c) is by vector v _a+1continuous b bit be added to register R _a+lin.

It is acb that all bc positions two input the two input XOR gate sums that XOR gate and b position two input XOR gate.

The invention provides a kind of QC-LDPC highly-parallel coding method based on look-up table, in conjunction with the highly-parallel encoder (as shown in Figure 1) of QC-LDPC code, its coding step is described below:

1st step, input information vector s, is saved to register R ₁~ R _a, reset register R _a+1~ R _t;

2nd step, register R ₁~ R _aserial moves to left u position, look-up table L ₁~ L _ainput vector h respectively ₁~ h _awith output vector v ₁~ v _a, bc position two inputs XOR gate B ₁~ B _a-1to vector v ₁~ v _asummation, obtains vector v _a+1, b position two inputs XOR gate A _l(1≤l≤c) is by vector v _a+1l section b bit and register R _a+lserial loop moves to left the results added of u position, and deposits back register R _a+l;

3rd step, repeats the 2nd step x time, after completing, and register R ₁~ R _athat store is information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tthat store is the vectorial p=(p of verification ₁, p ₂..., p _c);

4th step, parallel output code word (s, p).

Be not difficult to find out from above step, whole cataloged procedure needs x+t clock cycle altogether, and this is identical with traditional au road highly-parallel SRAA method.

Fig. 2 compares traditional au road highly-parallel SRAA method and resource consumption of the present invention.Note, the unit of substantially searching of look-up table is considered as one two input and door here.Can know from Fig. 2 and see, compared with the highly-parallel SRAA method of au road, present invention uses less register, XOR gate and with door, consumption is t/ (auc+t), 1/u and 1/u of au road highly-parallel SRAA method respectively.

As fully visible, compared with traditional au road highly-parallel SRAA method, the present invention maintains coding rate, can make full use of the look-up table function in fpga logic resource, have control simple, resource consumption is few, power consumption is little, low cost and other advantages.

Above-described embodiment, just the present invention's more preferably embodiment, the usual change that those skilled in the art carries out within the scope of technical solution of the present invention and replacement all should be included in protection scope of the present invention.

Claims (4)

1. a highly-parallel encoder for QC-LDPC code, the generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, b is broken down into b=ux, u and x is all the positive integer of non-1, the corresponding code word (s of generator matrix G, p), that the front a block row of G are corresponding is information vector s, and that rear c block row are corresponding is the vectorial p of verification, is one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), the i-th segment information vector s _i=(s _{i, 1}, s _{i, 2}..., s _i,b), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described encoder comprises following parts:

Register R ₁~ R _t, register R ₁~ R _afor cache information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c);

Look-up table L ₁~ L _a, the vectorial h of parallel input u position information bit formation respectively _m={ s _{m, un+1}, s _{m, un+2}..., s _{m, un+u}, parallel output b × c bit vector v _m, wherein, 1≤m≤a, 0≤n<x;

B × c position two inputs XOR gate B ₁~ B _a-1, by vector v ₁~ v _abe added together, obtain vector v _a+1;

B position two inputs XOR gate A ₁~ A _c, A _lby vector v _a+1the continuous b bit of l section be added to register R _a+lin, wherein, 1≤l≤c.

2. highly-parallel encoder as claimed in claim 1, is characterized in that, described look-up table L ₁~ L _acomplete different u position information bits and sub block rows matrix U respectively ₁~ U _aproduct, look-up table L _minput be h _m, it is h that each road exports _mwith sub block rows matrix U _mthe product of respective column, total output constitutes vector v _m.

3. highly-parallel encoder as claimed in claim 1, is characterized in that, described vector v _a+1in each element be vector { h ₁, h ₂..., h _awith the product of sub-block matrix U respective column, v _a+1vector { h ₁, h ₂..., h _awith the product of sub-block matrix U.

4. a highly-parallel coding method for QC-LDPC code, the generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, b is broken down into b=ux, u and x is all the positive integer of non-1, the corresponding code word (s of generator matrix G, p), that the front a block row of G are corresponding is information vector s, and that rear c block row are corresponding is the vectorial p of verification, is one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), the i-th segment information vector s _i=(s _{i, 1}, s _{i, 2}..., s _i,b), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described coding method comprises the following steps:

1st step, input information vector s, is saved to register R ₁~ R _a, reset register R _a+1~ R _t;

2nd step, register R ₁~ R _aserial moves to left u position, look-up table L ₁~ L _ainput vector h respectively ₁~ h _awith output vector v ₁~ v _a, b × c position two inputs XOR gate B ₁~ B _a-1to vector v ₁~ v _asummation, obtains vector v _a+1, b position two inputs XOR gate A _lby vector v _a+1l section b bit and register R _a+lserial loop moves to left the results added of u position, and deposits back register R _a+l, wherein, 1≤l≤c;

3rd step, repeats the 2nd step x time, after completing, and register R ₁~ R _athat store is information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tthat store is the vectorial p=(p of verification ₁, p ₂..., p _c);

4th step, parallel output code word (s, p).