CN104993836A - Lookup table-based QC-LDPC serial encoder in WPAN - Google Patents

Abstract

The invention relates to a scheme of solving serial encoding of QC-LDPC codes of four different code rates in a WPAN system, and is characterized in that a serial encoder of the QC-LDPC codes of the system mainly comprises four parts, i.e., a register, an index encoder, a lookup table and a b-bit two-input XOR gate. The AC-LDPC serial encoder provided by the invention is compatible with multiple code rates, can effectively reduce resource needs under the condition of keeping the encoding speed unchanged, and has the advantages of simple control, small resource consumption, small power consumption, low cost and the like.

Description

Based on QC-LDPC serial encoder in the WPAN of look-up table

Technical field

The present invention relates to wireless personal communications field, particularly a kind of serial implementation method of QC-LDPC code coder in WPAN system.

Background technology

Because the various distortion that exists in transmission channel and noise can produce interference to transmission signal, receiving terminal inevitably digital signal produces the situation of error code.In order to reduce the error rate, need to adopt channel coding technology.

Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with the excellent properties that it approaches Shannon limit.Quasi-cyclic LDPC (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.

SRAA method utilizes generator matrix G to encode.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array that (1≤i≤a, 1≤j≤t) is formed, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with verification vector is high-density matrix.Serial SRAA method completes first encoding needs ab+t clock cycle, needs (t+c) b register, cb two inputs to input XOR gate with door and cb individual two.In addition, acb bit ROM is also needed to store the first trip of circular matrix.

WPAN is the English abbreviation of wireless personal-area network, and English full name is Wireless Personal Area Network.WPAN standard have employed the QC-LDPC code of four kinds of different code checks.For these four kinds of QC-LDPC codes, all there is t=32 and b=21.Fig. 1 gives parameter a under different code check η and c.

In WPAN system, the existing solution of QC-LDPC slow coding adopts serial SRAA method, and the scramble time needed for four kinds of QC-LDPC codes is 368,452,536 and 620 clock cycle respectively.Logical resource needs 1008 registers, 336 two inputs input XOR gate with door and 336 two, and this is determined by the parameter of code check η=1/2 correspondence.In addition, four kinds of QC-LDPC codes need 16800 bit ROM to store the first trip of circular matrix altogether.When adopting hardware implementing, need more memory and register, equipment cost will certainly be caused high, and power consumption is large.

Summary of the invention

The large shortcoming of resources requirement existed in existing implementation for WPAN system multi code Rate of Chinese character QC-LDPC code slow coding, the invention provides a kind of serial encoding method based on look-up table, can keep, under the prerequisite that coding rate is constant, reducing resource requirement.

As shown in Figure 2, in WPAN system, the serial encoder of multiple QC-LDPC code forms primarily of 4 parts: register, index encoder, look-up table and b position two input XOR gate.Whole cataloged procedure divides 4 steps to complete: the 1st step, resets register R _a+1~ R _t, be the code check η that index encoder configuration information vector s is corresponding; 2nd step, input information bits e _k, register R ₁~ R _aserial moves to left and cushions e 1 time _k, to block line number control end input block line number ρ=[k/b]+1 of look-up table, look-up table is selected to export according to index τ, and b position two inputs XOR gate A _lby l b position output of look-up table and register R _a+lserial loop moves to left the results added of 1 time, and deposits back register R _a+l, wherein, 0≤k<a × b, 1≤ρ≤a, 1≤l≤c, symbol [k/b] represents the maximum integer being not more than k/b; 3rd step, with 1 for step-length increases progressively the value changing k, repetition the 2nd step a × b-1 time, until whole information vector s inputs complete, now, register R ₁~ R _athat store is information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tthat store is the vectorial p=(p of verification ₁, p ₂..., p _c); 4th step, parallel output code word v=(s, p).

The compatible multi code Rate of Chinese character of QC-LDPC serial encoder provided by the invention, can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thus reach the object reducing hardware cost and power consumption.

Be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.

Accompanying drawing explanation

Fig. 1 gives parameter a under different code check η and c;

Fig. 2 is the QC-LDPC code serial encoder overall structure of compatible four kinds of code checks in WPAN standard;

Fig. 3 gives the output τ of index encoder and information bit, relation between code check η and the block line number ρ of generator matrix G;

Fig. 4 compares traditional serial SRAA method and resource consumption of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as a limitation of the invention.

QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H are all the arrays be made up of circular matrix, have stages cycle feature, therefore are called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of lastrow (first trip is footline) ring shift right one; From the angle of row, each row of circular matrix are all the results that previous column (first is terminal column) circulation moves down.The set that the row vector of circular matrix is formed is identical with the set that column vector is formed, and therefore, circular matrix can be characterized by its first trip or first completely.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array that (1≤i≤a, 1≤j≤t) is formed:

The continuous b of G (or H) capable and b row are called as the capable and block row of block respectively.

For WPAN system, the corresponding code word v=(s, p) of generator matrix G, that the front a block row of G are corresponding is information vector s=(e ₀, e ₁..., e _ab-1), that rear c block row are corresponding is the vectorial p of verification.Be one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a); Verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c).WPAN standard have employed the QC-LDPC code of four kinds of different code checks, all has t=32 and b=21, and Fig. 1 gives parameter a under different code check η and c.

By the feature of formula (1) and circular matrix, Fig. 2 gives the serial encoder being applicable to four kinds of code check QC-LDPC codes in WPAN system, and it inputs XOR gate four kinds of functional modules compositions primarily of register, index encoder, look-up table and b position two.Register R ₁~ R _afor cache information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c).Index encoder forms the index τ of look-up table, with the use of reduced look-up-table.B position two inputs XOR gate A ₁~ A _c1st ~ the c of look-up table b position output valve is added to register R respectively _a+1~ R _tin.

The output τ of index encoder depends on three inputs: and the block line number ρ of information bit, code check η and generator matrix G (1≤ρ≤a).If the information bit of current input is 0, so τ=0; Otherwise, calculate τ according to code check η and block line number ρ.When η=1/2, τ=ρ; When η=5/8, τ=16+ ρ; When η=3/4, τ=36+ ρ; When η=7/8, τ=60+ ρ.Code check η has four kinds, therefore can represent with 2 bits; The maximum of block line number ρ is 28, therefore can represent with 5 bits; The maximum of τ is 88, therefore can represent with 7 bits.Fig. 3 gives the relation between output τ and three controlled quentity controlled variable of index encoder.

Look-up table exports according to index τ.If τ=0, so look-up table exports complete zero; If 1≤τ≤16, so look-up table export that the generator matrix τ block of η=1/2 is capable, the first trip of all circular matrixes in a+1 ~ t block row; If 17≤τ≤36, so look-up table exports the first trip of all circular matrixes in generator matrix τ-16 pieces of row of η=5/8, a+1 ~ t block row; If 37≤τ≤60, so look-up table exports the first trip of all circular matrixes in generator matrix τ-36 pieces of row of η=3/4, a+1 ~ t block row; Otherwise, the first trip of all circular matrixes during generator matrix τ-60 pieces of row of look-up table output η=7/8, a+1 ~ t block arrange.

The invention provides a kind of serial encoding method of variable bit rate QC-LDPC code, in conjunction with the serial encoder (as shown in Figure 2) of multi code Rate of Chinese character QC-LDPC code in WPAN system, its coding step is described below:

1st step, resets register R _a+1~ R _t, be the code check η that index encoder configuration information vector s is corresponding;

2nd step, input information bits e _k, register R ₁~ R _aserial moves to left and cushions e 1 time _k, to block line number control end input block line number ρ=[k/b]+1 of look-up table, look-up table is selected to export according to index τ, and b position two inputs XOR gate A _lby l b position output of look-up table and register R _a+lserial loop moves to left the results added of 1 time, and deposits back register R _a+l, wherein, 0≤k<a × b, 1≤ρ≤a, 1≤l≤c, symbol [k/b] represents the maximum integer being not more than k/b;

3rd step, with 1 for step-length increases progressively the value changing k, repetition the 2nd step a × b-1 time, until whole information vector s inputs complete, now, register R ₁~ R _athat store is information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tthat store is the vectorial p=(p of verification ₁, p ₂..., p _c);

4th step, parallel output code word v=(s, p).

Be not difficult to find out from above step, whole cataloged procedure needs ab+t clock cycle altogether, and this is identical with traditional serial SRAA method.

Fig. 4 compares traditional serial SRAA method and resource consumption of the present invention.Note, the unit of substantially searching of look-up table is considered as one two input and door here.Can know from Fig. 4 and see, the XOR gate and identical with door quantity and serial SRAA method that the present invention uses, advantage of the present invention is without the need to memory, employs less register, and consumption is 67% of serial SRAA method.As fully visible, compared with traditional serial SRAA method, the present invention maintains coding rate, have control simple, resource consumption is few, power consumption is little, low cost and other advantages.

Above-described embodiment, just the present invention's more preferably embodiment, the usual change that those skilled in the art carries out within the scope of technical solution of the present invention and replacement all should be included in protection scope of the present invention.

Claims (4)

1. one kind is suitable for the serial encoder of four kinds of different code check QC-LDPC codes that WPAN system adopts, WPAN is the English abbreviation of wireless personal-area network, English full name is Wireless Personal Area Network, and the generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, four kinds of different code check η are 1/2,5/8,3/4,7/8 respectively, for these four kinds different code check QC-LDPC codes, all have t=32 and b=21, the parameter a that four kinds of different code checks are corresponding is 16,20,24,28 respectively, the parameter c that four kinds of different code checks are corresponding is 16,12,8,4 respectively, the corresponding code word v=(s, p) of generator matrix G, that the front a block row of G are corresponding is information vector s=(e ₀, e ₁..., e _ab-1), that rear c block row are corresponding is the vectorial p of verification, and be one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described encoder comprises following parts:

Register R ₁~ R _t, register R ₁~ R _afor cache information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c);

Index encoder, forms the index τ of look-up table, with the use of reduced look-up-table, wherein, and 0≤τ≤88;

According to index τ, look-up table, exports that the ρ block of QC-LDPC code generator matrix corresponding to a certain code check is capable, the first trip of all circular matrixes in a+1 ~ t block row, wherein, and 1≤ρ≤a;

B position two inputs XOR gate A ₁~ A _c, the 1st ~ c of look-up table b position output valve is added to register R respectively _a+1~ R _tin.

2. serial encoder as claimed in claim 1, it is characterized in that, the output τ of described index encoder depends on block line number ρ tri-input of information bit, code check η and generator matrix G: if the information bit of current input is 0, so τ=0; Otherwise, calculate τ according to code check η and block line number ρ, when η=1/2,5/8,3/4 and 7/8 time, τ equals ρ, 16+ ρ, 36+ ρ and 60+ ρ respectively.

3. serial encoder as claimed in claim 1, it is characterized in that, described look-up table exports according to index τ: if τ=0, and so look-up table exports complete zero; If 1≤τ≤16, so look-up table export that the generator matrix τ block of η=1/2 is capable, the first trip of all circular matrixes in a+1 ~ t block row; If 17≤τ≤36, so look-up table exports the first trip of all circular matrixes in generator matrix τ-16 pieces of row of η=5/8, a+1 ~ t block row; If 37≤τ≤60, so look-up table exports the first trip of all circular matrixes in generator matrix τ-36 pieces of row of η=3/4, a+1 ~ t block row; Otherwise, the first trip of all circular matrixes during generator matrix τ-60 pieces of row of look-up table output η=7/8, a+1 ~ t block arrange.

4. one kind is suitable for the serial encoding method of four kinds of different code check QC-LDPC codes that WPAN system adopts, WPAN is the English abbreviation of wireless personal-area network, English full name is Wireless Personal Area Network, and the generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t and b are all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, four kinds of different code check η are 1/2,5/8,3/4,7/8 respectively, for these four kinds different code check QC-LDPC codes, all have t=32 and b=21, the parameter a that four kinds of different code checks are corresponding is 16,20,24,28 respectively, the parameter c that four kinds of different code checks are corresponding is 16,12,8,4 respectively, the corresponding code word v=(s, p) of generator matrix G, that the front a block row of G are corresponding is information vector s=(e ₀, e ₁..., e _ab-1), that rear c block row are corresponding is the vectorial p of verification, and be one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described coding method comprises the following steps:

1st step, resets register R _a+1~ R _t, be the code check η that index encoder configuration information vector s is corresponding;

2nd step, input information bits e _k, register R ₁~ R _aserial moves to left and cushions e 1 time _k, to block line number control end input block line number ρ=[k/b]+1 of look-up table, look-up table is selected to export according to index τ, and b position two inputs XOR gate A _lby l b position output of look-up table and register R _a+lserial loop moves to left the results added of 1 time, and deposits back register R _a+l, wherein, 0≤k<a × b, 1≤ρ≤a, 1≤l≤c, symbol [k/b] represents the maximum integer being not more than k/b;

3rd step, with 1 for step-length increases progressively the value changing k, repetition the 2nd step a × b-1 time, until whole information vector s inputs complete, now, register R ₁~ R _athat store is information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tthat store is the vectorial p=(p of verification ₁, p ₂..., p _c);

4th step, parallel output code word v=(s, p).