CN102891687A - Summation array-based QC-LDPC (Quasi-Low-Density Parity-Check) parallel encoder and encoding method - Google Patents

Abstract

The invention relates to a scheme of solving parallel encoding of QC-LDPC (Quasi-Low-Density Parity-Check) codes, in particular to a summation array-based QC-LDPC parallel encoder and an encoding method. The QC-LDPC parallel encoder mainly comprises a register, a summation array, a selector and a b-bit two-input exclusive-OR gate. The QC-LDPC parallel encoder provided by the invention has the capability of effectively reducing resource requirements under the condition of keeping the encoding speed unchanged and has the advantages of simpleness in control, low resource consumption, low power consumption, low cost and the like.

Description

QC-LDPC parallel encoder and coding method based on sum array

Technical field

The present invention relates to the communications field, particularly the Parallel Implementation method of QC-LDPC code coder in a kind of communication system.

Background technology

Because the various distortions that exist in transmission channel and noise can produce transmitted signal and disturb, the situation that digital signal produces error code can appear in receiving terminal inevitably.In order to reduce the error rate, need to adopt channel coding technology.

Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with its excellent properties that approaches the Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.

The SRAA method is to utilize generator matrix G to encode.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G _{I, j}(1≤i≤a, the array that 1≤j≤t) consists of, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with the verification vector is high-density matrix.Parallel SRAA method is finished first encoding needs b+t clock cycle, needs (ac+t) b register, acb two input and door and acb two input XOR gate.When adopting hardware to realize high spped coding, so many resource requirement means that power consumption is large, cost is high.

Summary of the invention

The large shortcoming of resources requirement that exists in the existing implementation for QC-LDPC code high spped coding the invention provides a kind of parallel encoding method based on the summation matrix, can keep reducing resource requirement under the constant prerequisite of coding rate.

As shown in Figure 1, the parallel encoder of QC-LDPC code mainly is comprised of 4 kinds of functional modules: register, sum array, selector and b position two input XOR gate.Whole cataloged procedure divided for 4 steps finished: in the 1st step, input message vector s is saved to register R ₁～R _a, zero clearing register R _A+1～R _tThe 2nd step, register R ₁～R _aThe serial ring shift left is 1 time separately, selector M ₁～M _cFrom the output of sum array, select b respectively, common formation vector (s _{1, k}, s _{2, k}..., s _{A, k}) (product of 1≤k≤b) and piece first trip matrix F, b position two input XOR gate A _l(1≤l≤c) is with l section b bit and the register R of product _A+1The results added that the serial ring shift left is 1 time, and deposit back register R _A+1In the 3rd step, take 1 for step-length increases progressively the value that changes k, repeat the 2nd and go on foot b time; The 4th step, parallel output code word v=(s, p).

QC-LDPC parallel encoder provided by the invention can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thereby reach the purpose that reduces hardware cost and power consumption.

Can be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.

Description of drawings

Fig. 1 is the parallel encoder overall structure of QC-LDPC code;

Fig. 2 is the formation schematic diagram of sum array;

Fig. 3 has compared traditional parallel SRAA method and resource consumption of the present invention.

Embodiment

The invention will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.

The QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H all are the arrays that is made of circular matrix, has segmentation circulation characteristics, so be called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of one of lastrow (first trip is footline) ring shift right; From the angle of row, each row of circular matrix all are that previous column (first is terminal column) circulation moves down one result.The set that the row vector of circular matrix consists of is identical with the set of column vector formation, therefore, circular matrix fully can by it first trip or first characterize.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G _{I, j}(1≤i≤a, the array that 1≤j≤t) consists of:

G(or H) the capable and b of continuous b row be called as respectively the capable and piece row of piece.Suppose g _{I, j}(1≤i≤a, a+1≤j≤t) is circular matrix G _{I, j}First trip, can define in the following manner so a * bc rank piece first trip matrix F:

F is that the first trip by all circular matrixes in the c piece row behind the generator matrix G consists of, and can be considered to be comprised of bc a dimensional vector.

The corresponding code word v=(s, p) of generator matrix G, that the front a piece row of G are corresponding is information vector s, that rear c piece row are corresponding is verification vector p.Take the b bit as one section, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a); Verification vector p is divided into the c section, i.e. p=(p ₁, p ₂..., p _c).For the segment information of the i(1≤i≤a) vector s _i, s is arranged _i=(s _{I, 1}, s _{I, 2}..., s _{I, b}).

By the characteristics of formula (1), (2) and circular matrix, Fig. 1 has provided the parallel encoder of QC-LDPC code, and it mainly is comprised of register, sum array, selector and b position four kinds of functional modules of two input XOR gate.

Register R ₁～R _aBe used for cache information vector s=(s ₁, s ₂..., s _a), register R _A+1～R _tBe used for calculating and storage verification vector p=(p ₁, p ₂..., p _c).

Sum array is to a position information bit s of parallel input _{1, k}, s _{2, k}..., s _{A, k}(1≤k≤b) sue for peace particularly, is therefrom to choose the individual different element of m(1≤m≤a) to carry out mould 2 and add.By permutation and combination knowledge as can be known, exhaustively obtain 2 ^a-1 different summation expression formula.2 ^a-1 summation expression formula can be with 2 ^aThe XOR gate of input more than-1 is realized.The input number scope of many input XOR gate is 1 ~ a, and when only having an input, single input XOR gate is actually direct-connected line.To sum up, sum array has a input and 2 ^a-1 output, its inside is by 2 ^aThe XOR gate of input more than-1 forms, as shown in Figure 2.

Selector M ₁～M _cOn the basis of sum array operation result, finish vector (s _{1, k}, s _{2, k}..., s _{A, k}) (the parallel multiplication of 1≤k≤b) and piece first trip matrix F.Selector M _l(1≤l≤c) from 2 of sum array ^aSelect b in-1 output, to consist of vector (s _{1, k}, s _{2, k}..., s _{A, k}) with the l section b bit of piece first trip matrix F product, selection mode depends on bc the column vector of F fully.

B position two input XOR gate A _l(1≤l≤c) with vector (s _{1, k}, s _{2, k}..., s _{A, k}) (1≤k≤b) the l section b bit with piece first trip matrix F product is added to register R _A+1In.

The invention provides a kind of parallel encoding method of QC-LDPC code, in conjunction with the parallel encoder (as shown in Figure 1) of QC-LDPC code, its coding step is described below:

In the 1st step, input message vector s is saved to register R ₁～R _a, zero clearing register R _A+1～R _t

The 2nd step, register R ₁～R _aThe serial ring shift left is 1 time separately, selector M ₁～M _cFrom the output of sum array, select b respectively, common formation vector (s _{1, k}, s _{2, k}..., s _{A, k}) (product of 1≤k≤b) and piece first trip matrix F, b position two input XOR gate A _l(1≤l≤c) is with l section b bit and the register R of product _A+1The results added that the serial ring shift left is 1 time, and deposit back register R _A+l

The 3rd step take 1 for step-length increases progressively the value that changes k, repeated the 2nd and goes on foot b time, after finishing, and register R ₁～R _aThat store is information vector s=(s ₁, s ₂..., s _a), register R _A+1～R _tThat store is verification vector p=(p ₁, p ₂..., p _c);

The 4th step, parallel output code word v=(s, p).

Be not difficult to find out that from above step whole cataloged procedure needs b+t clock cycle altogether, this and traditional parallel SRAA method are identical.

Fig. 3 has compared traditional parallel SRAA method and resource consumption of the present invention.Can know from Fig. 3 and to see that the present invention need not and door, use less register.As fully visible, compare with traditional parallel SRAA method, the present invention has kept coding rate, has that control is simple, resource consumption is few, power consumption is little, low cost and other advantages.

Above-described embodiment is more preferably embodiment of the present invention, and the common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacement all should be included in protection scope of the present invention.

Claims (5)

1. the parallel encoder of a QC-LDPC code, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G _{I, j}The array that consists of, wherein, a, t, b are positive integers, c=t-a, 1≤i≤a, 1≤j≤t, the corresponding code word v=of generator matrix G (s, p), that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p, take the b bit as one section, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), i segment information vector s _i=(s _{I, 1}, s _{I, 2}..., s _{I, b}), verification vector p is divided into the c section, i.e. p=(p ₁, p ₂..., p _c), it is characterized in that described encoder comprises following parts:

Register R ₁～R _t, register R ₁～R _aBe used for cache information vector s=(s ₁, s ₂..., s _a), register R _A+1～R _tBe used for calculating and storage verification vector p=(p ₁, p ₂..., p _c);

Sum array is to parallel input a position information bit s _{1, k}, s _{2, k}..., s _{A, k}Make up summation, wherein, 1≤k≤b;

Selector M ₁～M _c, on the basis of sum array operation result, finish vector (s _{1, k}, s _{2, k}..., s _{A, k}) with the parallel multiplication of piece first trip matrix F;

B position two input XOR gate A ₁～A _c, A _lWith vector (s _{1, k}, s _{2, k}..., s _{A, k}) be added to register R with the l section b bit of piece first trip matrix F product _A+1In, wherein, 1≤l≤c.

2. parallel encoder as claimed in claim 1 is characterized in that, described first trip matrix F is that the first trip of all circular matrixes consists of in being listed as by c piece before the generator matrix G.

3. parallel encoder as claimed in claim 1 is characterized in that, described sum array has a input and 2 ^a-1 output, sum array is to a position information bit s of parallel input _{1, k}, s _{2, k}..., s _{A, k}Make up summation, piece first trip matrix F has 2 ^a-1 different non-zero column vector, they and vector (s _{1, k}, s _{2, k}..., s _{A, k}) inner product correspondence 2 ^a-1 summation expression formula, these summation expression formulas are with 2 ^aThe XOR gate of input more than-1 is realized.

4. parallel encoder as claimed in claim 1 is characterized in that, described selector M _lFrom 2 of sum array ^aSelect b in-1 output, to consist of vector (s _{1, k}, s _{2, k}..., s _{A, k}) with the l section b bit of piece first trip matrix F product, selection mode depends on bc the column vector of F fully.

5. the parallel encoding method of a QC-LDPC code, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G _{I, j}The array that consists of, wherein, a, t, b are positive integers, c=t-a, 1≤i≤a, 1≤j≤t, the corresponding code word v=of generator matrix G (s, p), that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p, take the b bit as one section, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), i segment information vector s _i=(s _{I, 1}, s _{I, 2}..., s _{I, b}), verification vector p is divided into the c section, i.e. p=(p ₁, p ₂..., p _c), it is characterized in that described coding method may further comprise the steps:

In the 1st step, input message vector s is saved to register R ₁～R _a, zero clearing register R _A+1～R _t

The 2nd step, register R ₁～R _aThe serial ring shift left is 1 time separately, selector M ₁～M _cFrom the output of sum array, select b respectively, common formation vector (s _{1, k}, s _{2, k}..., s _{A, k}) with the product of piece first trip matrix F, b position two input XOR gate A _lL section b bit and register R with product _A+lThe results added that the serial ring shift left is 1 time, and deposit back register R _A+1, wherein, 0≤k＜b, 1≤l≤c;

The 3rd step take 1 for step-length increases progressively the value that changes k, repeated the 2nd and goes on foot b time, after finishing, and register R ₁～R _aThat store is information vector s=(s ₁, s ₂..., s _a), register R _A+1～R _tThat store is verification vector p=(p ₁, p ₂..., p _c);

The 4th step, parallel output code word v=(s, p).

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