CN103023516A - LDPC (low density parity check) coder capable of generating matrix and check matrix jointly and coding method - Google Patents
LDPC (low density parity check) coder capable of generating matrix and check matrix jointly and coding method Download PDFInfo
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Abstract
The invention relates to an LDPC (low density parity check) coder capable of generating matrix and check matrix jointly and a coding method and solves the problem about coding scheme of QC-LDPC (quasic-LDPC) codes in a CCSDS near-field communication system. The LDPC coder is characterized in that the coder of the QC-LDPC codes of the system mainly consists of a controller, a parallel shift register adder accumulator filter and a filter linear feedback shift register, comprehensively generates the matrix and the check matrix and adopts a two-stage assembly line mechanism. The QC-LDPC coder can effectively reduce resource demands on the premise of keeping constant coding speed and has the advantages of low resource consumption, power consumption and cost, and the like.
Description
Technical field
The present invention relates to near-earth space data communication field, particularly the efficient implementation method of QC-LDPC code coder in a kind of CCSDS near-earth communication system.
Background technology
Because the various distortions that exist in transmission channel and noise can produce transmitted signal and disturb, the situation that digital signal produces error code can appear in receiving terminal inevitably.In order to reduce the error rate, need to adopt channel coding technology.
Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with its excellent properties that approaches the Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.
The SRAA method is to utilize generator matrix G to encode.The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, j(1≤i≤a, the array that 1≤j≤t) consists of, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with the verification vector is high-density matrix.Parallel SRAA method is finished first encoding needs b+t clock cycle, needs (ac+t) b register, acb two input and door and acb two input XOR gate.
CCSDS near-earth communication system has been recommended a kind of QC-LDPC code, wherein, and a=14, c=2, t=16, b=511.
The existing solution of QC-LDPC high spped coding is to adopt parallel SRAA method in the CCSDS near-earth communication system, the required scramble time is 527 clock cycle, and logical resource needs 22484 registers, 14308 two inputs and door and 14308 two input XOR gate.When adopting hardware to realize, so many resource requirement means that power consumption is large, cost is high.
Summary of the invention
The large shortcoming of resources requirement that exists in the existing implementation for CCSDS near-earth communication system QC-LDPC code high spped coding, the invention provides a kind of high efficient coding method of uniting generator matrix and check matrix, can keep reducing resource requirement under the constant prerequisite of coding rate.
As shown in Figure 3, the encoder of QC-LDPC code mainly is comprised of 3 parts in the CCSDS near-earth communication system: controller, parallel SRAA Filter and Filltering linear feedback shift register (Linear Feedback Shift Register, LFSR), Integrated using generator matrix and check matrix.Whole cataloged procedure adopts two-stage streamline mechanism, and minute 2 steps finish: in the 1st step, at first order streamline, input message vector s uses parallel SRAA filter calculating section verification vector p
1And p
xAnd vector f; The 2nd step, at second level streamline, utilize the operation result of first order streamline, use filtering LFSR compute vector q, u and part verification vector p
y, and output codons v=(s, p
1, p
x, p
y).
QC-LDPC encoder provided by the invention can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thereby reach the purpose that reduces hardware cost and power consumption.
Can be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 is QC-LDPC code near lower triangular check matrix H in the CCSDS near-earth communication system
ALTStructural representation;
Fig. 2 has provided QC-LDPC code near lower triangular check matrix H in the CCSDS near-earth communication system
ALTDetailed structure;
Fig. 3 is the encoder overall structure of QC-LDPC code in the CCSDS near-earth communication system;
Fig. 4 is the structural representation of parallel SRAA filter;
Fig. 5 is the structural representation of filtering LFSR;
Fig. 6 is the hardware resource consumption of each part of encoder and whole circuit;
Fig. 7 is each coding step and required processing time of whole cataloged procedure;
Fig. 8 has compared traditional parallel SRAA method and coding rate of the present invention and resource consumption.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
The QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H all are the arrays that is made of circular matrix, has segmentation circulation characteristics, so be called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of one of lastrow (first trip is footline) ring shift right; From the angle of row, each row of circular matrix all are that previous column (first is terminal column) circulation moves down one result.The set that the row vector of circular matrix consists of is identical with the set of column vector formation, therefore, circular matrix fully can by it first trip or first characterize.The row of circular matrix is heavy identical with column weight, is denoted as w.If w=0, this circular matrix is full null matrix so.If w=1, this circular matrix is replaceable so, is called permutation matrix, and it can be by obtaining the some positions of unit matrix I ring shift right.The check matrix H of QC-LDPC code is by c * t b * b rank circular matrix H
I, j(1≤i≤c, the following array that 1≤j≤t) consists of:
The generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, j(1≤i≤a, the array that 1≤j≤t) consists of:
G(or H) the capable and b of continuous b row be called as respectively the capable and piece row of piece.
CCSDS near-earth communication system has been recommended a kind of QC-LDPC code, wherein, and a=14, c=2, t=16, b=511.For CCSDS near-earth communication system, the corresponding code word v=(s, p) of check matrix H, that the front a piece row of H are corresponding is information vector s, that rear c piece row are corresponding is verification vector p=(e
1, e
2..., e
Cb).Take the b bit as one section, information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a); Verification vector p is divided into the c section, i.e. p=(p
1, p
2).All circular matrixes in the check matrix H all have w=2, can be considered 2 permutation matrixes (w=1) sum.
Check matrix H is carried out preliminary treatment, it is transformed near lower triangular shape H
ALT, as shown in Figure 1.In Fig. 1, the unit of all submatrixs all is 1 bit, and T is lower triangular matrix.Pretreated process is as follows: with all permutation matrixes in H the 1st, 2 row respectively ring shift rights 472,319, on this basis, with two capable additions of piece.At H
ALTIn, all circular matrixes in front 15 row all have w=4, can be considered 4 permutation matrixes (w=1) sum, and the circular matrix in the last piece row has w=2, can be considered 2 permutation matrixes (w=1) sum.Fig. 2 has provided QC-LDPC code near lower triangular check matrix H in the CCSDS near-earth communication system
ALTDetailed structure, what provide among the figure is the ring shift right figure place of permutation matrix in each piece row.
In Fig. 1, p
x=(e
512, e
513, e
514), p
y=(e
515, e
516..., e
1022), p
2=(p
x, p
y), p=(p
1, p
2), v=(s, p).Make E=[A
TC
T]
T, F=[B
TD
T]
T, L=[I 0]
T, matrix E corresponding informance vector s then, the corresponding a part of verification vector of matrix F p
1, the corresponding another part verification vector of matrix L p
x, the corresponding remainder verification vector of matrix T p
yAbove-mentioned matrix and vector satisfy following relation:
p
y T＝T
-1(Cs
T+Dp
1 T+[p
x T 0]) (3)
Therefore the non-full rank of check matrix H of QC-LDPC code in the CCSDS near-earth communication system, can't only encode with H, can consider that associating generator matrix G and check matrix H encode.Thinking is as follows: use first G calculating section verification vector p
1And p
x, re-use H
ALTCalculating section verification vector p
yBy generator matrix G and formula (3), can obtain the general coding flow process of QC-LDPC code, may further comprise the steps:
(1) uses generator matrix G calculating section verification vector p
1And p
x
(2) compute vector f
T=Cs
T
(3) compute vector q
T=Dp
1 T
(4) compute vector u
T=f
T+ q
T
(5) calculating section verification vector p
y T=T
-1(u
T+ [p
x T0]).
According to above-mentioned coding flow process, Fig. 3 has provided the encoder that is applicable to QC-LDPC code in the CCSDS near-earth communication system, it mainly is comprised of controller, parallel SRAA Filter and Filltering LFSR three functions module, and Integrated using generator matrix and check matrix adopt two-stage streamline mechanism.At first order streamline, parallel SRAA filter is used for calculating section verification vector p
1And p
xAnd vector f.At second level streamline, filtering LFSR is used for compute vector q, u and part verification vector p
y
Fig. 4 is the structural representation of parallel SRAA filter, mainly by register R
1～R
A+3, R
I, jTwo inputs of (1≤i≤a, 1≤j≤2), multidigit and door M
I, j(1≤i≤a, 1≤j≤2), multidigit two input XOR gate A
I, j(1≤i≤a, 1≤j≤2) and 56 input XOR gate A
1Form.Register R
1～R
A+2, R
I, jTwo inputs of (1≤i≤a, 1≤j≤2), multidigit and door M
I, j(1≤i≤a, 1≤j≤2) and multidigit two input XOR gate A
I, j(1≤i≤a, 1≤j≤2) have consisted of improved parallel SRAA, are used for calculating section verification vector p
1And p
xRegister R
1～R
a, R
A+3With 56 input XOR gate A
1Consist of 56 tap filters, be used for compute vector f.A
1The corresponding E of each input in a permutation matrix, these permutation matrix place piece row number equal register R
1～R
aSubscript, its ring shift right figure place adds the 1 tap position that equals register.
Parallel SRAA filter is calculating section verification vector p simultaneously
1And p
xAnd vector f.When initial, register R
1～R
aThat store is information vector s, register R
A+1And R
A+2Be cleared register R
I, 1(1≤i≤a) loads circular matrix G in the generator matrix
I, a+1First trip, register R
I, 2(1≤i≤a) loads circular matrix G in the generator matrix
I, a+2Front 3 bits of first trip.When each clock arrives, register R
1～R
aThe serial ring shift left is 1 time separately, 56 input XOR gate A
1The result of calculation serial is moved to left into register R
A+3, register R
I, 1(1≤i≤a) is serial ring shift right 1 time separately, register R
I, 2(1≤i≤a) separately serial moves to right 1 time and from G
I, a+2The back of first trip moves into 1 new bit, multidigit two inputs and door M
I, jCarry out the multiplying of scalar and vector, M
1, j～M
A, jThe sum of products of (1≤j≤2) and register R
A+jAdd up.Repeat said process, b clock cycle of process finished computing.At this moment, register R
1～R
aThat store still is information vector s, register R
A+1, R
A+2And R
A+3That store is respectively part verification vector p
1, p
xAnd vector f.
Fig. 5 is the structural representation of filtering LFSR, mainly by register R
A+4, R
A+5With XOR gate A
2～A
4Form.Register R
A+4With 4 input XOR gate A
2Consist of 4 tap filters, be used for compute vector q.A
2The corresponding F of each input in a permutation matrix, the ring shift right figure place of this permutation matrix adds the 4 tap positions that equal register.Register R
A+5With XOR gate A
3, A
4Consist of LFSR, be used for compute vector u and part verification vector p
yXOR gate A
3Output vector u, XOR gate A
4Output verification vector p
y
Filtering LFSR is compute vector q, u and part verification vector p simultaneously
yWhen initial, register R
A+4That store is part verification vector p
1, register R
A+5Front b-3 bit storage be vector f, rear 3 bit storage be part verification vector p
xWhen each clock arrives, register R
A+4Serial ring shift left 1 time, register R
A+5Serial moves to left 1 time.Repeat said process, b-3 clock cycle of process finished computing.At this moment, register R
A+4That store still is part verification vector p
1, register R
A+5That store is part verification vector p
2=(p
x, p
y).
The invention provides a kind of high efficient coding method of QC-LDPC code, in conjunction with the encoder (as shown in Figure 3) of QC-LDPC code in the CCSDS near-earth communication system, its coding step is described below:
In the 1st step, at first order streamline, input message vector s uses parallel SRAA filter calculating section verification vector p
1And p
xAnd vector f;
The 2nd step, at second level streamline, utilize the operation result of first order streamline, use filtering LFSR compute vector q, u and part verification vector p
y, and output codons v=(s, p
1, p
x, p
y).
Fig. 6 has summed up the hardware resource consumption of each part of encoder and whole circuit.
Fig. 7 has summed up each coding step and required processing time of whole cataloged procedure.Notice that owing to adopted two-stage streamline mechanism, the required processing time of whole cataloged procedure is depended on the maximum of single step.
Fig. 8 has compared traditional parallel SRAA method and coding rate of the present invention and resource consumption.Coding rate of the present invention and parallel SRAA method are basic identical.The present invention used less register, XOR gate and with door, the amount of expending is respectively 73%, 51% and 50% of parallel SRAA method.As fully visible, compare with traditional parallel SRAA method, the present invention is keeping under the constant condition of coding rate, has that resource consumption is few, power consumption is little, low cost and other advantages.
Above-described embodiment is more preferably embodiment of the present invention, and the common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacement all should be included in protection scope of the present invention.
Claims (8)
1. encoder that is suitable for the QC-LDPC code that CCSDS near-earth communication system adopts, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, jThe array that consists of, check matrix H are the arrays that is made of c * t b * b rank circular matrix, wherein, a=14, t=16, b=511, c=t-a=2,1≤i≤a, 1≤j≤t, the corresponding code word v=(s, p) of generator matrix G, that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p=(e
1, e
2..., e
1022), take the b bit as one section, information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), verification vector p is divided into the c=2 section, i.e. p=(p
1, p
2), wherein, p
2=(p
x, p
y), p
x=(e
512, e
513, e
514), p
y=(e
515, e
516..., e
1022), it is characterized in that described encoder comprises following parts:
Controller, the operation of the input of control information vector, the output of code word and other parts realizes two level production lines;
Parallel shift register adds sum filter, is used for calculating section verification vector p
1, p
xAnd vector f;
The filtering linear feedback shift register is used for compute vector q, u and part verification vector p
y
2. encoder as claimed in claim 1 is characterized in that, described encoder associating generator matrix G and check matrix H are encoded: use first G calculating section verification vector p
1And p
x, re-use the near lower triangular check matrix H
ALTCalculating section verification vector p
yThereby, obtain code word v=(s, p
1, p
x, p
y).
3. encoder as claimed in claim 2 is characterized in that, described near lower triangular check matrix H
ALTBy being carried out conversion, check matrix H obtains: first with all permutation matrixes in H the 1st, 2 row respectively ring shift rights 472,319, again with two capable additions of piece.
4. encoder as claimed in claim 1 is characterized in that, described parallel shift register adds sum filter by register R
1～R
A+3, register R
I, j, multidigit two input and a door M
I, j, multidigit two input XOR gate A
I, jWith 56 input XOR gate A
1Form, wherein, 1≤i≤a, 1≤j≤c, A
1The corresponding H of 56 inputs
ALT56 permutation matrixes in the front a piece row, each permutation matrix place piece row number equal register R
1～R
aSubscript, its ring shift right figure place adds the 1 tap position that equals register, R
1～R
A+2, R
I, j, M
I, jAnd A
I, jConsist of improved parallel shift register and added accumulator, be used for calculating section verification vector p
1And p
x, R
1～R
a, R
A+3And A
1Consist of 56 tap filters, be used for compute vector f.
5. such as claim 1,4 described encoders, it is characterized in that described parallel shift register adds simultaneously calculating section verification vector p of sum filter
1, p
xAnd vector f:
When initial, register R
1～R
aThat store is information vector s, register R
A+1And R
A+2Be cleared register R
I, 1Load circular matrix G in the generator matrix
I, a+1First trip, register R
I, 2Load circular matrix G in the generator matrix
I, a+2Front 3 bits of first trip, wherein, 1≤i≤a;
When each clock arrives, register R
1～R
aThe serial ring shift left is 1 time separately, 56 input XOR gate A
1The result of calculation serial is moved to left into register R
A+3, register R
I, 1The serial ring shift right is 1 time separately, register R
I, 2Serial moves to right 1 time and from G separately
I, a+2The back of first trip moves into 1 new bit, multidigit two inputs and door M
I, jCarry out the multiplying of scalar and vector, M
1, j～M
A, jThe sum of products and register R
A+jAdd up, wherein, 1≤j≤c;
Repeat said process, b clock cycle of process finished computing, at this moment, and register R
1～R
aThat store still is information vector s, register R
A+1, R
A+2And R
A+3That store is respectively part verification vector p
1, p
xAnd vector f.
6. encoder as claimed in claim 1 is characterized in that, described filtering linear feedback shift register is by register R
A+4～R
A+5With XOR gate A
2～A
4Form A
2The corresponding H of 4 inputs
ALT4 permutation matrixes in the a+1 piece row, the ring shift right figure place of each permutation matrix adds 4 and equals register R
A+4The tap position, R
A+4And A
2Consist of 4 tap filters, be used for compute vector q, A
3, A
4And R
A+5Consist of linear feedback shift register, be used for compute vector u and part verification vector p
y, XOR gate A
3Output vector u, XOR gate A
4Output verification vector p
y
7. such as claim 1,6 described encoders, it is characterized in that described filtering linear feedback shift register is compute vector q, u and part verification vector p simultaneously
y:
When initial, register R
A+4That store is part verification vector p
1, register R
A+5Front b-3 bit storage be vector f, rear 3 bit storage be part verification vector p
x
When each clock arrives, register R
A+4Serial ring shift left 1 time, register R
A+5Serial moves to left 1 time;
Repeat said process, b-3 clock cycle of process finished computing, at this moment, and register R
A+4That store still is part verification vector p
1, register R
A+5That store is part verification vector p
2=(p
x, p
y).
8. coding method that is suitable for the QC-LDPC code of CCSDS near-earth communication system employing, the generator matrix G of QC-LDPC code is by a * t b * b rank circular matrix G
I, jThe array that consists of, check matrix H are the arrays that is made of c * t b * b rank circular matrix, wherein, a=14, t=16, b=511, c=t-a=2,1≤i≤a, 1≤j≤t, the corresponding code word v=(s, p) of generator matrix G, that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p=(e
1, e
2..., e
1022), take the b bit as one section, information vector s is divided into a section, i.e. s=(s
1, s
2..., s
a), verification vector p is divided into the c=2 section, i.e. p=(p
1, p
2), wherein, p
2=(p
x, p
y), p
x=(e
512, e
513, e
514), p
y=(e
515, e
516..., e
1022), it is characterized in that described coding method may further comprise the steps:
In the 1st step, at first order streamline, input message vector s uses parallel shift register to add sum filter calculating section verification vector p
1, p
xAnd vector f;
The 2nd step, at second level streamline, utilize the operation result of first order streamline, use filtering linear feedback shift register compute vector q, u and part verification vector p
y, and output codons v=(s, p
1, p
x, p
y).
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| CN113422611A (en) * | 2021-05-19 | 2021-09-21 | 上海大学 | Highly parallel encoding method of QC-LDPC encoder |
| CN113422611B (en) * | 2021-05-19 | 2022-11-04 | 上海大学 | Highly parallel encoding method of QC-LDPC encoder |
| TWI823436B (en) * | 2022-06-23 | 2023-11-21 | 慧榮科技股份有限公司 | Apparatus and method for generating low-density parity-check (ldpc) code |
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