TWI823436B - Apparatus and method for generating low-density parity-check (ldpc) code - Google Patents

Abstract

The invention is related to an apparatus and a method for generating low-density parity-check (LDPC) code. The apparatus includes an LDPC encoder, a look-ahead circuit and an exclusive-OR calculator. The LDPC encoder is arranged operably to encode the former part of user data with a parity check matrix using a two-stage encoding algorithm to generate a first calculation result. The look-ahead circuit is arranged operably to perform a dot product on the latter part of user data with one of plurality of feature rows corresponding to the parity check matrix to generate a second calculation result. The exclusive-OR calculator is arranged operably to perform an exclusive-OR calculation on the first calculation result and the second calculation result to generate the former part of LDPC code. With the apparatus described above, the time consumed by the two two-stage encoding algorithm would be reduced, resulting in the elimination of timing bubble between the transmissions of user data and LDPC code.

Description

Device and method for generating low-density parity check code

The present invention relates to a storage device, and in particular, to a device and method for generating a low-density parity check code.

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processor (Host) can provide any address to access the NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of the NOR flash memory in a timely manner. material. On the contrary, NAND flash memory does not have random access, but sequential access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write a sequence of Bytes values into the NAND flash memory to define the type of request command (Command) (such as , read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory). Improving the accuracy of data transmission to flash memory modules has always been an important issue that affects the overall performance of flash memory controllers. Therefore, the present invention proposes a low-density parity check code generation device and method for improving the accuracy of data transmission to a flash memory module.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

This specification relates to a low-density parity check code generation device, including: a low-density parity check code encoder, a look-ahead circuit and a mutual exclusion or calculation unit. The low-density parity check code encoder is used to use a two-stage encoding algorithm to encode user data using a parity check matrix. The front part is encoded to produce the first calculation result. The lookahead circuit is configured to perform an inner product calculation on the rear part of the user data using one of the plurality of feature columns corresponding to the parity check matrix in each iteration to generate a second calculation result. The mutual exclusion or calculation unit is used to perform mutual exclusion or calculation on the first calculation result and the second calculation result to generate the front part of the low-density parity check code.

This specification also relates to a method of generating a low-density parity check code executed by a controller. The controller is coupled to the switch, the low-density parity check code encoder and the look-ahead circuit. The method includes: when the front part of the user data is transmitted to the low-density parity check code encoder, controlling the switch to allow the rear part of the user data to feed into the look-ahead circuit, and sending a first signal to the low-density parity check code the check code encoder to start the second stage encoding; and when the rear part of the user data is transmitted to the look-ahead circuit, a second signal is sent to the low-density parity check code encoder to start outputting the first calculation result to the mutex or calculation The unit sends a third signal to the look-ahead circuit to start outputting the second calculation result to the mutual exclusive OR calculation unit.

One of the advantages of the above-described embodiment is that the calculation time of the two-stage encoding algorithm can be shortened by the above-described device, thereby eliminating the time gap between the transmission of user data and low-density parity check codes.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

10: Electronic devices

110: Host side

130:Flash controller

131:Host interface

134: Processing unit

136: Random access memory

138:NAND flash controller

139:Flash memory interface

150:Flash memory module

151:Interface

153#0~153#15: NAND flash memory unit

CH#0~CH#3: Channel

CE#0~CE#3: enable signal

302:User information

304:LDPC code

310:LDPC encoder

320:Multiplexer

tb: time slot

402#1: The front part of the user data

402#2: End of user data

404#1,404#2: Calculation result

406#1: The front part of LDPC code

406#2: The rear part of the LDPC code

510,610:Controller

520:Switcher

530,560: LDPC encoder

540: Forward looking circuit

550: Mutual exclusion or calculation unit

570:Multiplexer

620: Inner product calculation unit

630: Feature column generation circuit

640: Data register

680,680#0~680#3: Feature column

710:Multiplexer

720#0~720#3: Input port

730: Source register

730#0~730#3: Register

810#0~810#3:D flip-flop

S1010~S1040: Method steps

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

Figure 3 is a schematic diagram of encoding and transmission of user data and LDPC codes according to some embodiments.

FIG. 4 is a schematic diagram of eliminating the time gap between the transmission of user data and LDPC codes according to an embodiment of the present invention.

FIG. 5 is a block diagram of an LDPC code generating device according to an embodiment of the present invention.

FIG. 6 is a block diagram of a front-view circuit according to an embodiment of the present invention.

7 and 8 are block diagrams of a feature sequence generating circuit according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of a feature column according to an embodiment of the present invention.

Figure 10 is a flow chart of a control method according to an embodiment of the present invention.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority, precedence relationship between them, or that they are one element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The electronic device 10 includes a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. The host 110 and the host interface (Host Interface) 131 of the flash memory controller 130 can be connected by Universal Serial Bus (USB), advanced Advanced technology attachment (ATA), serial advanced technology attachment (SATA), peripheral component interconnect express (PCI-E), Universal Flash Storage, Communication protocols such as UFS) and Embedded Multi-Media Card (eMMC) communicate with each other. The flash interface (Flash Interface) 139 of the NAND Flash Controller (NFC) 138 and the flash memory module 150 can communicate with each other using a Double Data Rate (DDR) communication protocol, for example, open NAND flash (Open NAND Flash Interface, ONFI), double data rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and When executing software and/or firmware instructions, the functions described later are provided. The processing unit 134 receives host commands through the host interface 131, such as read command (Read Command), write command (Write Command), discard command (Discard Command), erase command (Erase Command), etc., schedules and executes these commands. . The flash memory controller 130 also includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, is used to configure space as a data buffer to store user data (also called host data) read from the host 110 and about to be written to the flash memory module 150, and from the flash memory module. The group 150 reads and outputs the user data to the host 110 . The random access memory 136 can also store data needed during execution, such as variables, data tables, host-to-Flash Address Mapping Table (H2F table for short), flash memory and host addresses. Comparison table (Flash-to-Host Address Mapping Table, referred to as F2H table), etc. The NAND flash memory controller 138 provides functions required to access the flash memory module 150, such as Such as command sequencer (Command Sequencer), low-density parity-check (Low-Density Parity-Check, LDPC), etc.

The flash memory controller 130 can be configured with a shared bus architecture (Shared Bus Architecture) for coupling components to each other to transmit data, addresses, control signals, etc. These components include the host interface 131, the processing unit 134, and the RAM 136 , NAND flash memory controller 138, etc. The bus includes parallel physical lines that connect two or more components in the flash memory controller 130 . A shared bus is a shared transmission medium. At any time, only two devices can use these lines to communicate with each other and transfer data. Data and control signals can propagate in both directions between components along data and control lines respectively, but on the other hand, address signals can only propagate in one direction along address lines. For example, when the processing unit 134 wants to read data at a specific address of the RAM 136, the processing unit 134 transmits the address to the RAM 136 on the address line. Then, the data at this address will be returned to the processing unit 134 on the data line. In order to complete the data reading operation, control signals are transmitted using control lines.

The flash memory module 150 provides a large amount of storage space, usually hundreds of gigabytes (GB) or even several terabytes (TB), for storing a large amount of user data. For example, high-resolution pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array can be configured as single-level cells (Single Level Cells, SLCs) and multi-level cells (Multiple Level Cells, MLCs). (Triple Level Cells, TLCs), Quad-Level Cells (QLCs), or any combination of the above. The processing unit 134 can write user data to a specified address (destination address) in the flash memory module 150 through the flash memory interface 139, and read user data from a specified address (source address) in the flash memory module 150. . The flash memory interface 139 uses several electronic signals to coordinate the transmission of data and commands between the flash memory controller 130 and the flash memory module 150, including data lines (Data Line), clock signals (Clock Signal) and control signals (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control The control signal line can be used to transmit Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), Write Enable (WE) ) and other control signals.

Referring to Figure 2, the interface 151 in the flash memory module 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to four NAND flash memory units, for example, channel CH#0 is connected to NAND flash memory cells 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory cell can be packaged as an independent chip (die). The flash memory interface 139 can send one of the enable signals CE#0 to CE#3 through the interface 151 to enable the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, and 153#8 to 153#11. , or 153#12 to 153#15, and then read user data from the enabled NAND flash memory unit in a parallel manner, or write user data to the enabled NAND flash memory unit. Those skilled in the art can change the design of the flash memory module 150 according to system requirements, configure more or fewer channels in the flash memory module 150, and/or connect each channel to more or fewer NAND flash memory cells. , the present invention is not limited thereby.

所屬技術領域人員知道可使用習知的奇偶校檢矩陣和高效演算法來產生低密度奇偶檢查碼，例如二階段編碼(2-stage Encoding)等。 The NAND flash memory controller 138 may include a low-density parity check encoder (LDPC Encoder) for generating a low-density parity check code (LDPC Code) based on user data, which is a linear error correction code (Linear Error Correcting Code). ). For example, the generation of LDPC code can be expressed by the following formula: MSG _1xn ☉ PCM _nx(n+m) =CW _1x(n+m) where MSG _1xm represents a 1-column, n-row matrix of user data, PCM _{nx (n+m)} represents n columns and (n+m) rows parity check matrix (Parity Check Matrix), CW _1x(n+m) represents 1 column and (n+m) of the last generated codeword (Codeword) Row matrix, ☉ represents Modulo 2 Multiplication. The parity check matrix may contain a Quasi-Cyclic (QC) structure, and the value of the first n bits in CW _1x(n+m) is equal to the value of MSG _1xn , while the value of the first n bits in CW _1x(n+m) The value of the last m bits is called the LDPC code. Examples are as follows:

Those skilled in the art know that conventional parity check matrices and efficient algorithms can be used to generate low-density parity check codes, such as two-stage encoding (2-stage Encoding).

Referring to part (A) of FIG. 3 , in some embodiments, the NAND flash memory controller 138 may include an LDPC encoder 310 and a multiplexer (Multiplexer) 320 . The LDPC encoder 310 uses a predetermined parity check matrix to encode a fixed-length user data 302 into a fixed-length LDPC code 304, for example, encoding a 2KB (byte) user data 302 into a 512B LDPC Code 304. Initially, the multiplexer 320 is used to output user data 302 to the flash memory module 150 . After the user data 302 transmission is completed, the multiplexer 320 is controlled to output the LDPC code 304 to the flash memory module 150 . However, referring to part (B) of Figure 3 , in the LDPC encoder 310 implemented using some algorithms, the LDPC encoder 310 needs to operate for a period of time tb after receiving the complete user information 302 to generate the LDPC code 304 , so that the LDPC code 304 can start to be transmitted to the flash memory module 150. This operation time tb is also called a time gap (Timing Bubble). For example, in two-stage encoding, the parity check matrix can be split into two matrices, H=[H1,H2]. In the first stage, the user data (also called Message Bits) and the first matrix H1 are subjected to inner product calculation (Dot Product) to generate a partial parity code (Partial Parity). In the second stage, the inner product of the partial parity check code and the inverse matrix H2 ^T of the second matrix is calculated to generate the LDPC code. Since the second stage needs to use the inner product calculation of the inverse matrix, the calculation complexity is high. Therefore, the LDPC encoder 310 needs to calculate for a period of time to obtain the LDPC code, resulting in a time gap. However, the high-speed transmission interface cannot be interrupted when running. If there is a time gap in the process of transmitting data to the flash memory module 150, the data transmitted to the flash memory module 150 is prone to errors.

In order to eliminate the time gap as described above, with reference to Figure 4, an embodiment of the present invention proposes an LDPC code generation method and device for eliminating the time gap tb as shown in Figure 3. Since the LDPC encoder 310 needs to run for a fixed period of time tb before it can start to generate the completed LDPC code, the embodiment of the present invention divides the finally generated LDPC code 304 into two parts: the front part (a) 406#1 and the rear part ( b)406#2. The length of front part (a) 406#1 depends on the time Depends on the length of gap tb. For example, if the LDPC encoder 310 needs 2 clock cycles to start outputting the LDPC code, and 1 clock cycle can output 4B of data to the flash memory module 150, then the front part (a) of the LDPC code 304 The length of 406#1 is fixed at 8B. The entire user information 302 can be divided into two parts: the front part (a) 402#1 and the rear part (b) 402#2, and is used for the front part (a) 402#1 and the rear part (b) 402#2 respectively. Two circuits are used to encode the front part (a) 406#1 and the rear part (b) 406#2 of the LDPC code 304.

Referring to the LDPC code generation device shown in Figure 5, a circuit may include an LDPC encoder 560 (for example, the previously implemented LDPC encoder 310), using a two-stage encoding algorithm, using a predefined parity check matrix pair The user data 302 encodes the rear part (b) 406#2 of the LDPC code 304. Another circuit may include a switcher 520, an LDPC encoder 530, a Look-ahead Circuit 540, an Exclusive-OR Calculation Unit 550, and a multiplexer 570 for using a predefined The parity check matrix quickly encodes the front part (a) 406#1 of the LDPC code 304 of the user data 302, so that the LDPC code 304 can be transmitted immediately after the rear part (b) of the user data 302 is sent to the flash memory module 150. The front part (a) 406#1 and the rear part (b) 406#2 to the flash memory module 150, so that there is no time gap between the transmission of the user data 302 and the LDPC code 304 (as shown in the lower half of Figure 4 shown).

The switch 520 includes an input terminal and two output terminals. The input terminal is used to receive the user data 302 . One output terminal is coupled to the input terminal of the LDPC encoder 530 , and the other output terminal is coupled to the input terminal of the look-ahead circuit 540 . The switch 520 is selectively coupled to the input end of the LDPC encoder 530 or the look-ahead circuit 540 under the control of the controller 510 . The controller 510 may control the switch 520 before starting to encode the user data 302 so that the user data 302 is fed into the LDPC encoder 530 . Then, after the front part (a) 402#1 of the user data 302 is completely fed into the LDPC encoder 530, the controller 510 controls the switch 302 to allow the back part (b) 402#2 of the user data 302 to be fed into the LDPC encoder 530. Enter the forward looking circuit 540. The LDPC encoder 530 uses a two-stage encoding algorithm to encode the front part (a) 402#1 of the user data 302 with a predefined parity check matrix to generate encoded data 404#1. Controller 510 can When the LDPC encoder 530 calculates most of the partial parity codes for the front part (a) 402#1 of the user data 302, the LDPC encoder 530 is instructed to start performing the second stage of encoding (that is, to start the second stage of encoding early). stage coding). Since the rear part (b) 402#2 of the user data 302 is not fed into the LDPC encoder 530 during the execution of the second stage of encoding, the lookahead circuit 540 Inner product calculation is performed corresponding to the feature row of the parity check matrix to generate encoding data 404#2, which is used to compensate the calculation result 404#1 of the LDPC encoder 530. It should be noted here that those skilled in the art understand that since the inner product calculation described in this specification is performed in a binary field (Binary Field), the matrix inner product calculation described in this specification is equivalent to modulo 2 multiplication. The mutual exclusion OR calculation unit 550 is coupled to the output ends of the LDPC encoder 530 and the look-ahead circuit 540, and performs mutual exclusion OR calculation on the output 404#1 of the LDPC encoder 530 and the output 404#2 of the look-ahead circuit 540 batch by batch. , for example, each batch can be mutually exclusive or calculated for 8B outputs 404#1 and 404#2. The multiplexer 570 includes two input terminals and an output terminal. One input terminal is coupled to the output of the mutex calculation unit 550 , the other input terminal is coupled to the output of the LDPC encoder 560 , and the output terminal is coupled to the flash memory module 150 . The controller 510 may control the multiplexer 570 at the beginning of generating the LDPC code, or after the rear part (b) 402#2 of the user data 302 is fed to the look-ahead circuit 540, for converting the mutual exclusion or calculation unit 550 The output terminal is coupled to the flash memory module 150, so that the calculation result of the mutual exclusive OR calculation unit 550 (that is, the front part (a) 406#1 of the LDPC code 304) can be output to the flash memory module 150. After the controller 510 completes outputting the front part (a) 406#1 of the LDPC code 304 to the flash memory module 150, it controls the multiplexer 570 to couple the output end of the LDPC encoder 560 to the flash memory module 150, so that The calculation result of the LDPC encoder 560 (that is, the rear part (b) 406#2 of the LDPC code 304) can be output to the flash memory module 150.

Referring to the embodiment of the look-ahead circuit 540 shown in FIG. 6 , it includes a controller 610 , an inner product calculation unit 620 , a feature column generation circuit 630 and a data register 640 . The data register 640 is used to store the last part (b) 402#2 of the user data 302. The feature string generation circuit 630 may include a source register for storing a look-ahead basis, the length of which is preset to |m ₂ |+|p _a |-1, m ₂ represents the rear part of the user data 302 ( b) The length of 402#2, p _a represents the length of the front part of LDPC code 304 (a) 406#1. The lookahead basis is derived from the parity check matrix and contains the subset of the parity check matrix required to encode the rear part (b) 402#2 of the user data 302. In addition, the length of the feature row is equal to the length of the rear part (b) 402#2 of the user data 302. For example, assuming that the rear part (b) 402#2 of the user data 302 is 8B (that is, 64 bits) and the front part (a) 406#1 of the LDPC code 304 is 8B (that is, 64 bits), then the source register The length of is 127 bits, and the length of the feature column 680 is 8B (that is, 64 bits). Since the parity check matrix contains a cyclic structure, except for the first iteration, the feature column used for calculation in each iteration is the result of the previous feature column being cyclically shifted to the right by one bit. Referring to the feature column diagram shown in FIG. 9 , each column represents a forward-looking basis, and the backslash in each column partially represents the feature column 680 in the forward-looking basis. Feature column 680#1 is the result of feature column 680#0 being rotated to the right by one bit, feature column 680#2 is the result of feature column 680#1 being rotated to the right by one bit, and so on. The feature column generation circuit 630 further includes a circuit for obtaining the feature column 680 required for each iteration from the lookahead basis. In each iteration, the controller 610 sends a signal to the feature string generation circuit 630 to drive the feature string generation circuit 630 to output the feature string 680 required for this iteration. The inner product calculation unit 620 is coupled to the feature sequence generation circuit 630 and the data register 640. In each iteration, the inner product calculation is performed on the feature sequence output by the feature sequence generation circuit 630 and the value stored in the data register 640 to obtain the calculation result 404. #2, and output the calculation result 404#2 to the exclusive OR calculation unit 550.

Referring to the embodiment of the feature column generation circuit 630 shown in FIG. 7 , it includes a multiplexer 710 and a source register 730 . Initially, the source register 730 stores a default look-ahead basis. The multiplexer 710 includes a plurality of input ports, and each input port is respectively connected to a preset number of registers in the source register 730 through a preset number of physical lines in a specified order. For example, the input port 720#0 of the multiplexer 710 is connected to the registers 730#1, 730#2, and 730#3 in sequence through physical lines; the input port 720#1 of the multiplexer 710 is connected to the registers in sequence through physical lines. 730#2, 730#3, 730#0; the input port 720#2 of the multiplexer 710 passes through the real The body lines are connected to the registers 730#3, 730#0, and 730#1 in sequence; and the input port 720#3 of the multiplexer 710 is connected to the registers 730#0, 730#1, and 730#2 in sequence through the physical lines. In the first iteration, the multiplexer 710 receives a control signal to connect the input port 720#0 to the output port for outputting the values of the registers 730#1, 730#2, and 730#3 as the feature sequence 680. In the second iteration, the multiplexer 710 receives a control signal to connect the input port 720#1 to the output port for outputting the values of the registers 730#2, 730#3, and 730#0 as the feature sequence 680, and so on. And so on.

Referring to the embodiment of the feature sequence generating circuit 630 shown in FIG. 8 , it includes a bit-shifter (Bit-shifter) connected in series with a plurality of D flip-flop (D flip-flop) 810 #0 to 810 #3. The output terminal q of each D flip-flop is connected to the input terminal d of the next D flip-flop, forming a ring. Initially, the controller (not shown in Figure 8) sets each of the D flip-flops 810#0 to 810#3 to store the default forward-looking basis. The outputs of a part of the D flip-flops, such as the outputs of the D flip-flops 810#1, 810#2, and 810#3, form a feature sequence. The controller sets a D flip-flop so that it stores a logic "1", or resets a D flip-flop so that it stores a logic "0". Then, when each D flip-flop detects a change in the clock signal clk (that is, rising edges and falling edges), it outputs the value stored in it to the next D flip-flop for storage. In each iteration, the outputs 680[0] to 680[2] of the D flip-flops 810#1 to 810#3 are sequentially collected as the feature sequence 680. For example, the controller initially drives the D flip-flops 810#0 to 810#3 to store the default forward-looking base "0b0001". The outputs of D flip-flops 810#0 to 810#3 are "0b001" in the first iteration; the outputs of D flip-flops 810#0 to 810#3 are "0b000" in the second iteration; The outputs of the flip-flops 810#0 to 810#3 are "0b100" in the third iteration; the outputs of the D flip-flops 810#0 to 810#3 are "0b010" in the fourth iteration.

Refer to the flowchart of the control method executed by the controller 510 shown in FIG. 10 . The details are as follows:

Step S1010: Send a signal to the switch 520 to allow the user data 302 to be fed into the LDPC encoder 530 (also called the first LDPC encoder).

Step S1020: After the front part (a) 402 #1 in the user data 302 is transmitted, control the switch 520 to couple the input terminal to the front-view circuit 540 so that the back part (b) 402 in the user data 302 #2 is fed into the lookahead circuit 540 and sends a signal to the LDPC encoder 530 to start the second stage encoding (ie, start the second stage encoding early).

Step S1030: After the transmission of the rear part (b) 402#2 in the user data 302 is completed, control the multiplexer 570 so that the output end of the mutex or calculation unit 550 is connected to the output end of the multiplexer 570 for allowing The calculation result of the mutual exclusion or calculation unit 550 (that is, the front part (a) 406#1 of the LDPC code) can be written to the flash memory module 150; a signal is sent to the LDPC encoder 530 to start outputting the calculation result 404#1; and A signal is given to the lookahead circuit 540 to start outputting the calculation result 404#2; and a signal is sent to the LDPC encoder 560 (which may also be called the second LDPC encoder) to start calculating the rear part (b) 406#2 of the LDPC code.

Step S1040: When the transmission of the front part (a) 406#1 of the LDPC code is completed, control the multiplexer 570 so that the output end of the LDPC encoder 560 is connected to the output end of the multiplexer 570 for allowing the LDPC encoder 560 The calculation result (that is, the last part of the LDPC code (b) 406#2) can be written to the flash memory module 150; and a signal is sent to the LDPC encoder 560 to start outputting the calculation result 406#2.

Although Figures 1, 2, 5 to 8 contain the above-described elements, it does not rule out the use of more other additional elements to achieve better technical effects without violating the spirit of the invention. In addition, although the flow chart in Figure 10 is executed in a specified order, those skilled in the art can modify the order of these steps without violating the spirit of the invention and achieve the same effect. Therefore, the present invention does not You are not limited to using only the order described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of claims in the application must be in the broadest possible way. The formula is interpreted to include all obvious modifications and similar settings.

302:User information

304:LDPC code

402#1: The front part of the user data

402#2: End of user data

404#1,404#2: Calculation results

406#1: The front part of LDPC code

406#2: The rear part of the LDPC code

510:Controller

520:Switcher

530,560: LDPC encoder

540: Forward looking circuit

550: Mutual exclusion or calculation unit

570:Multiplexer

Claims (13)

A device for generating low-density parity check codes, including: a first low-density parity check code encoder for using a two-stage encoding algorithm to encode the front part of user data with a parity check matrix to generate a first calculation Result; a look-ahead circuit for performing an inner product calculation on the rear part of the user data with one of the plurality of feature columns corresponding to the parity check matrix at each iteration to generate a second calculation result; and an exclusive OR calculation unit, coupled to the output end of the first low-density parity check code encoder and the output end of the lookahead circuit, for performing mutual exclusion on the first calculation result and the second calculation result or compute, the front part that produces a low-density parity check code. The device for generating a low-density parity check code as described in claim 1, including: a second low-density parity check code encoder for using the two-stage encoding algorithm and using the parity check matrix to The data is encoded to produce the rear part of the low-density parity check code. The device for generating low-density parity check codes according to claim 2, comprising: a multiplexer including a first input terminal, a second input terminal and a first output terminal, the first input terminal being coupled to the mutual The output terminal of the OR calculation unit, the second input terminal is coupled to the output terminal of the second low-density parity check code encoder, the first output terminal is coupled to the flash memory module; and the first controller , coupled to the multiplexer, for controlling the multiplexer to convert the second low-density parity check code to the second low-density parity check code after the front part of the low-density parity check code is output to the flash memory module. The output end of the code encoder is coupled to the flash memory module, allowing the rear part of the low-density parity check code to be output to the flash memory module. The device for generating low-density parity check codes as described in claim 3, including: a switch including a third input terminal, a second output terminal, and a third output terminal, and the third input terminal is used to receive the user data, the second output terminal is coupled to the input terminal of the first low-density parity check code encoder, and the third output terminal is coupled to the input terminal of the look-ahead circuit, wherein the first control A device coupled to the switch, the first low density parity check code encoder and the lookahead circuit for transmitting to the first low density parity check code in the front part of the user data When the encoder is completed, the switch is controlled so that the third input terminal is coupled to the third output terminal, the rear part of the user data is fed into the forward-looking circuit, and a first signal is emitted. Enable the first low-density parity check code encoder to start a second stage of encoding; when the rear part of the user data is transmitted to the look-ahead circuit, a second signal is sent to the first low-density parity check code encoder. The parity check code encoder starts outputting the first calculation result to the mutual exclusive OR calculation unit, and sends a third signal to the lookahead circuit to start outputting the second calculation result to the mutual exclusive OR calculation unit. . The device for generating a low-density parity check code as claimed in claim 1, wherein the look-ahead circuit includes: a data register for storing the rear part of the user data; and a feature string generation circuit for based on the foregoing A look-ahead basis generates the feature columns required for each iteration, wherein the look-ahead basis includes a subset of the rear portion of the parity check matrix used to encode the user data, wherein, except for In addition to the feature column required for one iteration, the feature column required for each iteration is the result of a cyclic right shift of the feature column used in the previous iteration; an inner product calculation unit is coupled to the feature column Generating a circuit and the data register for performing an inner product calculation on the rear part of the user data and the corresponding feature column in each iteration, obtaining a calculation result, and outputting the calculation result to the a mutual exclusion or calculation unit; and a second controller for outputting a control signal to the feature sequence generating circuit in each iteration, and driving the feature sequence generating circuit to output the corresponding feature sequence. The device for generating a low-density parity check code according to claim 5, wherein the parity check matrix includes a cyclic-like structure. The device for generating low-density parity check codes as claimed in claim 5, wherein the length of the look-ahead basis is |m ₂ |+| _pa |-1, and m ₂ represents the rear part of the user information The length of p _a represents the length of the front part of the low-density parity check code. The device for generating low-density parity check codes as claimed in claim 5, wherein the feature sequence generating circuit includes: a source register for storing the lookahead basis; and a multiplexer including a plurality of input ports and a Output ports, each of the input ports is connected to the preset number of registers in the source register through a preset number of physical lines in a specified order, for connecting the specified input port when a control signal is received. to the output port to output the corresponding feature column. The device for generating low-density parity check codes according to claim 5, wherein the feature sequence generating circuit includes: a plurality of D flip-flops for initially storing the look-ahead basis, wherein each of the The output end of the D flip-flop is connected to the input end of the next D flip-flop, forming a ring, wherein the output of a part of the D flip-flop forms the corresponding feature column, wherein each of the D flip-flop When the D flip-flop detects a change in the clock signal, it outputs the value stored therein to the next D flip-flop for storage. A method for generating a low-density parity check code, executed by a controller, wherein the controller is coupled to a switch, a first low-density parity check code encoder and a look-ahead circuit, the method includes: in user data When the front part is transmitted to the first low-density parity check code encoder, the switch is controlled to allow the rear part of the user data to be fed into the look-ahead circuit, and a first signal is sent to the first The low-density parity check code encoder is used to start the second-stage encoding, wherein the first low-density parity check code encoder is coupled to the switch and is used to use the two-stage encoding algorithm to encode the parity check matrix. The front part of the user data is encoded to generate a first calculation result, wherein the look-ahead circuit is coupled to the switch and is used to encode multiple values corresponding to the parity check matrix at each iteration. One of the feature columns performs an inner product calculation on the rear part of the user data to generate a second calculation result; and when the transmission of the rear part of the user data to the look-ahead circuit is completed, a second A signal is sent to the first low-density parity check code encoder to start outputting the first calculation result to the mutex or calculation unit, and a third signal is sent to the lookahead circuit to start outputting the second calculation result to the The mutual exclusive or calculation unit, wherein the mutual exclusive or calculation unit is coupled to the first low density parity check code encoder and the look-ahead circuit, and is used to compare the first calculation result and the second The results of the computation are mutually exclusive or computed, producing the front part of the low-density parity check code. The method for generating a low-density parity check code as described in claim 10, including: after the front part of the low-density parity check code is output to the flash memory module, controlling the multiplexer to convert the second low-density parity check code to the flash memory module. A check code encoder is coupled to the flash memory module to allow the rear part of the low-density parity check code to be output to the flash memory module, wherein the input end of the multiplexer is coupled to the mutex or calculation unit and the second low density parity check code encoder, Wherein, the output end of the multiplexer is coupled to the flash memory module, wherein the second low-density parity check code encoder is used to use the two-stage encoding algorithm to encode the parity check matrix. The user data is encoded to generate the rear portion of the low-density parity check code. The method for generating a low-density parity check code as described in claim 10, wherein the parity check matrix includes a cyclic-like structure. The method for generating low-density parity check codes as described in claim 12, wherein, in addition to the feature columns required for the first iteration, the feature columns required for each iteration are the feature columns used in the previous iteration. The result of loop shifting one bit to the right.

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