CN102340318A - Method for encoding quasi-cycle LDPC (Low Density Parity Check) codes - Google Patents

Abstract

The invention relates to a method for encoding a quasi-cycle LDPC (Low Density Parity Check) code. The method comprises the steps of: multiplying an input code by a sparse matrix A to obtain a first vector f1, and multiplying the input code by a matrix C to obtain a second vector f2; performing forward substitution on the first vector f1 in a first pipeline register and a spare matrix T with dual diagonals to obtain a third vector f3; multiplying f3 and a matrix E to obtain a fourth vector f4; performing vector additiono on the second vector f2and a fourth vector f4 in the first pipeline register to obtain an output check bit P1 of a first encoder; multiplying the output check bit P1 of the first encoder by a matrix B to obtain a fifth vector f5; performing vector addition on the first vector f1 and the fifth vector f5 to obtain a sixth vector f6; and performing forward substitution on the sixth vector f6 and the sparse matrix T with dual diagonals to obtain an output check bit P2 of a second encoder. According to the invention, methods of parallel execution and hardware pipelining are fully utilized to make the encoders have highest speed and throughput per hour.

Description

The coding method of quasi-cyclic LDPC code

Technical field

The invention belongs to the encoder techniques field, particularly relate to a kind of coding method of quasi-cyclic LDPC code.

Background technology

Loe-density parity-check code (Low-Density Parity-Check codes; LDPC) propose in 1962 by Gallager the earliest; Tanner in 1981 introduces two-dimensional plot and describes the LDPC sign indicating number, and Mackey etc. found the LDPC sign indicating number once more and proved that the LDPC sign indicating number is a kind of good sign indicating number that approaches Shannon (shannon) limit nineties.The LDPC sign indicating number is used widely in digital communication and storage.All used LDPC as its channel coding schemes in standards such as 802.16e, 802.11n, 802.3a, DVB-S2, DMB-T, CMMB.

The building method of LDPC sign indicating number mainly contains random configuration and structure construction method at present.The random configuration method comprises random search, PEG algorithm etc., and wherein, the code word of PEG algorithm construction has good performance, the LDPC sign indicating number of best performance in the medium code length that is considered to construct at present.Though such sign indicating number has a good error correcting capability when long code, yet because code character is long, and the scrambling of generator matrix and check matrix makes coding too complicated and be difficult to hardware and realize that such code word is fit to theoretical research and emulation is compared; The structure construction method comprises building methods such as how much, algebraical sum Combination Design; Most of LDPC constructive codes have circulation or accurate loop structure; Quasi-cyclic code (QC-LDPC) has very strong error correcting capability when middle short code; Performance is near the optimal L DPC sign indicating number of random configuration, and is extremely simple because of its hardware realization again, so all adopts the quasi-cyclic code with ad hoc structure in the existing standard.

The LDPC sign indicating number is a kind of sparse linear block codes, but different with the general linear block code, and the LDPC sign indicating number uses check matrix H to represent usually, and its corresponding common right and wrong of generator matrix G are sparse, and therefore, encoder complexity is higher.In order to reduce encoder complexity, Richardson and Urbanke have proposed a kind of efficient coding method based on the near lower triangular battle array (being called for short the RU algorithm), and its H matrix has near lower triangular structure, directly uses the H matrix to encode.In addition; The another kind that proposes based on lower triangular structure has the B-LDPC sign indicating number of biconjugate corner structure, and this code word can be used RU algorithm fast coding, and complexity is lower; And performance is in close proximity to the code word of equal length random configuration, used the code word of this structure among the 802.16e.

Summary of the invention

Technical problem to be solved by this invention provides a kind of coding method with quasi-cyclic LDPC code that the fastest speed and throughput are arranged.

The technical solution adopted for the present invention to solve the technical problems is: a kind of coding method of quasi-cyclic LDPC code is provided, comprises the following steps:

(1) input code and sparse matrix A multiply each other and obtain the first vector f ₁, input code and Matrix C multiply each other and obtain the second vector f ₂With the first vector f ₁With the second vector f ₂Be stored in the first flowing water register;

The first vector f in (2) the first flowing water registers ₁Obtain the 3rd vector f with the sparse matrix T at biconjugate angle through the forward direction displacement ₃f ₃Multiply each other with matrix E and to obtain four-vector f ₄

The second vector f in (3) the first flowing water registers ₂With four-vector f ₄Obtain the first encoder output verification position P through vector addition ₁

(4) first encoder output verification position P ₁Multiply each other with matrix B and to obtain the 5th vector f ₅

(5) first vector f ₁With the 5th vector f ₅Obtain the 6th vector f through vector addition ₆

(6) the 6th vector f ₆Obtain the second encoder output verification position P with the sparse matrix T at biconjugate angle through the forward direction displacement ₂

(7) the described second encoder output verification position P ₂Be stored in the second flowing water register; According to the demand output of will encoding.

Described matrix multiple adopts barrel shifter, will make full use of the sparse property of check matrix simultaneously.

During described matrix multiple, encoder is by the row executed in parallel; Non-0 element of in the check matrix each all is stored in one 12 the register in row and separately; The 0th to the 6th of register totally 7 cyclic shift value that is used for storing in the check matrix, the 7th to the 11st totally 5 row that are used for storing non-0 element place row in the check matrix number.

Described encoder is by the row executed in parallel; When carrying out matrix delegation and information bit multiplication; Non-0 element and information bit in this delegation of executed in parallel multiply each other, and comprising: at first utilize high 5 of register to select corresponding vector in the information bit, be input to it in the barrel shifter afterwards; Through low 7 the control displacement figure places in the register, non-0 element and information bit multiplication operations have just been accomplished once; Do once ' XOR ' operation to all non-0 elements in this delegation and the information bit gained result that multiplies each other then, so just accomplished matrix delegation and information bit and multiplied each other; In the encoder matrix multiplication capable and the row between be executed in parallel.

Described encoder has adopted a kind of coding ' XOR ' tree method.

Beneficial effect

The present invention is through the structure of the check matrix of analysis quasi-cyclic LDPC code; Provided a kind of method of fast coding; On this basis, make full use of the sparse and structurized characteristic of check matrix, designed the hardware implementation structure of the parallel pipelining process of this encryption algorithm.The present invention makes full use of the method for executed in parallel and hardware flowing water, makes encoder that the fastest speed and throughput arranged.

Description of drawings

Fig. 1 is the overall construction drawing of hardware coder of the present invention.

Fig. 2 is a matrix multiplication structure chart of the present invention.

Fig. 3 is the non-0 element storage format sketch map of check matrix of the present invention.

Fig. 4 is a n=8 of the present invention position barrel shifter structure chart.

Fig. 5 is the present invention's XOR tree structure diagram of encoding.

Embodiment

Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiment only to be used to the present invention is described and be not used in the restriction scope of the present invention.Should be understood that in addition those skilled in the art can do various changes or modification to the present invention after the content of having read the present invention's instruction, these equivalent form of values fall within the application's appended claims institute restricted portion equally.

The inventive principle of foundation of the present invention is:

For the LDPC sign indicating number is carried out efficient coding, matrix H is divided into following form:

$H=\left[\begin{array}{ccc}A& B& T\\ C& D& E\end{array}\right]$

If coding output code word is x=[k, p ₁, p ₂], wherein k is the encoder enter code word, p ₁, p ₂Be encoder output verification position.Because the LDPC sign indicating number has

Hx ^T＝0 (1)

If $F=\left[\begin{array}{cc}I& 0\\ -{\mathrm{ET}}^{-1}& I\end{array}\right],$ Can get with multiply by F (1) formula both sides

$\left\{\begin{array}{c}{\mathrm{Ak}}^T+{\mathrm{Bp}}_1^T+{\mathrm{Tp}}_2^T=0\\ (-{\mathrm{ET}}^{-1}A+C)k^T+(-{\mathrm{ET}}^{-1}B+D)p_1^T=0\end{array}\right.$

Because QC-LDPC sign indicating number (ET ^-1B+D)=1 always set up, separating above matrix equation can get

$p_1^T=({\mathrm{ET}}^{-1}A+C)k^T$

$p_2^T=T^{-1}({\mathrm{Ak}}^T+{\mathrm{Bp}}_1^T)$

Can be divided into following 6 steps to coding by above two formulas:

(1) calculates f ₁=Ak ^TAnd f ₂=Ck ^T

(2) calculate f ₃=T ^-1f ₁And f ₄=Ef ₃

(3) calculate p ₁=f ₄+ f ₂

(4) calculate $f_5={\mathrm{Bp}}_1^T;$

(5) calculate f ₆=f ₁+ f ₅

(6) calculate p ₂=T ^-1f ₆

Can know that by above-mentioned analysis the amount of calculation of LDPC encryption algorithm mainly is to calculate f ₁=Ak ^T, and A to be element in sparse matrix and the matrix be not 0 is exactly the matrix after the unit matrix circulation, so f ₁=Ak ^TCan be through k with correspondence ^TCyclic shift obtains, and computation complexity and code length are linear.f ₂, f ₅Can use the same method and obtain.Illustrate:

Formula (3) left side is two quadravalence unit matrixs sparse matrixes of constituting of right shifts 1 and 3 respectively, if 1011 move to left one must 0111,0101 move to left 3 1010, can get identical result 1101 to 0111 and 1010 XORs again

$\left[\begin{array}{cccccccc}0& 1& 0& 0& 0& 0& 0& 1\\ 0& 0& 1& 0& 1& 0& 0& 0\\ 0& 0& 0& 1& 0& 1& 0& 0\\ 1& 0& 0& 0& 0& 0& 1& 0\end{array}\right]\left[\begin{array}{c}1\\ 0\\ 1\\ 1\\ 0\\ 1\\ 0\\ 1\end{array}\right]=\left[\begin{array}{c}1\\ 1\\ 0\\ 1\end{array}\right]---\left(3\right)$

For calculating f ₃=T ^-1f ₁And p ₂=T ^-1f ₆, this paper adopts the forward direction method of replacement to obtain, below to calculate f ₃=T ^-1f ₁Be example derivation computational methods (note deriving is to binary system).

If f ₃=(u ₁, u ₂..., u ₂₉), f ₁=(v ₁, v ₂..., v ₂₉), the LDPC code check matrix T among the Yin Benwen is two diagonal matrixs, then has:

$f_3=T^{-1}{f}_1\&DoubleRightArrow;{\mathrm{Tf}}_3=f_1\&DoubleRightArrow;\left\{\begin{array}{c}{u}_1=v_1\\ u_1+{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="HDA0000096461330000022.png"\; state="\{\{state\}\}">u</figure-callout>}}_2=v_2\\ u_2+u_3=v_3\\ .\\ .\\ .\\ u_{28}+u_{29}=v_{29}\end{array}\right.\&DoubleRightArrow;\left\{\begin{array}{c}{u}_1=v_1\\ u_2=v_2+v_1\\ u_3=v_3+v_2+v_1\\ .\\ .\\ .\\ u_{29}=v_{29}+...+v_3+{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HDA0000096461330000022.png"\; state="\{\{state\}\}">v</figure-callout>}}_2+v_1\end{array}\right.$

Calculate f like this ₃=T ^-1f ₁And p ₂=T ^-1f ₆, on hardware, just can adopt " XOR gate " to realize.

Hardware coder should calculate p according to the step of front ₁And p ₂, in order to make encoder the fastest speed and throughput being arranged, the present invention has made full use of the method for executed in parallel and hardware flowing water.The general structure of hardware coder is as shown in Figure 1.

The function of several critical pieces of encoder is matrix multiplication (Matrix-Vector Multiplication; MVM), forward direction displacement (Forward-Substitution; FS), vector addition (Vector Addition; VA) and code word generate (Codeword Merge Generation, CWG), below main analysis matrix multiplication replace with forward direction.

Because the particularity of QC-LDPC code check matrix, matrix multiplication can use barrel shifter (barrel shifter) to realize, will make full use of the sparse property of check matrix simultaneously, to reduce amount of calculation.The structure of matrix multiplication is as shown in Figure 2.

When the compute matrix multiplication, encoder is by the row executed in parallel.Non-0 element of in the check matrix each all is stored in one 12 the register in row and separately, and its storage format is as shown in Figure 3.The 0th to the 6th of register totally 7 cyclic shift value that is used for storing in the check matrix, the 7th to the 11st totally 5 row that are used for storing non-0 element place row in the check matrix number.Because the check matrix of LDPC sign indicating number is a sparse matrix, major part all is 0 in the matrix, so storage matrix efficiently by this method.

Through such memory mechanism; When carrying out matrix delegation and information bit multiplication; Non-0 element and information bit in this delegation of executed in parallel multiply each other, and its process is: at first utilize high 5 of register to select corresponding vector in the information bit, be input to it in the barrel shifter afterwards; Through low 7 the control displacement figure places in the register, non-0 element and information bit multiplication operations have just been accomplished once; Do once ' XOR ' operation (being vector addition VA) to all non-0 elements in this delegation and the information bit gained result that multiplies each other then, so just accomplished matrix delegation and information bit and multiplied each other.In the encoder matrix multiplication capable and the row between be executed in parallel.

Fig. 4 is a n=8 position barrel shifter structure, and the barrel shifter of n=128 also has identical structure, but the progression of the shift unit of n=128 is 7 grades.

Consider equality f ₃=T ^-1f ₁, wherein, T is the sparse matrix at biconjugate angle, f ₃And f ₁Be vector.If f ₃=(u ₁, u ₂..., u ₂₉), f ₁=(v ₁, v ₂..., v ₂₉), a kind of more direct method that addresses this problem is to ask the inverse of a matrix matrix earlier, calculates then.But the inverse of a matrix computing is very complex calculations, need a large amount of processing times, and finding the inverse matrix has destroyed the sparse property of matrix.

The algorithm that the forward direction that the present invention adopts the front to propose is replaced, calculating only needs ' XOR ' operation just can realize, as shown in the formula:

$\left\{\begin{array}{c}{u}_1=v_1\\ u_2=v_2+v_1\\ u_3=v_3+v_2+v_1\\ .\\ .\\ .\\ u_{29}=v_{29}+...+v_3+v_2+v_1\end{array}\right.$

But, directly do not use ' XOR ' door to realize if do not improve, will introduce 28 * T _{2input_xor}Time-delay, T wherein _{2input_xor}Be the arithmetic time delay of two input XOR gates, and all there be (vector addition also is that ' XOR ' door is realized) in this time-delay in the two-stage of streamline, this will greatly influence the speed of whole encoder.After tested, the time-delay of forward direction replacement operator and vector addition computing introducing accounts for 56.54% of total time-delay.This encoder has adopted a kind of coding ' XOR ' tree, makes the time-delay that realizes have only 5 * T _{2input_xor}Fig. 5 is the structure chart of 8 bit vector forward direction iteration.

For code length is 7680 LDPC sign indicating number, checks that comprehensive report comprehensively can find, adopt the design of this coding XOR tree can make the time-delay of forward direction replacement operator reduce 82.14%, but area has but increased about 5 times.For high-speed applications, the cost of this area is an acceptable.

Calculate p ₂=T ^-1f ₆With calculating f ₃=T ^-1f ₁Adopt and use the same method.

Claims (5)

1. the coding method of a quasi-cyclic LDPC code is characterized in that, comprises the following steps:

(1) input code and sparse matrix A multiply each other and obtain the first vector f ₁, input code and Matrix C multiply each other and obtain the second vector f ₂With the first vector f ₁With the second vector f ₂Be stored in the first flowing water register;

The first vector f in (2) the first flowing water registers ₁Obtain the 3rd vector f with the sparse matrix T at biconjugate angle through the forward direction displacement ₃f ₃Multiply each other with matrix E and to obtain four-vector f ₄

The second vector f in (3) the first flowing water registers ₂With four-vector f ₄Obtain the first encoder output verification position P through vector addition ₁

(4) first encoder output verification position P ₁Multiply each other with matrix B and to obtain the 5th vector f ₅

(5) first vector f ₁With the 5th vector f ₅Obtain the 6th vector f through vector addition ₆

(6) the 6th vector f ₆Obtain the second encoder output verification position P with the sparse matrix T at biconjugate angle through the forward direction displacement ₂

(7) the described second encoder output verification position P ₂Be stored in the second flowing water register; According to the demand output of will encoding.

2. the coding method of a kind of quasi-cyclic LDPC code according to claim 1 is characterized in that: described matrix multiple adopts barrel shifter, will make full use of the sparse property of check matrix simultaneously.

3. the coding method of a kind of quasi-cyclic LDPC code according to claim 2 is characterized in that: during described matrix multiple, encoder is by the row executed in parallel; Non-0 element of in the check matrix each all is stored in one 12 the register in row and separately; The 0th to the 6th of register totally 7 cyclic shift value that is used for storing in the check matrix, the 7th to the 11st totally 5 row that are used for storing non-0 element place row in the check matrix number.

4. the coding method of a kind of quasi-cyclic LDPC code according to claim 3; It is characterized in that: described encoder is by the row executed in parallel; When carrying out matrix delegation and information bit multiplication; Non-0 element and information bit in this delegation of executed in parallel multiply each other, and comprising: at first utilize high 5 of register to select corresponding vector in the information bit, be input to it in the barrel shifter afterwards; Through low 7 the control displacement figure places in the register, non-0 element and information bit multiplication operations have just been accomplished once; Do once ' XOR ' operation to all non-0 elements in this delegation and the information bit gained result that multiplies each other then, so just accomplished matrix delegation and information bit and multiplied each other; In the encoder matrix multiplication capable and the row between be executed in parallel.

5. the coding method of a kind of quasi-cyclic LDPC code according to claim 1 is characterized in that: described encoder has adopted a kind of coding ' XOR ' tree method.

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