CN100557983C - A kind of quasi-cyclic low-density parity check codes encoder and check digit generation method - Google Patents

Abstract

The invention discloses a kind of quasi-cyclic low-density parity check codes encoder and check digit generation method, belong to the digital information technology field.Described encoder comprises: serial, encoder matrix memory cell, information bit buffer unit, core encoder unit and parallel/serial converting unit; Described method comprises: the information bit and the encoder matrix position of parallel input predetermined width; Parallel information position and parallel encoding matrix position to input calculate parallel check digit.The present invention is by the parallel input with information bit, the check digit generation method of check digit and line output is applied to the quasi-cyclic low-density parity check codes coding, can improve coding rate and save coding resource, and be easy between coding resource and coding rate, obtain compromise.

Description

A kind of quasi-cyclic low-density parity check codes encoder and check digit generation method

Technical field

The present invention relates to the digital information technology field, particularly quasi-circulating low-density parity check (Quasi-cyclic LowDensity Parity Check, QC-LDPC) code coder and check digit generation method.

Background technology

In recent years, because its excellent performance and structure that can parallel decoding (being convenient to realize high-speed coding), (Low Density Parity Check, LDPC) sign indicating number has been subjected to extensive concern to low-density checksum.

The LDPC sign indicating number is proposed by Gallager at first, referring to (R.G.Gallager, Low-Density Parity-Check Codes.Cambridge, MA:MIT.Press, 1963), along with the further investigation of people to Turbo code, D.J.C.Mackay, people such as M.Neal and N.Wiberg newly studies the LDPC code weight, referring to (MaCKay D J C.Good Error CorrectingCodes Based on Very Sparse Matrices.IEEE Trans on Information Theory, 1999,45 (2): 399-431.) find that it equally with Turbo code can well approach shannon limit, and cost is far smaller than Turbo code, thereby the LDPC sign indicating number causes people's strong interest once again.The outstanding performance of LDPC sign indicating number is not only the research focus of academia, also begins to be widely used in industrial quarters.At present in some standards, as DVB-S2, IEEE802.16e, and in the China Digital TV terrestrial broadcasting standard, all adopted the LDPC sign indicating number.

The LDPC sign indicating number has sparse parity matrix, therefore is convenient to realize parallel decoding, but in general, the encoder matrix of LDPC sign indicating number is not sparse, especially the sign indicating number of LDPC at random that comes out of computer search, owing to there are not enough architectural characteristics, coding is complicated and consume a large amount of memory cell.Quasi-cyclic LDPC (QC-LDPC) sign indicating number is the LDPC sign indicating number that a class has a fixed structure.The LDPC sign indicating number is suitable at random for rule that the performance of good QC-LDPC sign indicating number and computer generate or non-rule, referring to (L.Chen, J.Xu, I.Djurdjevic, and S.Lin, " Near-Shannon-limit quasicyclic low-density parity-check codes; " IEEETrans.Commun., vol.52, no.7, pp.1038-1042, Jul.2004.).The QC-LDPC sign indicating number can use simple shift register to finish coding in linearity in the time of check digit length, therefore in the practical application, the QC-LDPC sign indicating number has very strong competitiveness, and as the employing of China Digital TV broadcasting ground transmission standard is exactly the QC-LDPC sign indicating number.

Based on SRAA (Shift-Register-Adder-Accumulator, being shifted-deposit-add up) the QC-LDPC encoding scheme of circuit is the representative encoding scheme of a class, referring to (Zongwang Li, Lei Chen, Lingqi Zeng, Shu Lin, and Wai H.Fong, Efficient Encoding of Quasi-Cyclic Low-Density Parity-Check Codes, IEEETrans.on Commun, vol.54, no.1, Jan 2006.), wherein, utilize the accurate cycle characteristics of QC-LDPC generator matrix, delegation or row with the register-stored generator matrix calculate check digit by cyclic shift and combinational circuit; Simultaneously, provided two kinds of encoding schemes in the document, be called SIPO (Serial Input Parallel Output) and PISO (Parallel Input Serial Output) scheme based on the SRAA circuit.Simply introduce these two kinds two kinds of coding structures based on the SRAA circuit below respectively, at first, establishing QC-LDPC is the systematic code form, is made of encoder matrix G the circular matrix of c * t b * b size _QcBe shown below, wherein, I is the unit matrix of b * b, the 0th, and 0 matrix of b * b, G _{I, j}(1≤i≤t-c, 1≤j≤c) is the circular matrix of b * b.

Perhaps

Referring to Fig. 1, the SRAA principle in the SIPO scheme is as follows:

The first step, register B storage $g_{}^{}$ ${}_{1,j}^{\left(0\right)}={\mathrm{<figure-callout\; id="1"\; label="g"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">g</figure-callout>}}_{1,j}$ (g _{1, j}Be G _{1, j}First the row), register A is changed to 0.

Second step, information bit a ₁Input is exported a that obtains with door ₁g _{1, j} ⁽⁰⁾Obtain a with complete 0 XOR ₁g _{1, j} ⁽⁰⁾Deposit register A in.

In the 3rd step, one of the encoder matrix ring shift right among the B obtains g _{1, j} ⁽¹⁾, work as a ₂After the input, with a of door output ₂g _{1, j} ⁽¹⁾With a among the A ₁g _{1, j} ⁽⁰⁾Addition obtains a ₁g _{1, j} ⁽⁰⁾+ a ₂g _{1, j} ⁽¹⁾And be stored in register A.

Aforesaid operations repeats, as information bit a _bAfter the input, register A has obtained

Wherein ${\stackrel{\&RightArrow;}{a}}_1=(a_1,a_2,...,a_b).$ At this moment G _{2, j}First the row g _{2, j}Deposited in register B, information bit a _B+1Input continues aforesaid operations, works as a _2bAfter having imported, that stores among the A is

Wherein ${\stackrel{\&RightArrow;}{a}}_1=(a_1,a_2,...,a_b),$ ${\stackrel{\&RightArrow;}{a}}_2=(a_{b+1},a_{b+2},...,a_{2b}).$

Above-mentioned displacement, add up, deposit the operation proceed, after all information bits all moved into encoder, what store among the register A was exactly the check digit of b bit.

Referring to Fig. 2, the SRAA principle in the PISO scheme in SRAA principle and the SIPO scheme is similar, and that the difference part is to store among the register B is h _{I, j} ^(l)(h _{I, j} ^(l)Be G _{I, j}L cyclic shift of first row), the parallel input of information bit, a check bit is exported in t-c serial of every circulation.If all information are parallel simultaneously input, the register that is used to store the 1bit check digit can omit.

If an actual coding device has only SRAA coding circuit in the SIPO scheme, need then that b * c * (t-c) the individual clock cycle just can be finished coding, this moment, the core encoder circuit needed b two inputs and door, b two input XOR gate and 2b registers (no specified otherwise, register all refer to a bit register).If have only a SRAA circuit in the PISO scheme, need equally then that b * c * (t-c) the individual clock cycle just can be finished coding, this moment, the core encoder circuit needed b two inputs and door, b two input XOR gate and b+1 registers.In document " Efficient Encoding of Quasi-Cyclic Low-DensityParity-Check Codes ", proposed two kinds of encoding schemes and be used to improve coding rate based on SRAA, as follows respectively:

First kind of scheme (SIPO) is: use c SRAA circuit to work simultaneously, and information bit serial input, as shown in Figure 3, can be with b * (t-c) the individual clock cycle is finished coding, wherein ..., $\stackrel{\&RightArrow;}{{\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">P</figure-callout>}}_1}=({\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">p</figure-callout>}}_1,{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">p</figure-callout>}}_2,...,p_b),$ $\stackrel{\&RightArrow;}{{\mathrm{<figure-callout\; id="2"\; label="P"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">P</figure-callout>}}_2}=(p_{b+1},p_{b+2},...,p_{2b}),...,$ $\stackrel{\&RightArrow;}{P_c}=(p_{b\&times;(c-1)+1},p_{b\&times;(c-1)+2},...,p_{b\&times;c}).$

Second kind of scheme (PISO) is: use t-c SRAA circuit to work simultaneously, available b * c clock cycle is finished coding.These scheme characteristics are the parallel full input of information bit, check digit serial output, as shown in Figure 4.

Summary ginseng to SIPO scheme and PISO scheme is shown in Table 1.

Table 1

Encoding scheme	Coding rate (clock cycle)	Register	Two input XOR gate	Two inputs and door
					SIPO	(t-c)b	2cb	cb	cb
PISO	cb	(t-c)b	(t-c)b-1	(t-c)b

These the two kinds encoding schemes based on SRAA can satisfy the compromise of encoder speed and resource to a certain extent, but also there are the following problems:

1) limited coding rate to a certain extent;

2) the SIPO scheme needs very high encoder matrix and line output width, register is required high, and high operation speed is limited when adopting FPGA (FieldProgrammable Gate Array, field programmable gate array) to realize;

3) the PISO scheme needs the parallel simultaneously input of information bit, and this is difficult to realize in practice, because for the LDPC sign indicating number, and its code length and information bit often very long (several thousand even several ten thousand), high operation speed is limited equally when adopting FPGA to realize.

Summary of the invention

In order to improve the coding rate of QC-LDPC sign indicating number, reduce the coding resource of QC-LDPC sign indicating number, the invention provides a kind of quasi-cyclic low-density parity check codes encoder and check digit generation method.Described technical scheme is as follows:

A kind of quasi-cyclic low-density parity check codes encoder, described encoder comprises: serial, encoder matrix memory cell, information bit buffer unit, core encoder unit and parallel/serial converting unit; Wherein,

Described serial comprises an adaptive input-buffer unit, is used for buffer memory behind the parallel information position that information bit with serial input converts predetermined width to, and sends described core encoder unit to by the sequential requirement of core encoder unit;

Described information bit buffer unit is used to preserve the information bit of serial input, and requires serial to export described information bit according to the sequential of core encoder unit;

Described encoder matrix memory cell is used for the memory encoding matrix, and sends the encoder matrix parallel-by-bit of predetermined width to described core encoder unit;

Described core encoder unit is used to receive the parallel information position of described serial transmission and the parallel encoding matrix position that described encoder matrix memory cell transmits, by AND operation being carried out in described parallel information position and described parallel encoding matrix position step-by-step in each clock cycle, and the result of the described AND operation in each clock cycle carried out nonequivalence operation, calculate parallel check digit, send described parallel check digit to parallel/serial converting unit; Also be used to control the sequential of whole encoder;

Described parallel/serial converting unit comprises an adaptive output buffers unit, is used for the parallel check digit that described core encoder unit transmits is converted to buffer memory after the serial check digit, and requires serial output according to the sequential of core encoder unit.

The parallel information position bit wide of described core encoder unit input and the parallel check digit bit wide of output are regulated according to the requirement of coding rate and resource occupation, and the parallel encoding matrix position bit wide of described core encoder unit input is fixed.

The present invention also provides a kind of check digit generation method, and described method comprises:

Steps A: to the register zero clearing of the intermediate object program of the parallel check digit that is used for buffer memory;

Step B: the parallel information position and the encoder matrix position of transmitting predetermined width to the core encoder unit, described parallel information position is converted to by the information bit of serial input, and described encoder matrix position is obtained by the row or column of described core encoder unit by the combination selection encoder matrix;

Step C: the core encoder unit carries out AND operation to the parallel information position and the parallel encoding matrix position of input in each clock cycle step-by-step, and the result of the described AND operation in each clock cycle carried out distance, the intermediate object program step-by-step nonequivalence operation of the parallel check digit of result that computing obtains and core encoder unit caches, and in described register the new intermediate object program of buffer memory;

Step D: calculation times adds 1, judges whether described calculation times reaches preset times, if, obtain the final result of parallel check digit, send parallel/serial converting unit then to; Otherwise, return step B;

Step e: cycle-index adds 1, judges whether described cycle-index reaches default cycle-index, if all parallel check digit have all sent parallel/serial converting unit to, check digit generates and finishes; Otherwise, return steps A.

The bit wide of the parallel check digit that generates in the bit wide of the parallel information bit of the predetermined width among the described step B and the step e is regulated according to the requirement of coding rate and resource occupation.

The beneficial effect of technical scheme provided by the invention is:

The present invention is by the parallel input with information bit, and the coding structure of check digit and line output is applied to the quasi-cyclic low-density parity check codes coding, can improve coding rate and save coding resource, can guarantee to save resource on the basis of improving speed as far as possible.

Description of drawings

Fig. 1 is the SRAA coding circuit schematic diagram in the SIPO encoding scheme that provides of prior art;

Fig. 2 is the SRAA coding circuit schematic diagram in the PISO encoding scheme that provides of prior art;

Fig. 3 is the structural representation of the SIPO encoder that provides of prior art;

Fig. 4 is the structural representation of the PISO encoder that provides of prior art;

Fig. 5 is the structural representation of the quasi-cyclic low-density parity check codes encoder that provides of the embodiment of the invention 1;

Fig. 6 is that the check digit that the embodiment of the invention 2 provides generates method flow diagram.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.

The encoder applies QC-LDPC sign indicating number coding that the embodiment of the invention provides adopts the parallel input of information bit, and the mode of check digit and line output can improve coding rate and save coding resource.

Embodiment 1

Referring to Fig. 5, present embodiment provides a kind of quasi-cyclic low-density parity check codes coder structure, comprising: serial 101, information bit buffer unit 102, core encoder unit 103, encoder matrix memory cell 104 and parallel/serial converting unit 105; Wherein,

Serial 101 is used for the information bit of serial input is converted to parallel information bit, and in each clock cycle under the sequencing control of core encoder unit 103 with the parallel core encoder unit 103 of exporting to of the information bit of predetermined width; The width of the parallel information position of each output is flexible configuration as required, it comprises an adaptive buffer unit, be used for buffer memory behind the parallel information position that information bit with serial input converts predetermined width to, and send described core encoder unit to by the sequential requirement of core encoder unit;

Information bit buffer unit 102 is used for the information bit of buffer memory serial input, and finishes the sequential requirement of back according to core encoder unit 103 at core encoder, the serial check digit serial output successively together that obtains with parallel/serial converting unit 105; This information bit buffer unit 102 can be arranged on serial 101 the insides, also can be arranged on the outside of serial 101.

Encoder matrix memory cell 104 is used for the memory encoding matrix, and sends the encoder matrix parallel-by-bit of predetermined width to core encoder unit 103;

Core encoder unit 103 is used for digitwise operation is carried out in the parallel encoding matrix position of the parallel information position of serial 101 inputs and 104 inputs of encoder matrix memory cell, obtain parallel check digit and export to parallel/serial converting unit 105, and control whole encoder sequential;

Parallel/serial converting unit 105 is used for the parallel check digit of described core encoder unit input is converted to the serial check digit, and under the sequencing control of core encoder unit 103, the serial check bit sum is stored in the serial information position serial output successively of information bit buffer unit 102, it comprises an adaptive output buffers unit, be used for the parallel check digit that described core encoder unit transmits is converted to buffer memory after the serial check digit, and require serial output according to the sequential of core encoder unit;

The bit wide of the parallel input of information bit and check digit and line output can flexible configuration, when the width of present embodiment encoder matrix loop blocks is the b position, then the bit wide of the parallel input of encoder matrix is the b position, and preference information parallel-by-bit input simultaneously and the parallel output of check digit bit wide also are the b position.

The encoder matrix of memory cell 102 storages is a QC-LDPC sign indicating number encoder matrix, is made of encoder matrix G the circular matrix of c * t b * b size _QcAs the formula (1):

Perhaps

Code length t * b, wherein, long (the t-c) * b of information bit, the long c * b of check digit.Information bit in the present embodiment is $\stackrel{\&RightArrow;}{a}=(\stackrel{\&RightArrow;}{a_1},\stackrel{\&RightArrow;}{a_2},...,\stackrel{\&RightArrow;}{a_{t-c}}),$ Wherein $\stackrel{\&RightArrow;}{a_i}=(a_{(i-1)\&times;b+1},a_{(i-1)\&times;b+2},...,a_{i\&times;b}),(1\&le;i\&le;t-c),$ That is: will Be divided into the t-c piece, every block length is b.Check digit is $\stackrel{\&RightArrow;}{p}=(\stackrel{\&RightArrow;}{{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">p</figure-callout>}}_1},\stackrel{\&RightArrow;}{{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">p</figure-callout>}}_2},...,\stackrel{\&RightArrow;}{p_c}),$ Wherein, $\stackrel{\&RightArrow;}{p_j}=(p_{(j-1)\&times;b+1},p_{(j-1)\&times;b+2},...,p_{j\&times;b}),(1\&le;j\&le;c).$

Order:

Then:

Promptly

$\stackrel{\&RightArrow;}{p_j}=(\stackrel{\&RightArrow;}{a_1},\stackrel{\&RightArrow;}{a_2},...,\stackrel{\&RightArrow;}{a_{t-c}})\&times;\left[\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="G"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">G</figure-callout>}}_{1,\mathrm{<figure-callout\; id="2"\; label="j\; G"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">j</figure-callout>}}& \\ G_{}{}_{2,j}\\ .\\ .\\ .\\ G_{t-c,j}\end{array}\right]=\stackrel{\&RightArrow;}{a_1}{\mathrm{<figure-callout\; id="1"\; label="G"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">G</figure-callout>}}_{1,j}+\stackrel{\&RightArrow;}{a_2}{\mathrm{<figure-callout\; id="2"\; label="G"\; filenames="C20071017616100131.png,C20071017616100132.png"\; state="\{\{state\}\}">G</figure-callout>}}_{2,j}+...+\stackrel{\&RightArrow;}{a_{t-c}}{G}_{t-c,j}---\left(3\right)$

Wherein, $G_{i,j}=\left[\begin{array}{c}{g}_{i,j}\\ g_{i,j}^{\left(1\right)}\\ .\\ .\\ .\\ g_{i,j}^{(b-1)}\end{array}\right]=[h_{i,j},h_{i,j}^{\left(1\right)},...,h_{i,j}^{(b-1)}]$ Be circular matrix, g _{I, j}(row vector) is its first row, $g_{i,j}^{\left(l\right)}(1\&le;l\&le;b-1)$ Be g _{I, j}L position cyclic shift, h _{I, j}(column vector) is its first row, $h_{i,j}^{\left(l\right)}(1\&le;l\&le;b-1)$ Be h _{I, j}L position cyclic shift.

According to (3) formula, can be by parallel input information position

And encoder matrix submatrix G _{I, j}First the row g _{I, j}Or first row h _{I, j}, each clock cycle can obtain

And obtain in each clock cycle of adding up

Obtain the also check digit of line output by adding up of t-c clock cycle

Embodiment 2

Utilize the core encoder unit 103 in the encoder that embodiment 1 provides, present embodiment provides a kind of check digit generation method, and referring to Fig. 6, concrete generative process is as follows:

Step 201: to preserving the register P zero clearing of check digit (b position) intermediate object program.

Step 202: to 103 parallel input information positions, core encoder unit $\stackrel{\&RightArrow;}{a_i}=(a_{(i-1)\&times;b+1},a_{(i-1)\&times;b+2},...,a_{i\&times;b}),(1\&le;i\&le;t-c),$ The capable g of parallel input coding matrix _{I, j}Perhaps be listed as h _{I, j}

Step 203: core encoder unit 103 obtains G by combination selection _{I, j}(1≤i≤t-c, 1≤j≤c), by step-by-step " with " and distance calculate And with register P step-by-step XOR, the result is added up in register P.

Step 204: calculation times i adds 1, and its initial value is 0.

Step 205: judge whether calculation times i reaches t-c time, if, execution in step 206; Otherwise, execution in step 202.

206:t-c cycle calculations late register of step P obtains check digit

Will

Export to parallel/serial converting unit 105.

Step 207: cycle-index j adds 1, and wherein, the initial value of cycle-index j is 0.

Step 208: judge whether cycle-index j reaches c, if check digit generates and finishes; Otherwise return step 201.

After core encoder unit 103 generates check digit, walk abreast and export to parallel/serial converting unit 105, information bit buffer unit 102 and parallel/serial converting unit 105 are under the sequencing control of core encoder unit, and output serial information position and serial check digit are finished cataloged procedure.

Parameter in the present embodiment is identical with embodiment 1, repeats no more here.

The encoding scheme that embodiment 1 and embodiment 2 provide is called PIPO (Parallel Input Parallel Output; parallel input and line output) encoding scheme; contrast common SIPO and PISO encoding scheme based on SRAA; discuss under same-code speed below; the resources advantage of the embodiment of the invention, simple for describing, establish c=t-c=b; SIPO based on SRAA of the prior art has identical coding rate with the PISO scheme with embodiment of the invention PIPO scheme, is analyzed as follows:

1. resource consumption analysis

Based on the SIPO scheme of SRAA, need the register of the individual b of b (c=b) position, be used for the memory encoding matrix, b b bit register is used to store check digit, altogether 2b ²Individual register.b ²Individual two inputs and door (and essential the input with door with two realized), b ²Individual two input XOR gate (and essential) with two input XOR gate realizations.

Based on the PISO scheme of SRAA, need b b bit register to be used for the memory encoding matrix, altogether b ²Individual register.b ²Individual two inputs and door and b ²-1 two input XOR gate.

The PIPO scheme that the embodiment of the invention provides needs 1 b bit register to be used to preserve check digit, is total to b register, b ²Individual two inputs and door and b ²Individual two input XOR gate.If c=t-c=b, the comparison of SIPO, PISO and PIPO scheme resource is referring to table 2 under the same coding rate.

Table 2

Encoding scheme	Register	Two input XOR gate	Two inputs and door
				SIPO	2b 2	b 2	b 2
PISO	b 2	b 2-1	b 2
				PIPO	b	b 2	b 2

Wherein, the XOR among the SIPO must adopt the XOR gate of two inputs, and can adopt the XOR gate of many inputs in PISO and the PIPO scheme, and hardware more has superiority on realizing; The PIPO scheme can significantly reduce the requirement to register simultaneously.

2. the experimental result of resource consumption

On quartus II platform,, and test on the device Stratix IIEP2S90F1020C5 respectively at device Stratix EP1S80F1508C7.In the experiment, set c=t-c=b=16, resource (logical block and register) consumes the result shown in table 3 and table 4 under the same coding rate, and wherein, table 3 is the resource consumption on the 1S80, and table 4 is the resource consumption of 2S90:

Table 3

	SIPO	PISO	PIPO
				logic cells	512	427	176
lc registers	512	256	16

Table 4

Experimental result shows that under identical coding rate, SIPO scheme consumption of natural resource is maximum, and this programme PIPO consumption of natural resource is minimum, and PISO is mediate, and coincide with analysis.

3. the experimental result of clock speed

Simultaneously, watch 5 is depicted as each encoder of obtaining in the experiment the fastest clock speed on FPGA.Experimental result shows that clock speed of this programme and PISO scheme are fast equally.

Table 5

	SIPO	PISO	PIPO
				1S80	259.81MHz	390.02MHz	390.02MHz
2S90	230.36MHz	400MHz	400MHz

Be 16 * 16 only above, and the QC-LDPC sign indicating number of c=t-c=b=16 has carried out preliminary experiment to the loop blocks size.In the reality, b is often much bigger than c or t-c, such as the QC-LDPC sign indicating number in Chinese terrestrial DTV standard three kinds of code checks is arranged, and is respectively a little 4 code checks (7493,3048), point 6 code checks (7493,4572), and put 8 code checks (7493,6096), these three kinds of code check b=127, t=59 is so t-c is respectively 24,36 and 48.So the fastest coding rate of SIPO and PISO scheme can't reach the fastest coding rate of this programme.In addition, because the PISO scheme requires the parallel simultaneously input of all information bits, if information bit is very long, experiment finds that the support of FPGA is also bad, and supports finely to the encoding scheme of the embodiment of the invention.

Above analysis result shows that the PIPO encoding scheme that the embodiment of the invention provides is compared with the SRAA scheme, can save the consumption of resource under same-code speed greatly, or can improve coding rate greatly under same asset consumption; Simultaneously, reach very high coding rate easily, be convenient to hardware and realize and hardware optimization; Be more suitable for high speed QC-LDPC coding.

The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (4)

1. a quasi-cyclic low-density parity check codes encoder is characterized in that, described encoder comprises: serial, encoder matrix memory cell, information bit buffer unit, core encoder unit and parallel/serial converting unit; Wherein,

Described serial comprises an adaptive input-buffer unit, is used for buffer memory behind the parallel information position that information bit with serial input converts predetermined width to, and sends described core encoder unit to by the sequential requirement of core encoder unit;

Described information bit buffer unit is used to preserve the information bit of serial input, and requires serial to export described information bit according to the sequential of core encoder unit;

Described encoder matrix memory cell is used for the memory encoding matrix, and sends the encoder matrix parallel-by-bit of predetermined width to described core encoder unit;

Described core encoder unit is used to receive the parallel information position of described serial transmission and the parallel encoding matrix position that described encoder matrix memory cell transmits, by AND operation being carried out in described parallel information position and described parallel encoding matrix position step-by-step in each clock cycle, and the result of the described AND operation in each clock cycle carried out nonequivalence operation, calculate parallel check digit, send described parallel check digit to parallel/serial converting unit; Also be used to control the sequential of whole encoder;

Described parallel/serial converting unit comprises an adaptive output buffers unit, is used for the parallel check digit that described core encoder unit transmits is converted to buffer memory after the serial check digit, and requires serial output according to the sequential of core encoder unit.

2. quasi-cyclic low-density parity check codes encoder as claimed in claim 1, it is characterized in that, the parallel information position bit wide of described core encoder unit input and the parallel check digit bit wide of output are regulated according to the requirement of coding rate and resource occupation, and the parallel encoding matrix position bit wide of described core encoder unit input is fixed.

3. a check digit generation method is characterized in that, described method comprises:

Steps A: to the register zero clearing of the intermediate object program of the parallel check digit that is used for buffer memory;

Step B: the parallel information position and the encoder matrix position of transmitting predetermined width to the core encoder unit, described parallel information position is converted to by the information bit of serial input, and described encoder matrix position is obtained by the row or column of described core encoder unit by the combination selection encoder matrix;

Step C: the core encoder unit carries out AND operation to the parallel information position and the parallel encoding matrix position of input in each clock cycle step-by-step, and the result of the described AND operation in each clock cycle carried out nonequivalence operation, the intermediate object program step-by-step nonequivalence operation of the parallel check digit of result who obtains and core encoder unit caches, and in described register the new intermediate object program of buffer memory;

Step D: calculation times adds 1, judges whether described calculation times reaches preset times, if, obtain the final result of parallel check digit, send parallel/serial converting unit then to; Otherwise, return step B;

Step e: cycle-index adds 1, judges whether described cycle-index reaches default cycle-index, if all parallel check digit have all sent parallel/serial converting unit to, check digit generates and finishes; Otherwise, return steps A.

4. check digit generation method as claimed in claim 3 is characterized in that, the bit wide of the parallel check digit that generates in the bit wide of the parallel information bit of the predetermined width among the described step B and the step e is regulated according to the requirement of coding rate and resource occupation.

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