CN101141132A - Quasi-circulation low density parity code encoder and check bit generating method - Google Patents
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Abstract
The invention discloses a quasi-cycle low density parity checking code encoder and the parity bit generating method and consists of a serial/parallel switch unit, an encoding matrix storage unit, an information bit cache unit, a core encoding unit and a serial/parallel switch unit; the method consists of: the information bit and the encoding matrix bit that is parallel input into the set width; the parallel parity bit is obtained by calculating the input parallel information and the parallel encoding matrix. The invention applies the parallel input of the information bit, the parity bit generating method of the parallel output of the parity bit into the quasi-cycle low density parity checking encoding to improve the encoding speed, save encoding source and is easy to meet half way between the encoding sources and the encoding speed.
Description
Technical Field
The invention relates to the technical field of digital information, in particular to a Quasi-cyclic Low Density Parity Check (QC-LDPC) code encoder and a Check bit generation method.
Background
In recent years, low Density Parity Check (LDPC) codes have received much attention due to their excellent performance and structure that can be decoded in parallel (facilitating high-speed decoding).
LDPC Codes were originally proposed by Gallager, see (R.G. Gallager, low-sensitivity Party-Check Codes, cambridge, MA: MIT.Press, 1963), and with the intensive research on Turbo Codes, D.J.C.Mackay, M.New, and N.Wiberg et al, re-studied LDPC Codes, see (Maxay D J.C.good Error Correcting Codes Based on Very spark matrix IEEE Trans on Information Theory,1999, 45 (2): 399-431.) and found to approach the Shannon limit as well as Turbo Codes and at a cost much less than Turbo Codes, so that LDPC code re-degree has attracted strong attention. The excellent performance of the LDPC code is not only a research focus in academia, but also begins to be applied to the industrial field in a large amount. At present, LDPC codes are adopted in some standards, such as DVB-S2, IEEE802.16e and China digital television terrestrial broadcasting standards.
The LDPC code has a sparse check matrix, and thus parallel decoding is convenient to implement, but generally, an encoding matrix of the LDPC code is not sparse, and particularly, a random LDPC code searched by a computer has a complex encoding and consumes a large number of memory cells due to insufficient structural characteristics. Quasi-cyclic LDPC (QC-LDPC) codes are a class of LDPC codes that have a certain structure. The performance of good QC-LDPC codes is comparable to computer-generated regular or irregular random LDPC codes, see (L.Chen, J.Xu, I.Djurdjjevic, and S.Lin, "Near-Shannon-limit qualification low-sensitivity parity-codes," IEEE transactions, vol.52, no.7, pp.1038-1042, jul.2004.). The QC-LDPC code can be coded in the time linear to the length of the check bit by using a simple shift register, so that the QC-LDPC code has strong competitiveness in practical application, such as the QC-LDPC code adopted by the terrestrial transmission standard of China digital television broadcasting.
Based on SRAA (Shift-Register-Adder) electricityThe QC-LDPC coding scheme is a representative class of coding schemes, see (ZongwangLi, leiChen, lingqiZeng, shuLin, and WaiH. Fong, efficientEncodingof Quasi-CyclicLow-DensityParty-CheckCodes, IEEETrans. OnCommun, vol.54, no.1, jan 2006), wherein a quasi-cyclic characteristic of a QC-LDPC generated matrix is utilized, a register is used for storing one row or one column of the generated matrix, and check bits are obtained through cyclic shift and calculation of a combination circuit; meanwhile, two encoding schemes based on SRAA circuits are given in this document, which are called SIPO (serialinputprealloutput) and PISO (ParallelInputSerialOutput) schemes. Firstly, a QC-LDPC is set as a system code format and consists of c multiplied by t circulant matrixes with the size of b multiplied by b, and a coding matrix G qc Wherein I is a b × b unit matrix, 0 is a b × b 0 matrix, and G is represented by i，j (1. Ltoreq. I.ltoreq.t-c, 1. Ltoreq. J.ltoreq.c) is a circulant matrix of b x b.
Referring to fig. 1, the SRAA principle in the sipo scheme is as follows:
in the first step, register B stores(g 1，j Is G 1，j First row) register a is set to 0.
Second step, information bit a 1 A obtained from input, AND gate output 1 g 1，j (0) XOR with all 0's to give a 1 g 1，j (0) And stored in register a.
Thirdly, circularly right shifting the coding matrix in B by one bit to obtain g 1，j (1) When a is 2 After input, output from AND gatea 2 g 1，j (1) And a in A 1 g 1，j (0) Add to obtain a 1 g 1，j (0) +a 2 g 1，j (1) And is stored in register a.
The above operation is repeated, and when the information bit ab is input, the register A is obtained
Wherein
At this time G 2，j First row g of 2，j Is stored in register B, information bit a b+1 Inputting, continuing the above operation when a 2b After the input is finished, the data stored in A is
Wherein
The shift, accumulate, and register operations continue, and when all the information bits are shifted into the encoder, the check bits of b bits are stored in the register a.
Referring to fig. 2, the SRAA principle in piso scheme is similar to that in SIPO scheme except that h is stored in register B i，j (l) (h i，j (l) Is G i，j L cyclic shifts of the first column) of information bits are input in parallel, one check bit is output serially t-c times per cycle. If all the information is input in parallel at the same time, the register for storing the 1-bit check bit can be omitted.
If an actual encoder only has an SRAA encoding circuit in the SIPO scheme, b × c × (t-c) clock cycles are needed to complete encoding, and at the moment, b two-input AND gates, b two-input XOR gates and 2b registers (no special description is provided, the registers refer to one-bit registers) are needed by a core encoding circuit. If only one SRAA circuit in PISO scheme is needed, b × c × (t-c) clock cycles are needed to complete the encoding, and at this time, b two-input and gates, b two-input xor gates and b +1 registers are needed for the core encoding circuit. In the document "Efficient Encoding of quick-Cyclic Low-sensitivity Parity-Check Codes", two Encoding schemes based on SRAA are proposed for increasing the Encoding speed, as follows:
the first Scheme (SIPO) is: using c SRAA circuits operating simultaneously, the information bits are input serially, as shown in FIG. 3, and may be encoded in b (t-c) clock cycles, where
The second scheme (PISO) is: with t-c SRAA circuits operating simultaneously, the encoding can be done in b x c clock cycles. The scheme features full parallel input of information bits and serial output of check bits, as shown in fig. 4.
A summary of the SIPO and PISO protocols is shown in table 1.
TABLE 1
| Coding scheme | Coding speed (clock period) | Register with a plurality of registers | Two-input exclusive-OR gate | Two-input AND gate |
| SIPO | (t-c)b | 2cb | cb | cb |
| PISO | cb | (t-c)b | (t-c)b-1 | (t-c)b |
The two encoding schemes based on SRAA can satisfy the trade-off of encoder speed and resources to some extent, but there are the following problems:
1) The coding speed is limited to a certain extent;
2) The SIPO scheme requires a very high parallel output width of a coding matrix, has a high requirement on a register, and is limited in the highest working speed when implemented by using an FPGA (Field Programmable Gate Array);
3) The PISO scheme requires simultaneous and parallel input of information bits, which is difficult to implement in practice because for LDPC codes, the code length and the information bits are often very long (thousands or even tens of thousands), and the highest operating speed is also limited when the FPGA is used for implementation.
Disclosure of Invention
In order to improve the encoding speed of the QC-LDPC code and reduce the encoding resources of the QC-LDPC code, the invention provides a quasi-cyclic low-density parity check code encoder and a check bit generation method. The technical scheme is as follows:
a quasi-cyclic low density parity check code encoder, the encoder comprising: the device comprises a serial/parallel conversion unit, a coding matrix storage unit, an information bit cache unit, a core coding unit and a parallel/serial conversion unit; wherein the content of the first and second substances,
the serial/parallel conversion unit comprises an adaptive input buffer unit which is used for converting the serially input information bits into parallel information bits with preset width, then buffering the parallel information bits and transmitting the parallel information bits to the core coding unit according to the time sequence requirement of the core coding unit;
the information bit cache unit is used for storing serially input information bits and serially outputting the information bits according to the time sequence requirement of the core coding unit;
the coding matrix storage unit is used for storing a coding matrix and transmitting coding matrix bits with preset width to the core coding unit in parallel;
the core coding unit is used for receiving the parallel information bits transmitted by the serial/parallel conversion unit and the parallel coding matrix bits transmitted by the coding matrix storage unit, calculating to obtain parallel check bits, and transmitting the parallel check bits to the parallel/serial conversion unit; and is also used to control the timing of the entire encoder;
the parallel/serial conversion unit comprises an adaptive output buffer unit which is used for converting the parallel check bit transmitted by the core coding unit into a serial check bit and then buffering the serial check bit, and serially outputting the serial check bit according to the time sequence requirement of the core coding unit.
The bit width of the parallel information bit input by the core coding unit and the bit width of the output parallel check bit are adjusted according to the coding speed and the requirement of resource occupation, and the bit width of the parallel coding matrix bit input by the core coding unit is fixed.
The invention also provides a check bit generation method, which comprises the following steps:
step A: resetting a register for intermediate results of the cached parallel check bits;
and B: transmitting parallel information bits and coding matrix bits with preset widths to a core coding unit;
and C: the core coding unit carries out bitwise AND and XOR operation on the input parallel information bit and the parallel coding matrix bit, the obtained result and an intermediate result of the parallel check bit cached by the core coding unit are subjected to bitwise XOR operation, and the intermediate result is cached in the register;
step D: adding 1 to the calculation times, judging whether the calculation times reach preset times, if so, obtaining a final result of the parallel check bits, and then transmitting the final result to a parallel/serial conversion unit; otherwise, returning to the step B;
step E: adding 1 to the cycle times, judging whether the cycle times reach the preset cycle times, if so, transmitting all the parallel check bits to the parallel/serial conversion unit, and finishing the check bit generation; otherwise, returning to the step A.
And B, the bit width of the parallel information bits with the preset width in the step B and the bit width of the parallel check bits generated in the step E are adjusted according to the requirements of the coding speed and the resource occupation.
The technical scheme provided by the invention has the beneficial effects that:
the coding structure of parallel input of information bits and parallel output of check bits is applied to the coding of the quasi-cyclic low-density parity check code, so that the coding speed can be increased, coding resources can be saved, and the resources can be saved as much as possible on the basis of increasing the speed.
Drawings
Fig. 1 is a schematic diagram of an SRAA encoding circuit in a SIPO encoding scheme provided by the prior art;
FIG. 2 is a schematic diagram of an SRAA encoding circuit in a PISO encoding scheme provided by the prior art;
fig. 3 is a schematic structural diagram of a SIPO encoder provided in the prior art;
FIG. 4 is a schematic diagram of a PISO encoder provided in the prior art;
fig. 5 is a schematic structural diagram of a quasi-cyclic low density parity check code encoder according to embodiment 1 of the present invention;
fig. 6 is a flowchart of a parity bit generation method provided in embodiment 2 of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The encoder provided by the embodiment of the invention applies QC-LDPC code encoding, adopts the modes of parallel input of information bits and parallel output of check bits, and can improve the encoding speed and save encoding resources.
Example 1
Referring to fig. 5, the present embodiment provides a quasi-cyclic low-density parity-check code encoder structure, including: a serial/parallel conversion unit 101, an information bit buffer unit 102, a core encoding unit 103, an encoding matrix storage unit 104, and a parallel/serial conversion unit 105; wherein the content of the first and second substances,
the serial/parallel conversion unit 101 is configured to convert serially input information bits into parallel information bits, and output the information bits of a preset width to the core encoding unit 103 in parallel in each clock cycle under the time sequence control of the core encoding unit 103; the width of the parallel information bit output each time can be flexibly configured according to the requirement, and the device comprises an adaptive cache unit, a core coding unit and a control unit, wherein the adaptive cache unit is used for converting the serially input information bit into the parallel information bit with the preset width, then caching the parallel information bit and transmitting the parallel information bit to the core coding unit according to the time sequence requirement of the core coding unit;
the information bit buffer unit 102 is configured to buffer serially input information bits, and sequentially serially output the information bits together with the serial check bits obtained by the parallel/serial conversion unit 105 according to the time sequence requirement of the core coding unit 103 after the core coding is finished; the information bit buffer unit 102 may be provided inside the serial/parallel conversion unit 101 or may be provided outside the serial/parallel conversion unit 101.
The coding matrix storage unit 104 is used for storing a coding matrix and transmitting coding matrix bits with preset width to the core coding unit 103 in parallel;
the core coding unit 103 is configured to perform bitwise operation on the parallel information bits input by the serial/parallel conversion unit 101 and the parallel coding matrix bits input by the coding matrix storage unit 104 to obtain parallel check bits, output the parallel check bits to the parallel/serial conversion unit 105, and control the timing sequence of the entire encoder;
the parallel/serial conversion unit 105 is used for converting the parallel check bits input by the core coding unit into serial check bits, and sequentially and serially outputting the serial check bits and the serial information bits stored in the information bit buffer unit 102 under the time sequence control of the core coding unit 103, and comprises an adaptive output buffer unit which is used for converting the parallel check bits transmitted by the core coding unit into serial check bits, buffering the serial check bits and serially outputting the serial check bits according to the time sequence requirement of the core coding unit;
the bit width of the information bit parallel input and the check bit parallel output can be flexibly configured, when the width of the coding matrix circulation block is b bits, the bit width of the coding matrix parallel input is b bits, and meanwhile, the bit width of the information bit parallel input and the check bit parallel output is preferably also b bits.
The coding matrix stored in the storage unit 102 is a QC-LDPC code coding matrix, which is composed of c × t cyclic matrices with b × b size, and the coding matrix G qc As shown in formula (1):
The code length is t × b, wherein the information bit length is (t-c) × b, and the check bit length is c × b. The information bits in this embodiment are
Wherein
(1. Ltoreq. I. Ltoreq. T-c), namely: will be provided with
And dividing into t-c blocks, wherein each block is b in length. Check bit is
Wherein the content of the first and second substances,
order:
then:
namely, it is
Wherein, the first and the second end of the pipe are connected with each other,
is a circulant matrix, g i，j (line vector) is its first line, g i，j (l) (1. Ltoreq. L. Ltoreq. B-1) is g i，j Is cyclically shifted by l bits, h i，j (column vector) as its first column, h i，j (l) (l is not less than 1 and not more than b-1) is h i，j Is cyclically shifted by l bits.
According to equation (3), information bits can be input in parallel
And a coding matrix submatrix G i，j First row g of i，j Or the first column h i，j Each clock cycle can be derivedAnd accumulating the results obtained in each clock cycle
Check bits of parallel output are obtained through accumulation of t-c clock cycles
Example 2
With the core encoding unit 103 in the encoder provided in embodiment 1, this embodiment provides a parity bit generation method, and referring to fig. 6, a specific generation process is as follows:
step 201: the register P holding the intermediate result of the check bits (b bits) is cleared.
Step 202: parallel input of information bits to core encoding unit 103
(i is more than or equal to 1 and less than or equal to t-c), and inputting the row g of the coding matrix in parallel i，j Or column h i，j 。
Step 203: the core encoding unit 103 obtains G by combination selection i，j (i is more than or equal to 1 and less than or equal to t-c, j is more than or equal to 1 and less than or equal to c) is obtained by calculation according to the bitwise AND and XORAnd bitwise exclusive-ored with register P, accumulating the result in register P.
Step 204: the number of calculations i is increased by 1, and the initial value is 0.
Step 205: judging whether the calculation times i reach t-c times, if so, executing a step 206; otherwise, step 202 is performed. Step 206: t-c times cycle meterThe post-calculation register P obtains a check bit
Will be provided with
Output to the parallel/serial conversion unit 105.
Step 207: the cycle number j is added to 1, wherein the initial value of the cycle number j is 0.
Step 208: judging whether the cycle number j reaches c, if so, finishing the generation of the check bit; otherwise, the procedure returns to step 201.
After the core coding unit 103 generates the check bits, the check bits are output to the parallel/serial conversion unit 105 in parallel, and the information bit buffer unit 102 and the parallel/serial conversion unit 105 output serial information bits and serial check bits under the time sequence control of the core coding unit, thereby completing the coding process.
The parameters in this embodiment are the same as those in embodiment 1, and are not described again here.
The encoding schemes provided in embodiments 1 and 2 are called PIPO (Parallel Input Parallel Output) encoding schemes, and compared with the SIPO and PISO encoding schemes based on SRAA in general, the following discusses resource advantages of embodiments of the present invention at the same encoding speed, and for simplicity of description, c = t-c = b, the SIPO and PISO schemes based on SRAA in the prior art have the same encoding speed as the PIPO scheme of embodiments of the present invention, and are analyzed as follows:
1. resource consumption analysis
The SIPO scheme based on SRAA requires b (c = b) b-bit registers for storing coding matrixes and b-bit registers for storing check bits, and the total number of the b-bit registers is 2b 2 A register. b is a mixture of 2 A two-input AND gate (and must be implemented with a two-input AND gate), b 2 A two-input xor gate (and necessarily implemented with a two-input xor gate).
The PISO scheme based on SRAA needs b-bit registers for storing the coding matrix, and b is total 2 A register. b 2 A two-input AND gate and b 2 -1 two-input xor gate.
The PIPO scheme provided by the embodiment of the invention needs 1 b-bit register for storing the check bit, b registers in total, b 2 A two-input AND gate and b 2 A two-input exclusive-or gate. Let c = t-c = b, see table 2 for a comparison of SIPO, PISO and PIPO scheme resources at the same coding speed.
TABLE 2
| Coding scheme | Register with a plurality of registers | Two-input exclusive-OR gate | Two-input AND gate |
| SIPO | 2b 2 | b 2 | b 2 |
| PISO | b 2 | b 2 -1 | b 2 |
| PIPO | b | b 2 | b 2 |
The exclusive or operation in the SIPO must adopt a two-input exclusive or gate, while the PISO and PIPO schemes can adopt a multi-input exclusive or gate, which is more advantageous in hardware implementation; meanwhile, the PIPO scheme can greatly reduce the requirement on the register.
2. Experimental results of resource consumption
Experiments were performed on the quartz II platform on device Stratix EP1S80F1508C7, and device Stratix II EP2S90F1020C5, respectively. In the experiment, c = t-c = b =16 is set, and the results of resource (logic unit and register) consumption at the same encoding speed are shown in table 3 and table 4, where table 3 is resource consumption at 1S80 and table 4 is resource consumption at 2S 90:
TABLE 3
| SIPO | PISO | PIPO | |
| logic cells | 512 | 427 | 176 |
| lc registers | 512 | 256 | 16 |
TABLE 4
| SIPO | PISO | PIPO | |
| logic cells | 256 | 144 | 144 |
| lc registers | 512 | 256 | 16 |
The experimental result shows that under the same coding speed, the SIPO scheme consumes the most resources, the PIPO scheme consumes the least resources, and the PISO is between the SIPO scheme and the PIPO scheme, and is consistent with the analysis.
3. Experimental results of clock speed
Meanwhile, table 5 shows the fastest clock speed of each encoder on the FPGA obtained in the experiment. The experimental result shows that the clock speed of the scheme is as fast as that of the PISO scheme.
TABLE 5
| SIPO | PISO | PIPO | |
| 1S80 | 259.8l MHz | 390.02MHz | 390.02MHz |
| 2S90 | 230.36MHz | 400MHz | 400MHz |
Only the preliminary experiment was performed on the QC-LDPC code having the cyclic block size of 16 × 16 and c = t-c = b = 16. In practice, b is often much larger than c or t-c, for example, in the QC-LDPC code in the terrestrial digital television standard of china, there are three code rates, namely, a point 4 code rate (7493, 3048), a point 6 code rate (7493, 4572), and a point 8 code rate (7493, 6096), where the three code rates b =127, t =59, so t-c is 24, 36, and 48, respectively. Therefore, the fastest coding speed of the SIPO and PISO schemes cannot reach the fastest coding speed of the scheme. In addition, the PISO scheme requires that all information bits are input in parallel at the same time, and if the information bits are long, experiments show that the support of the FPGA is not good, and the encoding scheme of the embodiment of the invention is supported well.
The analysis result shows that compared with the SRAA scheme, the PIPO coding scheme provided by the embodiment of the invention can greatly save the consumption of resources at the same coding speed or can greatly improve the coding speed at the same resource consumption; meanwhile, the high coding speed is easy to achieve, and hardware implementation and hardware optimization are facilitated; is more suitable for high-speed QC-LDPC coding.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (4)
1. A quasi-cyclic low density parity check code encoder, the encoder comprising: the device comprises a serial/parallel conversion unit, an encoding matrix storage unit, an information bit cache unit, a core encoding unit and a parallel/serial conversion unit; wherein the content of the first and second substances,
the serial/parallel conversion unit comprises an adaptive input buffer unit which is used for converting the serially input information bits into parallel information bits with preset width, then buffering the parallel information bits and transmitting the parallel information bits to the core coding unit according to the time sequence requirement of the core coding unit;
the information bit cache unit is used for storing serially input information bits and serially outputting the information bits according to the time sequence requirement of the core coding unit;
the coding matrix storage unit is used for storing a coding matrix and transmitting coding matrix bits with preset width to the core coding unit in parallel;
the core coding unit is used for receiving the parallel information bits transmitted by the serial/parallel conversion unit and the parallel coding matrix bits transmitted by the coding matrix storage unit, calculating to obtain parallel check bits, and transmitting the parallel check bits to the parallel/serial conversion unit; and is also used to control the timing of the entire encoder;
the parallel/serial conversion unit comprises an adaptive output buffer unit which is used for converting the parallel check bit transmitted by the core coding unit into a serial check bit and then buffering the serial check bit, and serially outputting the serial check bit according to the time sequence requirement of the core coding unit.
2. The quasi-cyclic low density parity check code encoder as claimed in claim 1, wherein the bit width of the parallel information input by the core coding unit and the bit width of the parallel check bits output by the core coding unit are adjusted according to the requirements of coding speed and resource occupation, and the bit width of the parallel coding matrix input by the core coding unit is fixed.
3. A method for parity bit generation, the method comprising:
step A: resetting a register for intermediate results of the cached parallel check bits;
and B: transmitting parallel information bits and coding matrix bits with preset width to a core coding unit;
and C: the core coding unit carries out bitwise AND and XOR operation on the input parallel information bit and the parallel coding matrix bit, the obtained result and an intermediate result of the parallel check bit cached by the core coding unit are subjected to bitwise XOR operation, and the intermediate result is cached in the register;
step D: adding 1 to the calculation times, judging whether the calculation times reach preset times, if so, obtaining a final result of the parallel check bits, and then transmitting the final result to a parallel/serial conversion unit; otherwise, returning to the step B;
and E, step E: adding 1 to the cycle times, judging whether the cycle times reach the preset cycle times, if so, transmitting all the parallel check bits to the parallel/serial conversion unit, and finishing the check bit generation; otherwise, returning to the step A.
4. The check bit generating method according to claim 3, wherein the bit width of the parallel information bits with the preset width in step B and the bit width of the parallel check bits generated in step E are adjusted according to the requirements of encoding speed and resource occupation.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101442319B (en) * | 2008-11-25 | 2011-04-06 | 西安电子科技大学 | Encoder based on dual-diagonal quasi cyclic shift LDPC code check matrix |
| CN102231631A (en) * | 2011-06-20 | 2011-11-02 | 中兴通讯股份有限公司 | Encoding method for Reed-Solomon (RS) encoder and RS encoder |
| CN107888334A (en) * | 2017-09-30 | 2018-04-06 | 西安空间无线电技术研究所 | Random volume, decoder and method based on LT codes and LDPC code cascade |
| CN113472358A (en) * | 2021-06-17 | 2021-10-01 | 西安空间无线电技术研究所 | High-speed parallel encoder based on quasi-cyclic generator matrix |
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2007
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101442319B (en) * | 2008-11-25 | 2011-04-06 | 西安电子科技大学 | Encoder based on dual-diagonal quasi cyclic shift LDPC code check matrix |
| CN102231631A (en) * | 2011-06-20 | 2011-11-02 | 中兴通讯股份有限公司 | Encoding method for Reed-Solomon (RS) encoder and RS encoder |
| CN107888334A (en) * | 2017-09-30 | 2018-04-06 | 西安空间无线电技术研究所 | Random volume, decoder and method based on LT codes and LDPC code cascade |
| CN107888334B (en) * | 2017-09-30 | 2020-11-10 | 西安空间无线电技术研究所 | Random encoder, decoder and method based on LT code and LDPC code cascade |
| CN113472358A (en) * | 2021-06-17 | 2021-10-01 | 西安空间无线电技术研究所 | High-speed parallel encoder based on quasi-cyclic generator matrix |
| CN113472358B (en) * | 2021-06-17 | 2024-05-14 | 西安空间无线电技术研究所 | High-speed parallel encoder based on quasi-cyclic generation matrix |
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