CN106877882B - Data processing method and device - Google Patents
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- CN106877882B CN106877882B CN201710036389.9A CN201710036389A CN106877882B CN 106877882 B CN106877882 B CN 106877882B CN 201710036389 A CN201710036389 A CN 201710036389A CN 106877882 B CN106877882 B CN 106877882B
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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Abstract
The present disclosure relates to a data processing method and apparatus, the method comprising: acquiring data to be encoded; selecting a second generation matrix to encode the information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generation matrix, and the second generation matrix is obtained by replacing each cyclic matrix in the first generation matrix into a quasi-cyclic matrix; the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, and the product of the number of cyclic sub-matrices in each row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix. According to the method and the device, the bit width of the data of the encoding operation can be reduced through the transformation of the encoding generation matrix under the condition that the quasi-cyclic characteristic of the generation matrix is not changed, the logic resource occupation of the operation is reduced, and the working frequency of the encoding calculation is further improved.
Description
Technical Field
The present disclosure relates to the field of encoding technologies, and in particular, to a data processing method and apparatus.
Background
Quasi-cyclic Low-density Parity-check (QC-LDPC) codes have been widely verified by the industry to have error performance as good as randomly constructed LDPC codes. One of the encoding schemes commonly used in QC-LDPC codes is to implement linear encoding complexity by using a Shift Register accumulator structure (SRAA structure for short) with the help of quasi-cyclic characteristics. In the coding scheme, the data bit width of the coding operation is the cycle length of the QC-LDPC code, the logic resource occupation of the coder is directly related to the cycle length, and at least register resource with twice the cycle length is needed. Therefore, for the QC-LDPC codes with large cycle length, the logic resources required for implementing the encoder using the encoding scheme are high, and are not suitable for some items with low resource occupation requirements.
Disclosure of Invention
The present disclosure provides a data processing method and apparatus, which are used to solve the problem of high logic resources required by a QC-LDPC code with a large cycle length.
According to a first aspect of the present disclosure, there is provided a data processing method, the method comprising:
acquiring data to be encoded;
selecting a second generation matrix to encode the information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generation matrix, and the second generation matrix is obtained by replacing each cyclic matrix in the first generation matrix into a quasi-cyclic matrix; wherein the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, wherein the product of the number of cyclic sub-matrices per row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix.
Optionally, the permuting each circulant matrix in the first generation matrix into a quasi-circulant matrix includes:
acquiring a first matrix in the first generated matrix, wherein the first matrix is a matrix comprising (c-r) x r cyclic matrices; wherein each of the circulant matrices in the first matrix is a q × q matrix;
and performing row permutation and column permutation on each circulation matrix in the first matrix to obtain a quasi-circulation matrix corresponding to each circulation matrix, and obtaining a second matrix comprising (c-r) x r quasi-circulation matrices, wherein each quasi-circulation matrix is a matrix comprising l x l circulation sub-matrices, each circulation sub-matrix is a z x z matrix, q is l x z, q, l, z, c and r are natural numbers greater than 1, and c-r and r respectively represent the row number and the column number of the first generation matrix.
Optionally, the encoding the information segment to be encoded according to the second generator matrix includes:
c-r information segments to be coded are obtained;
multiplying a first vector comprising c-r of said information segments with said second matrix;
when each information segment in the first vector is multiplied by a corresponding quasi-cyclic matrix in the second matrix, each information segment is decomposed into l sub-information segments with the length of z, a second vector comprising the l sub-information segments is obtained, and the second vector is multiplied by the corresponding quasi-cyclic matrix.
Optionally, decomposing each information segment into l sub information segments with a length of z to obtain a second vector including the l sub information segments, and multiplying the second vector by the corresponding quasi-cyclic matrix, includes:
writing a kth sub information segment in l sub information segments with the length of z in a second vector obtained according to the ith information segment into a first shift register, and shifting the written kth sub information segment according to the current shifting times of the second vector; the first shift register is a z-bit shift register;
writing a first column element of a kth cyclic sub-matrix in a first column cyclic sub-matrix of a quasi-cyclic matrix corresponding to the second vector into a first register; the first register is a z-bit register, k is a natural number which is greater than 0 and less than or equal to l, and the initial value of k is 1;
multiplying the value in the first register and the value in the first shift register to obtain the coding result of the kth sub information segment;
caching the coding result in a second shift register, wherein the second shift register is a z-bit shift register;
taking k as k +1, and repeatedly executing the steps of writing the kth sub information segment of the sub information segments with the length of z in the second vector into a first shift register and caching the encoding result in a second shift register until the k is l, and finishing the encoding of the ith information segment;
and after the coding of the ith information segment is finished, taking i as i +1, and repeatedly executing the steps of writing the kth sub information segment in the l sub information segments with the length of z in the second vector into the first shift register and caching the coding result in the second shift register until i as c-r.
According to a second aspect of the present disclosure, there is provided a data processing apparatus, the apparatus comprising: at least one processor, a memory;
the memory is used for storing at least one program module;
the at least one processor, by executing the at least one program module stored in the memory, is configured to:
acquiring data to be encoded;
selecting a second generation matrix to encode the information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generation matrix, and the second generation matrix is obtained by replacing each cyclic matrix in the first generation matrix into a quasi-cyclic matrix; wherein the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, wherein the product of the number of cyclic sub-matrices per row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix.
Optionally, the permuting each circulant matrix in the at least one first generator matrix of the processor into a quasi-circulant matrix specifically includes:
acquiring a first matrix in the first generated matrix, wherein the first matrix is a matrix comprising (c-r) x r cyclic matrices; wherein each of the circulant matrices in the first matrix is a q × q matrix;
and performing row permutation and column permutation on each circulation matrix in the first matrix to obtain a quasi-circulation matrix corresponding to each circulation matrix, and obtaining a second matrix comprising (c-r) x r quasi-circulation matrices, wherein each quasi-circulation matrix is a matrix comprising l x l circulation sub-matrices, each circulation sub-matrix is a z x z matrix, q is l x z, q, l, z, c and r are natural numbers greater than 1, and c-r and r respectively represent the row number and the column number of the first generation matrix.
Optionally, the encoding, by the at least one processor, the information segment to be encoded according to the second generator matrix specifically includes:
c-r information segments to be coded are obtained;
multiplying a first vector comprising c-r of said information segments with said second matrix;
when each information segment in the first vector is multiplied by a corresponding quasi-cyclic matrix in the second matrix, each information segment is decomposed into l sub-information segments with the length of z, a second vector comprising the l sub-information segments is obtained, and the second vector is multiplied by the corresponding quasi-cyclic matrix.
Optionally, the decomposing, by the at least one processor, each information segment into l sub-information segments with a length of z to obtain a second vector including the l sub-information segments, and multiplying the second vector by the corresponding quasi-cyclic matrix specifically includes:
writing a kth sub information segment in l sub information segments with the length of z in a second vector obtained according to the ith information segment into a first shift register, and shifting the written kth sub information segment according to the current shifting times of the second vector; the first shift register is a z-bit shift register;
multiplying the value in the first register and the value in the first shift register to obtain the coding result of the kth sub information segment;
writing a first column element of a kth cyclic sub-matrix in a first column cyclic sub-matrix of a quasi-cyclic matrix corresponding to the second vector into a first register; the first register is a z-bit register, k is a natural number which is greater than 0 and less than or equal to l, and the initial value of k is 1;
caching the coding result in a second shift register, wherein the second shift register is a z-bit shift register;
taking k as k +1, and repeatedly executing the steps of writing the kth sub information segment of the sub information segments with the length of z in the second vector into a first shift register and caching the encoding result in a second shift register until the k is l, and finishing the encoding of the ith information segment;
and after the coding of the ith information segment is finished, taking i as i +1, and repeatedly executing the steps of writing the kth sub information segment in the l sub information segments with the length of z in the second vector into the first shift register and caching the coding result in the second shift register until i as c-r.
Through the technical scheme, the embodiment of the disclosure can have the following beneficial effects:
after the data to be coded are obtained, selecting a second generating matrix to code an information segment of the data to be coded, wherein the information segment is obtained by segmenting the data to be coded according to the dimension of the first generating matrix; the second generation matrix is obtained by permuting each cyclic matrix in the first generation matrix into a quasi-cyclic matrix; the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, and the product of the number of cyclic sub-matrices in each row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix. Because the second generation matrix is obtained by replacing each cyclic matrix in the first generation matrix into a quasi-cyclic matrix, and the quasi-cyclic characteristic of the matrix is not changed by the replacement of the matrix, the method and the device can reduce the data bit width of the encoding operation, reduce the logic resource occupation of the operation and further improve the working frequency of the encoding operation under the condition of not changing the quasi-cyclic characteristic of the generation matrix.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
FIG. 1 is a flow diagram illustrating a method of data processing in accordance with an exemplary embodiment;
FIG. 2 is a flow chart of a matrix permutation method according to the embodiment shown in FIG. 1;
FIG. 3 is a flow diagram illustrating a method of encoding processing according to the embodiment shown in FIG. 1;
FIG. 4 is a flow diagram illustrating a method of code computation according to the embodiment shown in FIG. 3;
FIG. 5 is a schematic diagram of an encoding calculation according to the embodiment shown in FIG. 4;
FIG. 6 is a schematic diagram of another encoding calculation shown in accordance with the embodiment shown in FIG. 4;
FIG. 7 is a block diagram illustrating a data processing apparatus according to an example embodiment.
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a flow chart illustrating a data processing method according to an exemplary embodiment, and referring to fig. 1, the data processing method may include the steps of:
in step 101, data to be encoded is acquired.
In step 102, selecting a second generator matrix to encode an information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generator matrix, and the second generator matrix is obtained by permuting each cyclic matrix in the first generator matrix into a quasi-cyclic matrix; the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, and the product of the number of cyclic sub-matrices in each row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix.
The first generator matrix may be an original generator matrix of the QC-LDPC code, and may be represented by:
wherein, I is a unit matrix with the size of q multiplied by q, and 0 is a full zero matrix with the size of q multiplied by q. G is because the result of the inverse, multiply and add operations of the circulant permutation array remains a circulant matrixi,jIs a circulant matrix with the size of qxq, wherein i is more than or equal to 1 and less than or equal to c-r, and j is more than or equal to 1 and less than or equal to r. It can be seen that GqcIs composed of two parts, wherein the matrix I(c-r)qIs an identity matrix of size (c-r) qx (c-r) q, and the matrix P on the right is a matrix of (c-r) x r consisting of circulant matrices of size q x q. Thus, G can be substitutedqcReferred to as a quasi-cyclic generator matrix in systematic form.
The foregoing permutation for each circulant matrix in the first generated matrix is a quasi-circulant matrix, which is actually to permute each circulant matrix G with a size of q × q in the matrix P, where G after the permutation is a quasi-circulant matrix, which can be represented as Ψ (G), a circulant matrix in each row of the quasi-circulant matrix can be represented as W, the quasi-circulant matrix is a square matrix with a latitude of l, and includes l × l circulant matrices, and each circulant matrix is a square matrix with a dimension of z, where q ═ l × z, q, l, z, c, and r are natural numbers greater than 1, and c-r and r respectively represent the number of rows and columns of the first generated matrix.
Therefore, the second generator matrix obtained after row-column permutation is still a quasi-cyclic matrix, the quasi-cyclic characteristic is not changed, and the cycle length is reduced from the original q to z, so that the bit width of the encoding operation is reduced from the original q to z during encoding.
In summary, the present disclosure relates to a data processing method and apparatus, the method includes: acquiring data to be encoded; selecting a second generating matrix to encode the information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generating matrix; the second generation matrix is obtained by permuting each cyclic matrix in the first generation matrix into a quasi-cyclic matrix; the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, and the product of the number of cyclic sub-matrices in each row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix. According to the method and the device, the bit width of the data of the encoding operation can be reduced through the transformation of the encoded generator matrix without changing the quasi-cyclic characteristic of the generator matrix, the logic resource occupation of the operation is reduced, and the working frequency of the encoding calculation is improved.
Fig. 2 is a flowchart illustrating a matrix permutation method according to the embodiment shown in fig. 1, and the method for permuting each circulant matrix in the first generated matrix into a quasi-circulant matrix as shown in fig. 2 includes the following steps.
In step 201, a first matrix of the first generated matrix is obtained, wherein the first matrix is a matrix including (c-r) × r circulant matrices, and each circulant matrix of the first matrix is a q × q matrix.
Wherein the first matrix is the matrix P in step 102, which is expressed as:
in step 202, perform row permutation and column permutation on each circulant matrix in the first matrix, obtain a quasi-circulant matrix corresponding to each circulant matrix, and obtain a second matrix including (c-r) × r quasi-circulant matrices.
For example, the method of permuting each circulant matrix in the first generator matrix into a quasi-circulant matrix may include:
consider that the circulant matrix G in the first matrix P described above is a matrix of size q × q, i.e. q elements per row and column. It can be defined that q ═ l × z, where l is the dimension of the permuted quasi-cyclic matrix Ψ (G), and z is the dimension of each cyclic sub-matrix of the quasi-cyclic matrix Ψ (G). The replacement process may include: for any i is more than or equal to 0 and less than l, pi can be definedi＝[i,l+i,2l+i,··,(z-1)l+]And constructing an index sequence pi ═ pi of matrix permutation0,π1,…,πl-1]. According to the index sequence, the cyclic matrix G is respectively subjected to row permutation and column permutation, and then the cyclic matrix can be changed into a quasi-cyclic matrix as shown in the following:
wherein, W0～Wl-1The superscript (1) denotes W0～Wl-1The cycle shifts down 1 time.
It can be seen that the conversion of the circulant matrix G of size qxq into the quasi-circulant matrix Ψ (G) consisting of l × l circulant sub-matrices of size zxz after row-column permutation is equivalent to the decomposition of the elements of each column of the circulant matrix G into l parts, each part having a length z. Therefore, the loop length is reduced from the original q to z, and the bit width of the encoding operation is reduced from the original q to z when encoding is performed.
In addition, it is worth mentioning that the values of l and z can be obtained based on the following principles:
because the frequency performance, the clock number and the resource occupation of the encoder are all inconsistent under different cycle lengths, a Time-space Product (TAP) can be defined as a standard for measuring the performance of the encoder, and the calculation formula of the TAP is as follows:
TAP is equal to clock number x trigger number x minimum delay
Taking an encoder as an example of a full-line block parallelism encoder, considering internal control and a BCU (binary coded decimal) calculation output part, the number of triggers required by the encoder to realize the implementation is determined by a cycle length z after cycle decomposition, and the full-line block parallelism encoder uses (c-r) × l Basic calculation units (BCU for short), so the implementation formula of the encoder is as follows:
where q is zxl, first part
Is the number of flip-flops required by the three counter groups, second part
Is a Read-Only memory (ROM) address line, the third part q × r is an information data shift register, the fourth part is each BCU calculation result of l × r, and x is a small amount of other control signals. In addition, of the above sections, although the sections involved in the definition of TAP are all related to the cycle length, each section is actually independent, so that the corresponding cycle length when achieving better performance can only be estimated from the results of frequency analysis. In this case, only the three parts of the counter group, the BCU calculation result and the XOR output of the BCU calculation result directly affect the frequency performance of the encoder, and these parts can be used respectively
And
and carrying out evaluation analysis on the three parts. Typically the original check matrix HqcThe number of the row blocks and the number of the column blocks are smaller than the cycle length of the BCU, so that the relation between the BCU calculation result and the BCU calculation result which is output in an exclusive or mode is only needed to be considered in value analysis.
The BCU calculation result and the BCU calculation result exclusive or output may be separately simulated to obtain a frequency value of the BCU calculation result and the BCU calculation result exclusive or output under the condition of different cycle lengths z, and a simulation result thereof may be as shown in table 1:
TABLE 1
Wherein, the calculation result is the BCU calculation result, and the XOR output is the BCU calculation result XOR output. Can determine when according to the simulation result
And
the delay is minimized when approaching, i.e. the highest operating frequency can be achieved by the encoder here.
When the encoder is a unit parallelism encoder, the internal control of the unit parallelism encoder and the output part of the BCU calculation are also considered (the unit parallelism encoder only uses one basic calculation unit, and the resource occupation is lowest), so the implementation formula of the encoder is as follows:
wherein the first part
The number of flip-flops required for five counter groups, second part
The third part is zx 3 and is a BCU calculation module, including an information data shift register, a calculation result buffer register and an output result register, wherein x is a small amount of other control signals.
In this case, only two parts, namely the counter group and the BCU calculation module, directly influence the frequency performance of the encoder, so that the two parts can be used respectively
And
and (6) carrying out analysis. In this scenario, the result of BCU calculation does not have a major impact on the frequency performance and the original check matrix H is usually usedqcWill be less than its cycle length, so analysis herein may only consider
And
the relationship (2) of (c).
Since the product of z and l is a fixed value and the frequency effect of the cycle length z on the encoder is given in table 1, it can be determined when the cycle length is
And coefficient of decomposition
The delay is minimized near where the best maximum operating frequency can be achieved.
The values of l and z can be determined based on the above principles.
Fig. 3 is a flowchart of an encoding processing method according to the embodiment shown in fig. 1, and as shown in fig. 3, the selecting the second generator matrix in step 102 to encode the information segment to be encoded may include the following steps.
In step 1021, c-r pieces of the information to be encoded are obtained.
Since the matrix P in the first generated matrix has (c-r) line blocks, the information sequence can be divided into (c-r) information segments, i.e. m ═ m (m), as described in step 1021,m2,…,mc-r) For convenience of explanation, the vector m will be referred to as a first vector.
In step 1022, the first vector comprising c-r of the information segments is multiplied with the second matrix.
The second matrix is a matrix obtained by replacing each cyclic matrix G in the matrix P with a quasi-cyclic matrix Ψ (G), when each information segment in the first vector is multiplied by a corresponding quasi-cyclic matrix in the second matrix, each information segment is decomposed into l sub-information segments with length z, a second vector including the l sub-information segments is obtained, and the second vector is multiplied by the corresponding quasi-cyclic matrix.
Illustratively, this step 1022 may include: multiplying a first vector comprising c-r of said information segments by said second matrix using a first encoding calculation formula;
the first encoding calculation formula includes:
wherein m isiRepresents the i-th of the information segment, h, in the first vectori,jRepresenting a circulant matrix G in the first matrixi,jAlso denoted G in the second matrixi,jThe permuted quasi-cyclic matrix (which can be expressed as Ψ (G)i,j) M) of the first column element, miThe superscript (z +1-l) of (A) denotes a cyclic downward shift of z +1-l times, hi,jThe superscript (l-1) of (A) represents hi,jThe cycle shifts down l-1 times.
Wherein, the formula (1) can be obtained according to the following principle:
dividing the first matrix P into r column blocks P ═ P1,P2,…,Pr]Wherein each sub-block Pj(1. ltoreq. j. ltoreq.r) comprises (c-r) circulant matrices of size qxq, i.e.
Therefore, one of the segments pjThe encoding calculation of (a) can be expressed as:
pj＝m·Pj＝m1·G1,j+m2·G2,j+…+mc-r·Gc-r,j(2)
according to the coding algorithm, linear computation complexity can be obtained through a segmented accumulation computation process.
The first column of elements may determine the circulant matrix, as is known from the definition of the circulant matrix. Thus h can be definedi,jIs a circulant matrix Gi,jThe first column of elements of
Represents hi,jCyclically shift the result down by one time, and
thus, when 1. ltoreq. l.ltoreq.q, the above formula (2) can be expressed as:
the above is considered for the q × q circulant matrix before the row-column permutation, and when the permutation is performed for the circulant submatrix including l × l z × z, the formula (3) can be expressed as the above formula (1).
The multiplying the second vector with the corresponding quasi-cyclic matrix comprises: the second vector is multiplied by the corresponding quasi-cyclic matrix using a first encoding calculation formula. Wherein if the second vector is according to the information segment miThe obtained quasi-cyclic matrix corresponding to the second vector is G in the first matrixi,jAfter replacement at the firstThe quasi-cyclic matrix of the two matrices can be expressed as Ψ (G)i,j)。
Thus, the first encoding calculation formula may include:
wherein [ m ]i,0mi,1… mi,l-1]Is expressed according to miThe second vector obtained, where mi,0～mi,l-1Represents miOf each sub-field of information of length z, Ψ (G)i,j) A quasi-cyclic matrix, W, representing the ith row and the jth column of the second matrix0～Wl-1Denotes Ψ (G)i,j) Cyclic sub-matrix of (1), W0～Wl-1The superscript (1) denotes W0～Wl-1Cyclically shifted down 1 time, hi,jDenotes Ψ (G)i,j) I.e. Ψ (G)i,j) Of the first column of l W, hi,jThe superscript (l-1) of (A) represents hi,jThe cycle shifts down l-1 times.
It is worth mentioning that the above method reduces the data bit width of the encoding operation and reduces the logic resource occupation of the operation without changing the quasi-cyclic characteristic of the generator matrix, besides, it is also used for permutated matrix Ψ (G)i,j) With its first column element hi,jAnd the superscript is used for representation, so that only the first column elements of the l W matrixes need to be stored during storage, and the total storage is still l × z ═ q bits, so that the total storage amount is not increased while the occupation of the logic resources of the operation is reduced.
Fig. 4 is a flowchart of a coding calculation method according to the embodiment shown in fig. 3, and as shown in fig. 4, for example, a BCU may include a first shift register, a second shift register and a first register, and the method for multiplying the second vector by the corresponding quasi-cyclic matrix shown in the above formula (4) may include the following steps.
The step 301 and the step 302 may be executed without any order, or may be executed simultaneously.
The above process completes the whole encoding work of the data to be encoded under the condition that the cycle length is z.
For example, fig. 5 is a schematic diagram illustrating a coding calculation flow according to an exemplary embodiment, where the coding calculation may be implemented by a BCU composed of one register and two shift registers, and the application scenario is a unit parallelism encoder that uses one BCU to perform coding calculation, referring to fig. 5, the first register is a register 501, the first shift register is a shift register 502, the second shift register is a shift register 503, and the coding calculation in the BCU may include the following flow.
Will be based on the information segment miM of l sub information segments with length z in the obtained second vectori,kWriting into shift register 502, and writing to m according to current shift times of the second vectori,kShifting and shifting h of the k-th cyclic sub-matrix in the first column of cyclic sub-matrices of the quasi-cyclic matrix corresponding to the second vectori，jWriting into the register 501; then, the value in the register 501 and the value in the shift register 502 are multiplied to obtain the mi,kAnd buffers the encoded result in the shift register 503. At this point, the information segment m is completediM in the sub information segment of (1)i,kThe coding of (2).
Then, taking k as k +1, repeating m in l sub information segments with length z in the second vectori,kWriting the coded result into the shift register 501, and buffering the coded result in the shift register 502 until k equals l, thereby completing the information segment miThe coding of (2). After completing the information segment miAfter the coding, i is taken as i +1, and m in l sub information segments with the length z in the second vector is repeatedly executedi,kAnd writing the coding result into the shift register 502, and buffering the coding result in the shift register 503 until i is equal to c-r. The encoding calculation of the data to be encoded is completed.
Fig. 6 is a schematic diagram illustrating another encoding computation flow according to an exemplary embodiment, which may be implemented by a plurality of BCUs in parallel, and the application scenario is a full-line block parallelism encoder using a plurality of BCUs for parallel encoding computation, and referring to fig. 6, the encoding computation module may process in parallel the encoding computation implemented by a plurality of BCUs shown in fig. 5. The process of implementing the coding calculation by each BCU is the same as the coding calculation process described in fig. 5, and is not described again.
In summary, according to the above technical solution, the present invention can obtain data to be encoded; selecting a second generating matrix to encode the information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generating matrix; the second generation matrix is obtained by permuting each cyclic matrix in the first generation matrix into a quasi-cyclic matrix; the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, and the product of the number of cyclic sub-matrices in each row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix. According to the method and the device, the bit width of the data of the encoding operation can be reduced through the transformation of the encoding generation matrix under the condition that the quasi-cyclic characteristic of the generation matrix is not changed, the logic resource occupation of the operation is reduced, and the working frequency of the encoding calculation is further improved.
Fig. 7 is a block diagram illustrating a data processing apparatus 700 that may be used to perform the method described in any of fig. 1-6, according to an example embodiment. Referring to fig. 7, the data processing apparatus 700 may include: at least one processor 710, memory 720;
the at least one processor 710, by executing the at least one program module stored in the memory 720, is configured to:
acquiring data to be encoded;
selecting a second generation matrix to encode the information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generation matrix, and the second generation matrix is obtained by replacing each cyclic matrix in the first generation matrix into a quasi-cyclic matrix; the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, wherein the product of the number of cyclic sub-matrices in each row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix;
optionally, the permuting each circulant matrix in the first generation matrix of the at least one processor 710 into a quasi-circulant matrix specifically includes:
acquiring a first matrix in the first generated matrix, wherein the first matrix is a matrix comprising (c-r) x r cyclic matrices; wherein each of the circulant matrices in the first matrix is a qxq matrix;
and performing row permutation and column permutation on each circulation matrix in the first matrix to obtain a quasi-circulation matrix corresponding to each circulation matrix, and obtaining a second matrix comprising (c-r) x r quasi-circulation matrices, wherein each quasi-circulation matrix is a matrix comprising l x l circulation sub-matrices, each circulation sub-matrix is a z x z matrix, q is l x z, q, l, z, c and r are natural numbers greater than 1, and c-r and r respectively represent the row number and the column number of the first generation matrix.
Optionally, the encoding, by the at least one processor 710, the information segment to be encoded according to the second generator matrix specifically includes:
c-r information segments to be coded are obtained;
multiplying a first vector comprising c-r of the information segments with the second matrix;
when each information segment in the first vector is multiplied by a corresponding quasi-cyclic matrix in the second matrix, each information segment is decomposed into l sub-information segments with the length of z, a second vector comprising the l sub-information segments is obtained, and the second vector is multiplied by the corresponding quasi-cyclic matrix.
Optionally, the decomposing, by the at least one processor 710, each information segment into l sub information segments with a length z to obtain a second vector including the l sub information segments, and multiplying the second vector by the corresponding quasi-cyclic matrix specifically includes:
writing a kth sub information segment in l sub information segments with the length of z in a second vector obtained according to the ith information segment into a first shift register, and shifting the written kth sub information segment according to the current shifting times of the second vector; wherein, the first shift register is a z-bit shift register;
multiplying the value in the first register and the value in the first shift register to obtain the coding result of the kth sub information segment;
writing a first column element of a kth cyclic sub-matrix in a first column cyclic sub-matrix of the quasi-cyclic matrix corresponding to the second vector into a first register; the first register is a z-bit register, k is a natural number which is greater than 0 and less than or equal to l, and the initial value of k is 1;
caching the coding result in a second shift register, wherein the second shift register is a z-bit shift register;
taking k as k +1, and repeatedly executing the steps of writing the kth sub information segment of the sub information segments with the length of z in the second vector into the first shift register and caching the encoding result in the second shift register until the k is l, and finishing the encoding of the ith information segment;
after the coding of the ith information segment is finished, i is taken to be i +1, and the steps from writing the kth sub information segment in the sub information segments with the length of z in the second vector into the first shift register to caching the coding result in the second shift register are repeatedly executed until i is taken to be c-r.
With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.
In summary, according to the above technical solution, the present disclosure can obtain data to be encoded; and selecting a second generating matrix to encode the information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generating matrix, the second generating matrix is obtained by replacing each cyclic matrix in the first generating matrix into a quasi-cyclic matrix, the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, and the product of the number of cyclic sub-matrices in each row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrix is equal to the dimension of the cyclic matrix. According to the method and the device, the bit width of the data of the encoding operation can be reduced through the transformation of the encoding generation matrix under the condition that the quasi-cyclic characteristic of the generation matrix is not changed, the logic resource occupation of the operation is reduced, and the working frequency of the encoding calculation is further improved.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (4)
1. A method of data processing, the method comprising:
acquiring data to be encoded;
selecting a second generation matrix to encode the information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generation matrix, and the second generation matrix is obtained by replacing each cyclic matrix in the first generation matrix into a quasi-cyclic matrix; wherein the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, wherein the product of the number of cyclic sub-matrices per row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix;
the permuting each circulant matrix in the first generation matrix into a quasi-circulant matrix includes:
obtaining a first matrix in the first generated matrix, wherein the first matrix is a matrix comprising (c-r) x r cyclic matrices, and each cyclic matrix in the first matrix is a q x q matrix;
performing row permutation and column permutation on each circulation matrix in the first matrix to obtain a quasi-circulation matrix corresponding to each circulation matrix, and obtaining a second matrix comprising (c-r) x r quasi-circulation matrices, wherein each quasi-circulation matrix is a matrix comprising l x l circulation sub-matrices, each circulation sub-matrix is a z x z matrix, q is l x z, q, l, z, c and r are natural numbers greater than 1, and c-r and r respectively represent the row number and the column number of the first generation matrix;
the selecting the second generating matrix to perform encoding processing on the information segment of the data to be encoded includes:
c-r information segments to be coded are obtained;
multiplying a first vector comprising c-r of said information segments with said second matrix;
when each information segment in the first vector is multiplied by a corresponding quasi-cyclic matrix in the second matrix, each information segment is decomposed into l sub-information segments with the length of z, a second vector comprising the l sub-information segments is obtained, and the second vector is multiplied by the corresponding quasi-cyclic matrix.
2. The method of claim 1, wherein decomposing each of the information segments into l sub-information segments of length z, obtaining a second vector comprising the l sub-information segments, and multiplying the second vector by the corresponding quasi-cyclic matrix comprises:
writing a kth sub information segment in l sub information segments with the length of z in a second vector obtained according to the ith information segment into a first shift register, and shifting the written kth sub information segment according to the current shifting times of the second vector; the first shift register is a z-bit shift register;
writing a first column element of a kth cyclic sub-matrix in a first column cyclic sub-matrix of a quasi-cyclic matrix corresponding to the second vector into a first register; the first register is a z-bit register, k is a natural number which is greater than 0 and less than or equal to l, and the initial value of k is 1;
multiplying the value in the first register and the value in the first shift register to obtain the coding result of the kth sub information segment;
caching the coding result in a second shift register, wherein the second shift register is a z-bit shift register;
taking k as k +1, and repeatedly executing the steps of writing the kth sub information segment of the sub information segments with the length of z in the second vector into a first shift register and caching the encoding result in a second shift register until the k is l, and finishing the encoding of the ith information segment;
and after the coding of the ith information segment is finished, taking i as i +1, and repeatedly executing the steps of writing the kth sub information segment in the l sub information segments with the length of z in the second vector into the first shift register and caching the coding result in the second shift register until i as c-r.
3. A data processing apparatus, characterized in that the apparatus comprises: at least one processor, a memory;
the memory is used for storing at least one program module;
the at least one processor, by executing the at least one program module stored in the memory, is configured to:
acquiring data to be encoded;
selecting a second generation matrix to encode the information segment of the data to be encoded, wherein the information segment is obtained by segmenting the data to be encoded according to the dimension of the first generation matrix, and the second generation matrix is obtained by replacing each cyclic matrix in the first generation matrix into a quasi-cyclic matrix; wherein the quasi-cyclic matrix is a square matrix comprising a plurality of cyclic sub-matrices, wherein the product of the number of cyclic sub-matrices per row of the quasi-cyclic matrix and the dimension of the cyclic sub-matrices is equal to the dimension of the cyclic matrix;
the permuting of each circulant matrix in the at least one first generator matrix of processors into a quasi-circulant matrix specifically includes:
acquiring a first matrix in the first generated matrix, wherein the first matrix is a matrix comprising (c-r) x r cyclic matrices; wherein each of the circulant matrices in the first matrix is a q × q matrix;
performing row permutation and column permutation on each circulation matrix in the first matrix to obtain a quasi-circulation matrix corresponding to each circulation matrix, and obtaining a second matrix comprising (c-r) x r quasi-circulation matrices, wherein each quasi-circulation matrix is a matrix comprising l x l circulation sub-matrices, each circulation sub-matrix is a z x z matrix, q is l x z, q, l, z, c and r are natural numbers greater than 1, and c-r and r respectively represent the row number and the column number of the first generation matrix;
the encoding, by the at least one processor, the information segment to be encoded according to the second generator matrix specifically includes:
c-r information segments to be coded are obtained;
multiplying a first vector comprising c-r of said information segments with said second matrix;
when each information segment in the first vector is multiplied by a corresponding quasi-cyclic matrix in the second matrix, each information segment is decomposed into l sub-information segments with the length of z, a second vector comprising the l sub-information segments is obtained, and the second vector is multiplied by the corresponding quasi-cyclic matrix.
4. The apparatus of claim 3, wherein the at least one processor decomposes each of the information segments into l sub-information segments of length z, obtains a second vector comprising the l sub-information segments, and multiplies the second vector by the corresponding quasi-cyclic matrix specifically comprises:
writing a kth sub information segment in l sub information segments with the length of z in a second vector obtained according to the ith information segment into a first shift register, and shifting the written kth sub information segment according to the current shifting times of the second vector; the first shift register is a z-bit shift register;
writing a first column element of a kth cyclic sub-matrix in a first column cyclic sub-matrix of a quasi-cyclic matrix corresponding to the second vector into a first register; the first register is a z-bit register, k is a natural number which is greater than 0 and less than or equal to l, and the initial value of k is 1;
multiplying the value in the first register and the value in the first shift register to obtain the coding result of the kth sub information segment;
caching the coding result in a second shift register, wherein the second shift register is a z-bit shift register;
taking k as k +1, and repeatedly executing the steps of writing the kth sub information segment of the sub information segments with the length of z in the second vector into a first shift register and caching the encoding result in a second shift register until the k is l, and finishing the encoding of the ith information segment;
and after the coding of the ith information segment is finished, taking i as i +1, and repeatedly executing the steps of writing the kth sub information segment in the l sub information segments with the length of z in the second vector into the first shift register and caching the coding result in the second shift register until i as c-r.
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| CN103023516A (en) * | 2013-01-01 | 2013-04-03 | 苏州威士达信息科技有限公司 | LDPC (low density parity check) coder capable of generating matrix and check matrix jointly and coding method |
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| CN101854228A (en) * | 2010-04-01 | 2010-10-06 | 华北电力大学（保定） | Method for constructing quasi-cyclic low-density parity check (LDPC) code |
| CN103023516A (en) * | 2013-01-01 | 2013-04-03 | 苏州威士达信息科技有限公司 | LDPC (low density parity check) coder capable of generating matrix and check matrix jointly and coding method |
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