CN107786211B - Algebraic structure obtaining method, encoding method and encoder of IRA-QC-LDPC code - Google Patents

Abstract

The invention discloses an IRAn algebraic structure acquisition method of an A-QC-LDPC code, a partial parallel coding method and a coder. The invention relates in particular to a sparse parity check matrix H ═ H_d H_p]H corresponding to the information bit of_dThe matrix algebraic structure acquisition method comprises the following steps: combining mathematics t- (v, k, λ)_t) The incidence matrix in the design is set to H_dA base matrix P of x y dimensions of the matrix when the parameters satisfy λ_tWhen 1 and v is 3k-2t +2, H_dThe column weight of the matrix is 3; using addition operations on the finite element subfield GF (q) for designing the full element shift matrix S_FThe base matrix P and the full-element shift matrix S are combined_FHadamard product is carried out to generate sparse shift matrix S_HWill S_HThe matrix is expanded by an L multiplied by L permutation matrix or an L multiplied by L all-zero matrix to obtain H_dA matrix; will double diagonal structure H_pThe matrix is decomposed into L multiplied by L partitioned sub-matrixes, and x sub-matrixes on the diagonal are still dual diagonal matrixes to form x linear serial coding algorithms which can be executed in parallel; the invention also realizes an IRA-QC-LDPC code encoder. The technical scheme of the invention effectively reduces the complexity of the coding algorithm and simultaneously reduces the hardware description complexity of the coder.

Description

Algebraic structure obtaining method, encoding method and encoder of IRA-QC-LDPC code

Technical Field

The invention belongs to the technical field of communication transmission channel coding, and particularly relates to an algebraic structure acquisition method, a parallel coding method and a coder of an IRA-QC-LDPC code.

Background

Low Density Parity Check (LDPC) codes defined as a sparse parity check matrix HNull space, i.e. Hc^TWhere H denotes a parity check matrix, c denotes a codeword sequence, and T denotes a transpose of a matrix or a vector. In 1962, Gallager firstly proposed an LDPC code and an iterative decoding algorithm thereof, but does not provide a construction method and an encoding algorithm of an H matrix. In 1995 thirty years later, Mackay re-discovered that LDPC codes were a good code approaching the shannon limit. Hui Jin in 2001 after 6 years proposed regular Repetitive Accumulation (RA) codes and Irregular Repetitive Accumulation (IRA) codes in his doctor paper, and theoretically proved that RA codes reached the Shannon limit on Gaussian white noise channels and IRA codes reached the Shannon limit on puncturing channels. For the beginning of the invention, both the RA code and the IRA code are considered to be a Turbo-like code. Thereafter, researchers analyzed their parity check matrices and found that the IRA code is an LDPC code with a random-like structure of a natural linear serial encoder. Its linear serial encodable characteristic is that the parity check matrix corresponding to check bit has double diagonal structure, and its quasi-random characteristic is that the parity check matrix corresponding to information bit is random structure.

Currently, in the communication industry standard, the practical LDPC codes with linearly-encodable systematic structure are mainly divided into two categories, and their corresponding parity check matrix H ═ H_d|H_p]There are also two typical configurations. A quasi-cyclic low-density parity check (QC-LDPC) code features that the parity check matrix is composed of block sub-matrices and its information bit is relative matrix H_dThe block sub-matrix is composed of a cyclic shift permutation matrix of n multiplied by n and an all-zero matrix of n multiplied by n, and a matrix H corresponding to the check bit_pThe block submatrix mainly comprises an identity matrix, an all-zero matrix and a permutation matrix, and H_pThe typical structure of (a) is an approximate lower triangular array structure, which can provide a linear encoding algorithm. The cyclic permutation matrix-based block structure of QC-LDPC is advantageous for the design of partially parallel hardware circuits for encoders and decoders, and has therefore been adopted by several industry standards of the IEEE 802 family. The other is IRA-LDPC code, which is mainly characterized in that the matrix H corresponding to the information bits_dIs of a random-like structure, the algebraic structure characteristics are not obvious, and therefore, a large number of 1-element storage devices are requiredLocating parameters of elements, matrix H corresponding to check bit_pIs of dual diagonal construction, provides a serial linear coding algorithm, and therefore finds application in a number of industry standards, including: the European second generation digital broadcast television standard DVB-S2, and the national military standard of the people' S republic of China (GJB 7296-2011).

The codes used in the standard all have a random-like framework structure. The random-like framework is characterized in that: structural parameters such as code rate and code length, and distribution of column weight and row weight of the parity check matrix are determined, and these parameters form the framework of H matrix determination; while the specific position distribution of the "1" element in the H matrix is uncertain, but its distribution is constrained by the framework structure. Therefore, the H matrix of the random executable code class in the standard is likely to be obtained by computer optimization search under the corresponding frame constraint. The H matrix obtained by searching in this way causes that part of parameters need to be stored in advance, and memory cells are occupied. For example, in the IEEE standard, the QC-LDPC code needs to store a cyclic shift value matrix from which the distribution of all 1 elements in the H matrix is determined. And in the European satellite communication standard, H of IRA-LDPC code_dThe matrix also obeys certain cyclic shift characteristics different from QC-LDPC codes, but the parameters needing to be stored are far more than the QC-LDPC codes; due to H in the Chinese military standard_dThe matrix has no cyclic characteristic, so the stored parameters are more than the parameters required to be stored by the IRA-LDPC code in the European satellite communication standard.

Disclosure of Invention

In view of the above drawbacks or needs of the prior art, the present invention provides an algebraic structure acquisition method, an encoding method and an encoder for an IRA-QC-LDPC code, aiming at combining mathematics t- (v, k, λ)_t) The incidence matrix in the design is set to H_dA base matrix P of x y dimensions of the matrix when the parameters satisfy λ_tWhen 1 and v is 3k-2t +2, H_dThe column weight of the matrix is 3; using addition operations on the finite element subfield GF (q) for designing the full element shift matrix S_FThe base matrix P and the full-element shift matrix S are combined_FPerforming Hadamard product to generate sparse shift momentArray S_HWill S_HThe matrix is expanded by a permutation matrix of L multiplied by L or an all-zero matrix to obtain H_dA matrix; therefore, the complexity of the coding algorithm is effectively reduced, and the complexity of the coder is also reduced.

To achieve the above object, according to an aspect of the present invention, there is provided an algebraic structure acquisition method of an IRA-QC-LDPC code, the method comprising:

the M multiplied by N dimension sparse parity check matrix is designed into a system structure H ═ H_d H_p]H in dimension of M × K × xL × yL corresponding to information bit_dThe matrix is designed into a block submatrix structure with x y L x L dimensions, each block submatrix is a permutation matrix or an all-zero matrix, and M x M (x M) x L dimensions corresponding to the check bits are a dual diagonal matrix H_pDecomposed into x × x L-dimensional block submatrices, x block submatrices on the diagonal being a dual diagonal structure; said H_dMatrix is composed of two compact matrices with smaller size and x y dimension base matrix P and sparse shift matrix S_HRepresents;

the base matrix P is represented by t- (v, k, lambda) in the combined mathematics_t) Constructing a designed incidence matrix; number of rows of the incidence matrix

Number of rows

Line weight

Column weight w_y(v-t +1)/(k-t +1) where t, v, k, λ_tIs a positive integer and satisfies v > k > lambda_t，λ_t＝1；

The sparse shift matrix S_HFrom a base matrix P and a full element shift matrix S_FDetermining that an addition operation alpha x beta (mod q) is introduced to a pixel subfield GF (q) to construct a positive integer matrix of q x q dimension, and arbitrarily cutting a full element shift matrix of x y dimension from the positive integer matrix to construct S_FQ is the smallest prime number greater than y, α, β ═ 0,1,2,. q-1;

the x y base matrix P and the x y full shift matrix S_FCarrying out generalized Hadamard product to generate the sparse shift matrix S with x y dimensions_H，S_HIs valued on GF (q) { -1 };

the sparse shift matrix S_HThe positive integer in (1) is extended by L × L permutation matrix, and the-1 is extended by L × L all-zero matrix to form H_dAnd (4) matrix.

Further, the base matrix P is represented by t- (v, k, λ) in the combinatorial mathematics_t) The designed incidence matrix is constructed, and the parameters satisfy v ═ 3k-2t +2 and lambda_tWhen 1, a P matrix with column weights of 3 is generated; when the parameter t is 3, the number of rows of the base matrix P is

Number of rows

Line weight

Column weight w_y＝(v-t+1)/(k-t+1)＝3。

According to another aspect of the present invention, there is provided an IRA-QC-LDPC code encoding method, the method specifically comprising:

sparse parity check matrix H ═ H_d H_p]The blocking feature of (a) is in particular that the K-long information sequence to be encoded is divided into y segments, denoted d ═ d₁...d_j...d_y]Wherein d is_j＝[d_j,1,d_j,2,...,d_j,L]Is a binary information vector of length L; the M long check sequence to be solved is divided into x segments, denoted p ═ p₁...p_i...p_x]Wherein p is_i＝[p_i,1,p_i,2,...,p_i,L]Is a binary check vector of length L; the coded code word sequence is c ═ d p]＝[d₁...d_j...d_y p₁...p_i...p_x](ii) a Said H_dAnd H_pThe block feature and code of^TWhen 0, we derive x independent matrix equations:

wherein,

represents H_dA block submatrix of the matrix; q_iRepresents H_pA block sub-matrix on a diagonal; t represents the transpose of a matrix or vector; each matrix equation forms an independent linear serial coding algorithm;

when H is present_dColumn weight w of the matrix_yWhen being equal to 3, then

Is shown simplified as

The symbol i denotes the index of x matrix equations, i 1, 2.., x; the symbol j represents y partitioned submatrix indexes in the ith matrix equation, and j is 1, 2. The symbols m and l represent their respective sub-matrices

M, L ═ 1,2, ·, L; 1, 2.; w is a_y1,2,3 is H_dAn index of matrix column weight 3; in the ith linear equation of the x independent matrix equations, a check vector p_i＝[p_i,1,p_i,2,...,p_i,L]Is calculated as

Check bit of first row is expressed by recursive summation

Calculation by recursive summationCalculating subsequent L-1 check bits, each check bit only needing to complete line weight w_xAn additive sum of data, where m is 2,3, and L denotes that each independent matrix equation has L check bits p_m,iTo compute serially, i 1,2, x denotes that there are x independent equations to complete L serial parity bits p in parallel_m,iAnd (4) calculating.

According to another aspect of the present invention, there is provided an encoder of an IRA-QC-LDPC code, the encoder including:

the y L long input buffer memory arrays are used for caching the K ═ yL bit information data sequence and starting the encoder to run, and when the information data of K ═ Ly is stored in the y multiplied by L input buffer memory array, the y L long information data are transmitted to the y L long information bit registers and are transmitted to the output end in series;

y information bit registers with length of L, when the information bit register receives the enable signal of '1', the data is output to the data line interweaving network, and when the enable signal is 0, the information is not output;

3 x y L long cycle left shift register arrays for accepting H_dThe first row of the 3 × y L × L permutation matrices contained in the matrix completes the initialization of the encoder; the loop left shift register array completes the operation of loop left shift once in parallel under the control of an enable signal E being 1, and a '1' element in each left shift register is used as an enable signal to be output to y L-length information bit registers;

x double summation processing units for receiving information data from the data line interleaving network, wherein the one-bit accumulator firstly processes w_xAccumulating and summing the data, sending the summation result to a one-bit feedback self-adder, simultaneously generating an enable signal E, then accumulating by the one-bit feedback self-adder, storing the calculation result of the check bit, and simultaneously outputting the calculation result of the check bit to x L-long output buffer arrays;

and the x L-long output buffer arrays respectively receive the check bits from the x double summation processing units, and sequentially output the information data sequence and the check data sequence through the multi-input single-output switch to form a coding output sequence.

Furthermore, y L-long input buffer arrays in the encoder are specifically composed of y L-long random storage units, and are used for buffering input information data to be processed, converting a serial input data sequence, an 8-bit, 16-bit or 32-bit parallel input data sequence into a data sequence with a segment length L and a codeword length K ═ Ly, and storing the data sequence, after a first L-long input buffer is full, automatically storing the data sequence into a second L-long input buffer until one codeword length K ═ Ly information data is full of y × L buffer arrays; the L-long input buffer can arbitrarily truncate 8-bit, 16-bit or 32-bit bytes, and the L-long input buffer is filled by right shifting; the y L long input buffers respectively complete the output of the L bit data serial of the y input buffers in sequence through a data line, and the data is transmitted to the y L long information bit registers and output to the output end of the encoder in serial.

Further, the 3 × y L-long left shift register arrays in the encoder are composed of 3 × y L-long arrays of writable erasable ROM or flash memory cells, and are arranged into y groups, and each group of 3L-long left shift registers is used for storing H_dSetting initial values for an encoder for a first row of 3 × y block permutation matrices of dimensions lxl of the matrix; receiving an enable signal E, circularly and leftwards shifting 3 multiplied by y L-length circular left shift registers once, wherein each register has only one 1 element, and the rest elements are 0, and outputting 1 element as an enable control signal of the y L-length information bit registers; the 3 x y L long loop left shift registers run in parallel, and each encoding cycle issues 3 x y enable control signals.

Furthermore, y L-long information bit registers in the encoder are formed by y L-long random storage units, and the y L-long information bit registers are serially input with information data by Y data lines L bits; each data storage unit of each L-length information bit register is provided with 3 enabling signal control ends and a data output line; information bit register for use with H_dOne row of a block permutation matrix in the matrix is subjected to multiplication, and only one of 3 enabling signals of each unit is 1 in each coding period; in a coding periodIn the system, y information bit registers work in parallel, each information bit register simultaneously outputs 3 data signals to a data line interleaving network, and 3y data signals are output in parallel.

Further, x double summation processing units in the encoder are composed of x double summers and an enable signal E generator; the dual summer includes w_xThe long shift register, the one-bit accumulator and the one-bit feedback self-adder are arranged in the long shift register; said w_xThe long shift register receives w from the data line interleaving network_xThe data are sent to the one-bit accumulator to be accumulated and summed, the calculated result is stored in the feedback self-adder, and an enable signal E is sent out at the same time₁,E₂,...,E_xThe feedback self-adder carries out one-time circular feedback self-addition on the newly stored data, saves the calculation result of the check bit and transmits the saved current value to the output buffer; the enable signal E generator is composed of an AND gate, and when x enable signals E are generated₁,E₂,...,E_xWhen both are 1, the enable signal generator output E ═ 1, where w_xLine weight is indicated.

Furthermore, x L long output buffer memory arrays in the encoder are composed of x × L Random Access Memory (RAM) units; the wiring form is to form x L long serial shift memories, first in first out; and the output end of the output buffer array sequentially outputs the information data sequence and the check data sequence through a multi-input single-output switch to form a coding output sequence.

Generally, compared with the prior art, the technical scheme of the invention has the following technical characteristics and beneficial effects:

(1) inventive matrix H_dUsing t- (v, k, lambda) in combinatorial mathematics_t) The design can make the maximum column weight of the parity check matrix corresponding to the information bit be 3, compared with the H matrix of the quasi-cyclic QC structure used in the IEEE standard, the number of the '1' elements reaches the minimum, compared with the H matrix of the IRA-LDPC code in the European satellite communication standard, under the conditions of similar code length and same code rate, the H matrix of the IRA-LDPC code in the European satellite communication standard_dThe number of '1' elements in the matrix is reduced by 20-30%, becauseTherefore, the computational complexity of the coding algorithm and the decoding algorithm is effectively reduced, and the hardware complexity of the coder and the decoder is also reduced;

(2) invention H_dThe matrix is a quasi-cyclic based block sub-matrix structure, and the matched dual diagonal lines H_pThe matrix can also be designed into a block form, so that the encoder can carry out partial parallel encoder design according to a block structure, and the execution time of the encoder is effectively reduced;

(3) the structure of the H matrix of the invention combines the structural characteristics of the IRA-LDPC code and the QC-LDPC code, not only can realize the partial parallel processing of the hardware circuit of the decoder like the QC-LDPC code, but also can perform partial parallel linear coding on the basis of the dual diagonal structure of the IRA code division block, and both the encoder and the decoder reduce the complexity and delay of hardware realization.

Drawings

FIG. 1 is a schematic block circuit diagram of an encoder of the present invention;

FIG. 2 is a schematic block diagram of an encoder input buffer array circuit of the present invention;

FIG. 3 is a functional block diagram of an encoder information bit register circuit of the present invention;

FIG. 4 is a schematic block diagram of an encoder cycle shift left register array circuit of the present invention;

FIG. 5 is a schematic block diagram of an encoder dual summing processing unit circuit of the present invention;

FIG. 6 is a schematic block diagram of an encoder output buffer array circuit according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

The basic principle of the invention is introduced:

parity check in the present inventionThe matrix has a systematic structure, i.e. H ═ H_d|H_p]In which H is_pThe matrix has the following block double diagonal structure,

wherein each sub-matrix is the same lxl bi-diagonal square matrix,

H_dthe matrix is in the form of an mxk ═ xL × yL block matrix,

wherein the subscript a_i,jRepresenting a cyclic shift value when the value range is a_i,jWhen the element belongs to {0,1, 2.,. L-1}, the submatrix

Is a permutation matrix of L × L, thus a_i,jAlso indicates the position coordinates of the first row of "1" elements of the L x L permutation matrix, which is circularly right-shifted by a column by L x L unit matrix_i,jObtaining the product; when a is_i,jWhen the molecular weight is equal to-1,

is an all-zero matrix of L × L, i 1, 2.

If from H_dExtracting the permutation matrix from the matrix, H_dIt can be further reduced to two types of matrices, namely, a base matrix P in x y dimensions and a shift matrix S in x y dimensions. The P matrix is constructed in the following way:

when the permutation matrix is used, the submatrix in the formula (3)

Substituted by 1 element; when in use

When being an all-zero matrix, a sub-matrix

Substituted with 0 elements, the P matrix can thus be written as P ═ P_i,j]，p_i,jE {0,1}, i 1,2, and x, j 1, 2. The S matrix is formed in the following way: the compound of formula (3) is represented by formula H_dThe subscripts of the matrix are extracted to form the following x y dimension shift matrix S,

if all a_i,jE {0,1, 2.,. L-1}, then S is a full-element shift matrix, denoted by S_FAnd (4) showing. If some exist

Then S is a sparse shift matrix, represented by S_HAnd (4) showing. One of the main tasks here is the design H_dSparse shift matrix S of matrix correspondence_HAnd requires H_dAnd H satisfies the row constraint, i.e., no 4 girth.

The invention designs H by using mathematical tools such as combination design, modulo n operation of finite field addition, generalized Hadamard product and the like_dAnd (4) matrix. Structure H_dThe basic idea of the matrix is: firstly, the combined design of the Steiner system structure H is utilized_dA base matrix P of the matrix; modulo n arithmetic construction H using finite field add-up_dFull element shift matrix S of matrix_F(ii) a Then the base matrix P and the full element shift matrix S_FCalculating sparse shift matrix S by generalized Hadamard product_H(ii) a Finally, the L multiplied by L permutation matrix and the L multiplied by L all-zero matrix are used for expanding S_HTo obtain H_d。

The following first describes the 3 basic mathematical tools required by the present invention, including the combined design Steiner system, the generation of a q × q matrix of positive integers by additive modulo n operations on the pixel subfield GF (q), and the quadrature method of two matrices on different fields, i.e. the generalized Hadamard product.

The combined design Steiner is a basic theory:

the combination design Steiner to be used in the present invention is described below.

Definition 1: let t, v, k, λ_tIs a positive integer and satisfies v > k > lambda_t. There is a doublet D ═ (X, B), X is a set of v elements, B ═ B₁,B₂,...,B_bIs a set of b k-tuples, which satisfies the following condition:

(a)|B_i|＝k，1≤i≤b；

(b) for any t-tuple on X, the number of the t-tuples contained in B is constant lambda_t；

Then B is said to be a t- (v, k, λ) on the set X_t) Design of, wherein B_iReferred to as a packet in set B; for parameter lambda_tThe t design at 1 is also known as the Steiner series and is denoted as S (t, k, v).

Theorem 1: let D ═ X, B be a t- (v, k, λ)_t) Design, μ is [0, t]If any integer is included in the integer, for any mu-tuple of X, B contains the number of groups of the mu-tuple_μThe calculation is as follows:

when mu is 0, t- (v, k, lambda)_t) Designed number of packets as

The invention specifies lambda_tLet D ═ 1, let D ═ X, B denote an arbitrary t- (v, k,1) or Steiner system S (t, k, v) design, defining the (t-1) correlation matrix of the dyad D as L_t-1(D)＝(l_i,j)，l_i,jE {0,1}, the binary matrix L_t-1(D) The number of rows is equal to the number B of groups of the set B, and the number of columns is equal to the number of all t-1 tuples in the v elements of the set X; when in parallel toL only when an element in the (t-1) tuple corresponding to the j-th column intersects an element in the k-tuple corresponding to the i-th row _i,j1 is ═ 1; otherwise l_i,j0. It follows that the matrix L_t-1(D) Is provided with

The rows of the image data are, in turn,

rows and having equal row weight w_r＝λ_t(v-t +1)/(k-t +1) and equal line weights

A row index i 1, 2., b and a column index j 1, 2., r, i.e. the matrix L_t-1(D) Is a matrix of dimension b x r.

Since the present invention requires the parity check matrix to be minimally sparse, so as to make H ═ H_d|H_p]The number of "1" elements of the matrix is minimized compared to all the LDPC codes in use, in order to achieve a reduction in the implementation complexity of the codec by reducing the number of "1" elements. Provision of H_dThe maximum weight of the matrix is designed to be 3, i.e. to be w_rBy setting (v-t +1)/(k-t +1) to 3, v-3 k-2t +2 is obtained. That is, when the positive integer values of the parameters t, v, k satisfy v ═ 3k-2t +2, the correlation matrix L of the binary D ═ X, B of the Steiner system S (t, k, v) is defined as_t-1(D) Constructed of H_dThe matrix satisfies the constraint of a maximum column weight of 3.

Introduction 1: if D is (X, B) is one S (t, k, v), the matrix L_t-1(D) The row and column constraint is satisfied.

In lemma 1, the meaning of satisfying the rank constraint is: l defined in binary field_t-1(D) The matrix does not contain 4-lines (i.e., does not contain 4-girth). L is_t-1(D) The reason for satisfying the row-column constraint is to specify a parameter λ_t＝1。

Finite field GF (q) basic theory:

the invention provides for the construction of a matrix of positive integers on the finite element subfield GF (q), the method of which is described below.

To construct a full-element shift matrix S_FA positive integer matrix needs to be designed. Roughly, when q is a prime number, GF (q) represents a finite field of q elements, and the addition and multiplication over GF (q) is defined as follows:

definition 1: for each a ≠ 0, a ∈ GF (q), the smallest positive integer n satisfying na ═ 0, referred to as the characteristic of the field element a. Then the element a in the field, under addition and multiplication, has the following form:

multiplication: a, a²,a³,...,a^m＝1,a,a²,., wherein m is a characteristic of a.

And (3) addition: a,2a,3a, na, 0, a,2a, wherein n is a characteristic of a.

As can be seen from the above, for addition, all elements in the prime subfield also form a cyclic abelian-addgroup.

From the addition operation of definition 1 on the prime field GF (q), a matrix V of q × q may be constructed, assuming that the row index of V is composed of the multiple values of the addition operation, assuming that α is 0,1,2,.. and q-1 denote different multiples of a, assuming that the column index of V is composed of the value a ∈ GF (q) of the addition operation {0,1,. and q-1}, assuming that β is 0,1, 2.

It is noted that the full shift matrix S_FAlso in the positive integer domain, so that only S is considered_FIs the size constraint problem of S_FIs a positive integer matrix of dimensions x y, S can be truncated from the positive integer matrix V of dimensions q x q_FAnd (4) matrix. Another constraint to consider is the girth feature of the positive integer matrix V. Theorem 3 and inference 1 below give the girth feature of the positive integer matrix V.

Theorem 3: assuming q is a prime number, if the q × q positive integer matrix V is expanded by using a binary permutation submatrix of dimension q × q, the matrix over GF (2) obtained after the expansion satisfies the row-column constraint, i.e., the matrix does not contain a closed 4-contour (girth).

Inference 1: and (3) if q is a prime number, L is a prime number larger than q, a positive integer matrix V of qxq is expanded by a permutation matrix of dimension LxL, and the matrix obtained after expansion meets row-column constraint.

Inference 1 shows that if L is a prime number, a binary matrix obtained by expanding a q × q positive integer matrix V with an L × L binary permutation matrix must satisfy row-column constraints and can serve as a parity check matrix of an LDPC code; if L is not a prime number, the expanded binary matrix cannot be guaranteed to meet the row-column constraint.

Generalized Hadamard product:

the invention specifies a base matrix P in the binary field GF (2) and a full-element shift matrix S in the positive integer field_FMultiplication is carried out to form a sparse shift matrix S satisfying row and column constraints_H. The concept of a generalized Hadamard product is introduced for this purpose.

Let matrix U ═ U_ij]Is a binary matrix of x y dimensions, and the matrix V is set to [ V ═ V_ij]Is a matrix of positive integers in the x by y dimension. Define generalized Hadamard product W ═ W_ij]＝UV＝[u_ij][v_ij]So that when u_ijWhen 1, w_ij＝v_ijIndicates w_ijIs a positive integer, when expanding the matrix W on the positive integer domain to a matrix in the binary domain, W_ijReplacing with a permutation matrix; when u is_ijWhen equal to 0, let w_ijIs-1, indicates w_ijIs not a positive integer, is represented by-1, when the matrix W on the field of positive integers is expanded into the binary field, W_ijWith an all-zero matrix.

It can be seen that the generalized Hadamard product as defined herein relates to a multiplication of two matrices over two different domains, where the result of the multiplication is to generate a sparse positive integer matrix, where the two domains refer to the binary domain and the positive integer domain. The matrix W resulting from the above method is sparse as long as U ═ U_ij]And V ═ V_ij]The rank constraint is satisfied, then W must satisfy the rank constraint. Thus, the matrix W may be used to construct a sparse shift matrix S_H。

A complete algebraic structure obtaining method of IRA-QC-LDPC code includes the following steps:

(1) designing the structure of a sparse parity check matrix H of the IRA-QC-LDPC code: the specific method is that the matrix H has a system structure with M × N dimensions, i.e. H ═ H_d|H_p]Where the information bits correspond to an M × K × xL × yL dimensional matrix H_dBlock submatrix structural features with quasi-cyclic, H_dThe block matrix is composed of x y block sub-matrixes, the size of each block sub-matrix is an L x L square matrix, the structure of the block sub-matrixes can be an L x L dimensional all-zero matrix or an L x L dimensional binary permutation matrix, and each permutation matrix is circularly right-shifted by a matrix_i,jThen obtain the cyclic shift value a_i,jWhen 0, the lxl permutation matrix is an identity matrix; when the value range is a_i,jE {1, 2.., L }, a_i,jGiven the coordinate position of the "1" element in the first row of the L × L permutation matrix, the unit matrix of L × L dimensions is circularly right-shifted by a column_i,jObtaining the L multiplied by L permutation matrix; when a is_i,jWhen is equal to-1, H_ai,jIs an L × L all-zero matrix, i 1, 2. M × xL dimensional matrix H corresponding to check bit_pHaving the structural feature of a block double diagonal, H_pComposed of x block sub-matrices, at H_pEach block submatrix on the diagonal is a dual diagonal matrix of dimension L × L, and each block submatrix on the off-diagonal is an all-zero matrix of dimension L × L.

(2) Design MxK dimension H_dX × y-dimensional basis matrix P corresponding to the matrix: the specific method is to combine the correlation matrix L of the two-tuple D ═ X, B in the S (t, k, v) Steiner system of the design_t-1(D) Is set to be H_dThe parameters of a base matrix P of the matrix are designed as follows: let P be ═ P_i,j]，i＝1,2,...,x，j＝1,2,...,y，p_i,jE.g. GF (2); is provided with

Giving the row number of the P matrix; is provided with

Giving the column number of the P matrix; let w_y(v-t +1)/(k-t +1) represents the column weight of the P matrix; is provided with

Represents the row weight of the P matrix; stipulate lambda_t1, the P matrix does not contain 4-contour; provision forThe values of the parameters t, v and k meet the expression v-3 k-2t +2 to obtain H_dThe column weight of the matrix is w_y(v-t +1)/(k-t +1) ═ 3; defining a correlation matrix L in a dyad D ═ (X, B)_t-1(D) The design of the k-tuple set B is obtained from a combined mathematic manual and published research papers, and can be designed by self as long as lambda is satisfied_tAll S (t, k, v) designs, 1 and v-3 k-2t +2, are suitable for use in the present invention; ordering rules of all elements in the B k tuples of the set B are arranged according to a dictionary order, and the set B is obtained as { B ═ B₁,B₂,...,B_b}; the invention particularly emphasizes the design of t-3, and requires parameters to satisfy lambda_t1, t-3 and v-3 k-4, and the associated correlation matrix is also the base matrix P-L_t-1(D)＝L₂(D) In that respect The number of columns of the base matrix is set by

Calculating; the invention provides that alpha < beta, and alpha, beta epsilon [1, v ∈ ]]Set a number of pairs (x)_α,x_β)_aThe subscript a of (a) denotes the sequence number of the doublet, a being 0,1,.., v (v-1)/2-1, the elements in each pair taking values from the set {1, 2.., v }, each pair being arranged in lexicographic order, typically in the form of:

the distribution of the "1" elements of each row in the base matrix P corresponds to the group B of the row_iThe above binary group consisting of the elements in (1) is related. In the case of line 0, the number of packets corresponding to line 0 is B₁；B₁Contains four elements x₁，x₂，x₃，x₄. These 4 elements constitute 6 tuples, their pair form in the above-mentioned sequence of pairs and their index numbers (x)₁,x₂)₀，(x₁,x₃)₁，(x₁,x₄)₂，(x₂,x₃)₇，(x₂,x₄)₈，(x₃,x₄)₁₃Then the position of the column of the "1" element of the 0 th row in the base matrix is determined by the subscript numbers 0,1,2,7,8,13 of the 6 tuples.

(3) Design MxK dimension H_dX y dimension full element shift matrix S corresponding to matrix_F: the specific method is to design a full-element shift matrix S with x y dimensions by introducing addition operation on a finite field GF (q)_F. Let S_F＝[s_i,j]，i＝1,2,...,x，j＝1,2,...,y，s_i,jIs epsilon GF (q). Assuming that q is the minimum prime number greater than y, a positive integer matrix V of q × q is constructed [ α × β ═ q](mod q), α, β ═ 0,1, 2. Taking the first x rows and the first y columns from the qxq V matrix to form a full element shift matrix S with the x y dimension_F. Since the V matrix defined in the prime subfield GF (q) satisfies the row-column constraint, the S dimension of x y is truncated from the V matrix of q x q_FThe matrix also satisfies the row-column constraint; truncating the x by y dimension S from a qxq V matrix_FOther methods of matrix are: regarding the x y matrix as a window, the whole window frame can slide on the q x q V matrix, and the positive integer matrix with the size of x y can be arbitrarily cut from the q x q V matrix to serve as S_FAnd (4) matrix.

(4) Design MxK dimension H_dSparse shift matrix S with x y dimensions corresponding to matrix_H: let S_H＝[w_i,j]，i＝1,2,...,x，j＝1,2,...,y，w_i,jE.g. GF (q) U { -1 }. Shifting the x y dimension base matrix P and the x y dimension full element matrix S_FPerforming a generalized Hadamard product to thereby generate a sparse shift matrix S of x y dimensions_HThe invention specifies S_H＝P×S_F＝[p_i,j×s_i,j]＝[w_i,j]When p is_i,jWhen 1, w_i,j＝s_i,j(ii) a When p is_i,jWhen equal to 0, w_i,j＝-1。

(5) Despreading sparse shift matrix S with L x L dimensional partitioned submatrices_HTo design H_dMatrix: the specific method is to S_H＝[w_i,j]，i＝1,2,...,x，j＝1,2,...,y，w_i,jE.g. GF (q) U { -1}, when w is_i,jE is GF (q), the unit matrix is circularly shifted by w_i,jThen, obtain a value corresponding to w_i,jL of shift valueX L permutation matrix when w_i,jForming an L × L all-zero matrix, and replacing S with x × y L × L permutation matrices and all-zero matrices_HOf (2) a corresponding element w_i,jObtaining H with dimension of M × K ═ xL × yL_dAnd (4) matrix. H_dNumber of rows of matrix

H_dThe number of columns of the matrix is

H_dThe row weight of the matrix is

H_dThe column weight of the matrix is w_y(v-t +1)/(k-t + 1). By H ═ H_d H_p]The matrix-defined IRA-QC-LDPC code has a code length N ═ K + M ═ yL + xL, and a code rate R ═ K/(K + M) ═ y/(y + x).

An IRA-QC-LDPC code encoding method includes the following steps:

for systematic forms of linear block codes, such as the IRA-QC-LDPC codes of the present invention, the encoding process is actually performed using the information sequence and H_dAnd (5) calculating a check sequence by matrix multiplication. Including a double diagonal line H_pH ═ H for matrix characterization_d|H_p]The matrix has a natural linear serial coding algorithm, serial coding refers to one-bit and one-bit calculation when calculating check bits, the calculation result of the previous check bit is needed when calculating the current check bit, and the main reason is that when H is used_pWhen the matrix has the characteristic of a dual diagonal structure, the derived coding algorithm is a recursive function. If the time to compute a one-bit parity bit is set to a period T, called an encoding period, then the time to serially compute an M-bit parity bit is MT. The invention relates to a method for preparing a compound H_dThe matrix is designed into a block submatrix form, namely, in order to shorten the calculation time of the serial coding algorithm from MT to LT, x linear serial coding algorithms with the calculation scale of LT are executed in parallel, and therefore the parallel execution algorithm is called as x linear serial coding algorithms. The parallel characteristics of parallel execution of x linear coding algorithms depend onIn H_dMatrix sum H_pThe matrixes are all formed by L multiplied by L partitioned sub-matrixes, and the linear characteristics of the matrixes depend on H_pThe dual diagonal block sub-matrix of the matrix still has the dual diagonal structural feature.

According to H ═ H_d|H_p]The block characteristic of the matrix is that the information sequence to be coded is represented in a segmented manner, the information data sequences with the length of K equal to yL are totally divided into y segments, the length of each segment is L, and the segment is marked as d equal to [ d ═ d₁...d_j...d_y]Wherein d is_jIs a binary sequence vector that is L long. Similarly, the check bit sequence to be solved is segmented, the check bit data sequences with the length of M ═ xL are totally divided into x segments, each segment is of the length L, and the length is marked as p ═ p₁...p_i...p_x]Wherein p is_iIs a binary sequence vector that is L long. The information bit sequence d ═ d at the output of the encoder₁...d_j...d_y]And the check bit sequence p ═ p₁...p_i...p_x]Combining to obtain coded code word sequence c ═ d p]＝[d₁...d_j...d_yp₁...p_i...p_x]. According to Hc^T0 to obtain Hc^T＝[H_d|H_p][d|p]^TH can be deduced when H is equal to 0_dd^T+H_pp^TUnder binary operation conditions, 0, one can deduce:

H_dd^T＝H_pp^T (6)

the formula (1), the formula (3) and the sequence d ═ d₁...d_j...d_y]And p ═ p₁...p_i...p_x]And substituting the formula (6), and expanding the formula (6) into the following form according to the form of the block matrix:

and further expanding the formula (7) according to the form of a block matrix and a segmented vector to obtain the following x independent matrix equations:

each matrix equation comprises L linear equations which are mutually correlated, and a linear coding algorithm is formed. Each of the x independent matrix equations comprises L linear equations which can respectively utilize the right x L dimensional dual diagonal matrix Q₁,Q₂,...,Q_xSolving the corresponding x check vectors p with the length of L₁...p_i...p_x. The linear serial coding algorithm resulting from the L independent sets of linear equations in a matrix equation is first derived. From the general point of view, taking the ith matrix equation in the x matrix equations as an example, let the jth vector in the y information sequence vectors with the same length as L be represented as d_j＝[d_j,1,d_j,2,...,d_j,L](ii) a Let the ith vector of x vectors of check bit sequence of the same length L be denoted as p_i＝[p_i,1,p_i,2,...,p_i,L](ii) a Let the jth LxL syndrome matrix of the ith matrix equation

Has the following forms:

wherein

The first symbol of the superscript represents the index of x matrix equations, i is 1,2,.. and x, the second symbol represents the index of y block submatrices in the ith matrix equation, and j is 1,2,. and y;

two elements of the subscript respectively represent the sub-matrixes

Row and column indices, m, l1, 2. Thus, the ith matrix equation in equation (8) can be written in the form of the following matrix:

from the 1 st row of the ith matrix equation, the first parity bit p corresponding to the first linear equation included in the ith matrix equation can be obtained_1,i

The remaining L-1 parity bit p can be solved by the same method_m,i，m＝2,3,...,L

The solving expression of the L check bits from the above ith matrix equation can be abbreviated as the following recursive summation expression,

(10) equations (10) and (11) form a linear serial coding algorithm for calculating L check bits, where equation (10) calculates the check bits in the first row of the ith independent matrix equation, and equation (11) indicates that the remaining L-1 check bits of the ith matrix equation are calculated recursively, and when i is 1, 2. It should be noted that the calculation of the linear equation for each row is actually the calculation of H_dThe product of a row of the matrix and the K ═ yL bit information bits is then summed, so that first parity bit p of the ith matrix equation is first calculated using equation (10)_1,iTo get it readyThe second parity bit p can be calculated by equation (11)_2,iThat is, to calculate the mth check bit, the (m-1) th check bit must be calculated first, which is a linear recursive calculation to form a linear serial encoding algorithm.

For lambda_tCombined design of 1 and v 3k-2t +2, corresponding to H_dThe column weight of the matrix is w_yLine weight is 3

Design of (H)_dThe matrix has only 3 · y ═ w_xThe x permutation matrices participate in the calculation of equations (10) and (11). Let H_dThe matrix array weight index is g ═ 1,2_y1,2,3, then H_dThe elements of the displacement matrix in the matrix can be simply expressed as

Since the general expression of the ith independent equation is derived, the first symbol of the superscript may be omitted and the first symbol of the subscript indexed by weight, so that H_dThe permutation matrices in the matrix may be arranged as 3 × y ═ w_xX array, formula (10) and formula (11) are each only w_xThe product term participates in the summation

(12) Formula (13) by considering H_dThe sparsity of the matrix, the case of column weight and row weight simplify the calculation, mainly H_dThe summation operation with the K-yL bit information bit for each row of the matrix is not performed in the K-yL bit, but rather when H is used_dThe calculation is only needed if there are 1 elements in each row of the matrix. It can be seen that when the x independent matrix equations of the formula (8) are expanded to bitwise calculation, x linear serial encoding algorithms of the formulas (12) and (13) are formed.

An IRA-QC-LDPC code encoder:

as can be seen from expressions (12) and (13), the multiplication operation

No computation is required because in the L × L-dimensional block submatrix, only one element per row is 1 and the remaining elements are 0, so w_xThe term multiplication operation effectively retains the information bit data corresponding to the element of each row "1" in the partitioned submatrix. The main computational task is to perform a summation operation

And this summation operation is also only w_xTerm summation, not L term summation. In addition, due to H_dThe structure of the matrix is formed by circularly shifting sub-matrixes, only the first row of y L multiplied by L sub-matrixes of each independent matrix equation needs to be stored in advance, and the rest rows are circularly shifted to the right once every one clock period under the control of a set coding period to generate the next row of the L multiplied by L dimensional sub-matrixes. The principle circuit construction for parallel execution of x linear serial coding algorithms is as follows:

as shown in fig. 1, which is a general block diagram of an encoder circuit, the principle circuit for parallel implementation of x linear serial encoders includes: the system comprises a y multiplied by L input buffer array, y L long information bit registers, 3 multiplied by y L long circulation left shift register array, x parallel double summation processing units and an x multiplied by L output buffer array.

The working principle is as follows: h is to be_dThe first row of 3 multiplied by y known L multiplied by L permutation matrixes contained in the matrix is stored in the circulating left shift register array, and the initialization of the encoder is completed; inputting a K-yL bit information data sequence to start an encoder, and automatically inputting data to the information bit register in series when y L long input buffers are full of L long information bits; after the y L long information bit registers are full of L bit data, H is started_dMultiplication and summation calculation of each row of the matrix and the yL bit information bit; the unit of 1 in each cycle left shift register sends out an enable signal to the corresponding unit of the information bit registerOutputting the information data of the element; each unit of the L long information bit register is only provided with one data line connected with x parallel double summation processing units, and each double summation processing unit is connected with six data lines from the information bit register, so that an Lxy data line interleaving network is formed between y L long information bit registers and x parallel double summation processing units; 3 x y L long circulation left shift register arrays are divided into y groups, each group of 3L long circulation left shift register arrays can run in parallel with y L long information bit registers, each 3 x y L long circulation left shift register array receives an enabling control signal E, the circulation left shift is performed once, and the calculation process of the next check bit is started; in each circulation left shift, 3 units of output information data of each information bit register are transmitted to x parallel double summation processing units through a data line interweaving network, and 3 multiplied by y data information is output in each coding period; each of the x parallel double summation processing units receives w_xA data signal, a common input x w_x3 × y signals; each double summation processing unit completes two summation operations, firstly, to w_xThe data signals are accumulated and summed to finish

The obtained sum is sent to a feedback self-adder to be stored, and an enable signal E is sent out₁,E₂,...,E_xWhen E is₁,E₂,...,E_xWhen all the values are 1, outputting an enable signal E which is 1 to 3 multiplied by y L long circulation left shift register arrays, completing one circulation left shift in parallel, and starting the next calculation; completion H_dThe computation of multiplication and summation of a row of the matrix with the K ═ yL bit information bits requires the following analysis of the consumed clock cycles: the circular left shift register array receives the enable signal, needs a machine period to perform circular left shift operation, sends the enable signal to trigger the information bit register to output data, needs to consume a machine period, needs a clock period to start the first adder of the double summation processing unit, and completes w in the adder_xThe accumulation of individual data consumes w_xOne machine cycle, thus completing

Calculating the need w_x+3 machine cycles, called one encoding cycle.

It should be noted that the y L-long input buffer arrays and the y L-long information bit registers store binary data in such a way that the least significant bit is on the right and the most significant bit is on the left, thus requiring 3 × y L-long circular shift register arrays to store H from the right_dThe first column of the matrix is originally a permutation matrix circularly shifted to the right, and the circular shift register needs to be designed to circularly shift to the left in hardware design.

As shown in fig. 2, the y × L input buffer array is formed by y L long RAM random access memories, and is used for buffering input information data to be processed, and functions to convert a serial input data sequence or a parallel input data sequence of 8 bits, 16 bits or 32 bits into a data sequence suitable for an encoding length L and a codeword length K equal to Ly; the method comprises the steps of sequentially storing 8-bit, 16-bit or 32-bit data transmitted from a data parallel input port into y L-long input buffers, automatically entering a second input buffer after a first L-long input buffer is full of data, ensuring continuous and uninterrupted storage of information data streams until a code word length K ═ Ly information data is full of a y multiplied by L buffer array, requiring a buffer system to arbitrarily cut 8-bit, 16-bit or 32-bit bytes so as to meet the continuous full-storage requirement of the L-long buffer, wherein L is likely to be prime number and not byte 2^eWhere e is 3,4, 5; when the y × L input buffer array is full of information for one codeword, K ═ Ly, the start of the next K long codeword may be part of one byte of the parallel input ports, and the buffer array can still store the next K long codeword in turn. The output operation is only possible when the y × L input register array is full of K ═ Ly information, and each of the y L long input registers is connected to a respective one of the data lines I₁,I₂,...,I_yAnd completing the data output operation of the parallel y data lines and the serial L bit data, and transmitting data to the y L long information bit registers.

As shown in FIG. 3, the information bit register set is composed of y L-long shift registers, and the input mode is that each L-long shift register is composed of an independent data line I_jJ 1, 2.. y serially inputs information data from the input buffer; the L-th information bit cell of the j-th information bit register has three enable control signal input ports and one data signal output port, the three enable signals coming from the circular shift register group because the column weight is 3, where j is 1, 2. The working principle is as follows: when the received enable signal is 1, the data is output, and when the received enable signal is 0, the information bit unit is closed and the information is not output.

Although each information bit unit has three enabling input signals, in each coding period, only one enabling signal in the three enabling signals is high level '1', and the other two enabling signals are low level '0'; each of the y L-long shift registers has three unit output signals per coding period, and thus 3 · y data information is output per coding period.

As shown in fig. 4, the circular shift register array is composed of 3 × y L-long circular shift registers, which form y groups, and each group is 3L-long circular shift register arrays. The data input mode is S_HStoring the first row data of three sub-matrixes corresponding to the first column of the matrix into the rightmost 3 circulation left shift registers, and sequentially storing H in the 3 multiplied by y L long circulation left shift register arrays respectively_dThe 3 × y blocks of dimension L × L of the matrix permute the first row of the matrix, completing the initialization of the encoder. The working principle is as follows: 3 x y circulation left shift registers receive the enabling signal E as 1 at the same time, and complete the operation of circulation left shift once; the 1 element in the left shift register of each cycle is output as an enable signal for controlling the output of a certain bit of data of the corresponding information bit register. Only one element in each circulation left shift register is 1, and the other elements are 0; the 3 × y loop shift registers have the same enable signal E equal to 1 and perform loop shift left at the same time.

As shown in fig. 5, x double summation processing units are used to calculateAnd the processing unit consists of x computing units which run in parallel and comprise two adders and an enabling signal E generator. Wherein, the x double summation processing units are composed of w_xThe long shift register, a one-bit accumulator and a feedback self-adder. Each double summation processing unit receives w from the data line interleaving network_xStoring of individual data into w_xIn a long shift register, then w is done in a one-bit accumulator_xThe accumulation of data is actually performed in an accumulator

The calculation result is sent to a feedback self-adder to be stored, and simultaneously, each of x one-bit accumulators running in parallel generates an enable signal E₁,E₂,...,E_xThe x enable signals enter an AND gate, and when the input signals are all 1, the AND gate outputs an enable signal with E being 1; the task of the feedback self-adder is to actually convert w into a code period_xProduct term

Result of summation of (2)

Adding the last check bit to complete the operation in the formula (13)

And (4) calculating. The check bit is stored in the feedback self-adder every time a check bit is obtained, except that the first row does not need to be fed back to the self-adder, and the check bit is output to the output buffer.

As shown in fig. 6, the output buffer array is composed of x × L RAM units, and the connection form is to form x L long serial shift memories, respectively receive the check bit calculation results from the x double summation processing units, first in first out, serial input and output the L calculated check values to the output buffer, shift right, and serially output; each of the x L-long output buffers gets a correctionAnd inputting verification data. Connecting an x +1 input-output multi-input single-output switch to the output ends of x L long output buffers, firstly connecting the multi-input single-output switch to an information bit data line, outputting the information data with the length of K ═ yL, then sequentially connecting the output ends of the x L long output buffers, and sequentially outputting M ═ xL check bits, thereby completing the encoding work and outputting an encoded code word c ═ d p]＝[d₁...d_j...d_yp₁...p_i...p_x]。

In order to make the technical scheme and implementation steps of the invention more clear, the following describes the implementation mode of the invention with specific examples. It should be noted that the following examples are only intended to illustrate the present invention, but not to limit the present invention.

It is first necessary to determine whether the t- (v, k,1) or S (t, k, v) Steiner series in the combinatorial design are known. In the mathematical manuals of combinatorial design and related research literature, all known t- (v, k, λ)_t) As long as the parameters t, k, v match with the parameters of the corresponding parity check matrix, they can be used for the technical implementation of the present invention.

Let t be 3, k be 4, v be 8, λ₃The known 3- (8,4,1) combinatorial design or Steiner series S (3,4,8) is obtained for 1. First, a doublet D (X, B) is generated from this known combinatorial design, assuming that the set of elements of the 3- (8,4,1) combinatorial design is denoted X { X ═ X₁,x₂,...,x₈}. Calculating the number of rows of the base matrix P

Assume that the packet set is denoted as B ═ B₀,...,B_i,...,B₁₃Where t-3 tuples occur once in each k-4 tuple of the set B, i.e. λ₃1 is ═ 1; and arranging each k-4-tuple group in the B according to the dictionary sequence and the parameter requirement to obtain a 4-tuple set consisting of the following 14 tuples:

B₀＝{x₁,x₂,x₃,x₄}，B₁＝{x₅,x₆,x₇,x₈}，B₂＝{x₁,x₂,x₅,x₆}，B₃＝{x₃,x₄,x₇,x₈}，B₄＝{x₁,x₄,x₅,x₈}，B₅＝{x₂,x₃,x₆,x₇}，B₆＝{x₁,x₂,x₇,x₈}，B₇＝{x₃,x₄,x₅,x₆}，B₈＝{x₁,x₄,x₆,x₇}，B₉＝{x₂,x₃,x₅,x₈}，B₁₀＝{x₁,x₃,x₅,x₇}，B₁₁＝{x₂,x₄,x₆,x₈}，B₁₂＝{x₁,x₃,x₆,x₈}，B₁₃＝{x₂,x₄,x₅,x₇}。

constructing S (3,4,8) the correlation matrix L of Steiner series₂(D) The method comprises the following steps The 14 packets in the set B give the row index of the correlation matrix, i.e., i 1, 2. The set X has 8 elements, and t-1 ═ 2 tuples (X)_α,x_β) A share of

Each one gives L₂(D) The number of columns. And L can be calculated₂(D) Has a row weight of

L₂(D) Has a column weight of w_x(v-t +1)/(k-t +1) ═ 3. The indexing scheme for the 28 columns is designed as follows. Let alpha < beta, and alpha, beta E [1,8 ]]Set a number of pairs (x)_α,x_β)_jThe index j of (a) indicates the sequence number of the tuple, each t-1 ═ 2 tuples (x)_α,x_β)_jOnly once, there is dictionary ordering giving 28 pairs of permutations:

(x₁,x₂)₀,(x₁,x₃)₁,(x₁,x₄)₂,(x₁,x₅)₃,(x₁,x₆)₄,(x₁,x₇)₅,(x₁,x₈)₆,(x₂,x₃)₇,(x₂,x₄)₈,(x₂,x₅)₉,(x₂,x₆)₁₀,(x₂,x₇)₁₁,(x₂,x₈)₁₂,(x₃,x₄)₁₃,(x₃,x₅)₁₄,(x₃,x₆)₁₅,(x₃,x₇)₁₆,(x₃,x₈)₁₇,(x₄,x₅)₁₈(x₄,x₆)₁₉,(x₄,x₇)₂₀(x₄,x₈)₂₁,(x₅,x₆)₂₂,(x₅,x₇)₂₃,(x₅,x₈)₂₄,(x₆,x₇)₂₅,(x₆,x₈)₂₆,(x₇,x₈)₂₇。

when the jth doublet (x)_α,x_β)_jWhen the ith 4-tuple in set B occurs, at L₂(D) The ith row and the jth column of the matrix show a 1 element when (x)_α,x_β)_jWith B_iWhen there is no intersection between the elements of (1), L₂(D) The corresponding position in the matrix is 0 element, thereby constructing L₂(D) The incidence matrix (14) is set to 14 × 28L in the form of x × y₂(D) The matrix acts as H_dThe base matrix P of the matrix.

Q is 29 and is greater than L₂(D) The correlation matrix column number y is 28, which is the minimum prime number, and a positive integer matrix V with q × q 29 × 29 is constructed by addition in the prime subfield GF (29), as shown in equation (15). Taking the x × y-14 × 28 matrix from the positive integer matrix V as H_dFull element shift matrix S of matrix_FThe intercepting mode is upper left14 rows and 28 columns of corners, resulting in S_FThe matrix is shown in formula (16).

A base matrix P having a dimension of (14) x × y of 14 × 28 and a full-element shift matrix S having a dimension of (16) x × y of 14 × 28_FCarrying out generalized Hadamard product to obtain sparse shift matrix S_HSee formula (17). To S_HExpanding the matrix, filling the positive integer value with the corresponding L × L-dimensional permutation matrix, filling the-1 with the L × L-dimensional all-zero matrix, and obtaining the H_dMatrix and form H ═ H_dH_p]And the matrix is an irregular IRA-QC-LDPC code with the code length of N, K, M, 28L, 14L, 42L, the code rate of R, 28L, 42L, 2/3, the maximum column weight of 3, the row weight of 8, the weight of the first row of 7 and no four-line cycle.

The IRA-QC-LDPC code can form a 14-parallel L-bit linear serial encoder, data is input to an L-long information bit register in series by an L-long input buffer array, and 28 data lines I₁,I₂,...,I₂₈And (4) parallel transmission. In one coding period, 3 × y is 3 × 28L long circular left shift registers, 3 × 28 enable signals are provided, and 28L long information bit registers each having 3 units of output data output 3 × 28 data to the data line interleaving network. The data line interweaving network consists of 28 × L data lines, and in one coding period, there is 3 × 28 ═ w_xX 6 x 14 data are transmitted over a data line interleaved network. A total of 14 double summation processing units are executed in parallel, and each double summation processing unit performs double summation in one coding cycleAnd the processing unit receives the data wire from the data wire interleaving network w_xStore w as 6 data_xIn a bit shift register, and then summed by a one-bit accumulator to complete

Calculating, storing the calculation result in a feedback self-adder, and simultaneously emitting an enable signal E₁,E₂,...,E₁₄When E is₁,E₂,...,E₁₄When both are 1, the and gate of the enable signal generator outputs an enable signal E equal to 1. The enable signal makes 3 × y-3 × 28-84L long loop left shift registers loop left once in parallel, starts the next coding period, and repeats the above process to obtain the next coding period

And sending the result to a feedback self-adder to be fed back and self-added with the previous storage result to obtain the calculation result of the next check bit.

It will be appreciated by those skilled in the art that the foregoing is only a preferred embodiment of the invention, and is not intended to limit the invention, such that various modifications, equivalents and improvements may be made without departing from the spirit and scope of the invention.

Claims (7)

1. A partial parallel coding method of IRA-QC-LDPC codes is characterized by comprising the following steps: sparse parity check matrix H ═ H_d H_p]The blocking feature of (a) is in particular that the K-long information sequence to be encoded is divided into y segments, denoted d ═ d₁...d_j...d_y]Wherein d is_j＝[d_j,1,d_j,2,...,d_j,L]Is a binary information vector of length L; the M long check sequence to be solved is divided into x segments, denoted p ═ p₁...p_i...p_x]Wherein p is_i＝[p_i,1,p_i,2,...,p_i,L]Is a binary check vector of length L; the coded code word sequence is c ═ d p]＝[d₁...d_j...d_y p₁...p_i...p_x](ii) a Said H_dAnd H_pThe block feature and code of^TWhen 0, we derive x independent matrix equations:

wherein,

represents H_dA block submatrix of the matrix; q_iRepresents H_pA block sub-matrix on a diagonal; t represents the transpose of a matrix or vector; each matrix equation forms an independent linear serial coding algorithm;

when H is present_dColumn weight w of the matrix_yWhen being equal to 3, then

Is shown simplified as

The symbol i denotes the index of x matrix equations, i 1, 2.., x; the symbol j represents y partitioned submatrix indexes in the ith matrix equation, and j is 1, 2. The symbols m and l represent their respective sub-matrices

M, L ═ 1,2, ·, L; g is H1, 2,3_dAn index of matrix column weight 3; in the ith linear equation of the x independent matrix equations, a check vector p_i＝[p_i,1,p_i,2,...,p_i,L]The calculation expression of (a) is:

calculating the check bits of the first row by a recursive summation expression

Calculating subsequent L-1 check bits, each check bit only needing to complete line weight w_xAddition and one-time recursive superposition of data, wherein m is 2,3, and L represents L check bits p of each independent matrix equation_m,iTo compute serially, i 1,2, x denotes that there are x independent equations to complete L serial parity bits p in parallel_m,iCalculating (1);

the algebraic structure obtaining method of the IRA-QC-LDPC code comprises the following steps:

the M multiplied by N dimension sparse parity check matrix is designed into a system structure H ═ H_d H_p]H in dimension of M × K × xL × yL corresponding to information bit_dThe matrix is designed into a block submatrix structure with x y L x L dimensions, each block submatrix is a permutation matrix or an all-zero matrix, and M x M (x M) x L dimensions corresponding to the check bits are a dual diagonal matrix H_pDecomposed into x × x L-dimensional block submatrices, x block submatrices on the diagonal being a dual diagonal structure; said H_dMatrix is composed of two compact matrices with smaller size and x y dimension base matrix P and sparse shift matrix S_HRepresents;

the base matrix P is represented by t- (v, k, lambda) in the combined mathematics_t) Constructing a designed incidence matrix; number of rows of the incidence matrix

Number of rows

Line weight

Column weight w_y(v-t +1)/(k-t +1) where t, v, k, λ_tIs a positive integer and satisfies v > k > lambda_t，λ_t＝1；

The sparse shift matrix S_HFrom a base matrix P and a full element shift matrix S_FDetermining that an addition operation (alpha x beta) modq on the pixel subfield GF (q) is introduced to construct a positive integer matrix of dimension q x q, and arbitrarily cutting the positive integer matrix of dimension x yFull element shift matrix forming S_FQ is the smallest prime number greater than y, α, β ═ 0,1,2,. q-1;

the x y base matrix P and the x y full shift matrix S_FCarrying out generalized Hadamard product to generate the sparse shift matrix S with x y dimensions_H，S_HIs valued on GF (q) { -1 };

the sparse shift matrix S_HThe positive integer in (1) is extended by L × L permutation matrix, and the-1 is extended by L × L all-zero matrix to form H_dA matrix; the base matrix P is represented by t- (v, k, lambda) in the combined mathematics_t) The designed incidence matrix is constructed, and the parameters satisfy v ═ 3k-2t +2 and lambda_tWhen 1, a P matrix with column weights of 3 is generated; when the parameter t is 3, the number of rows of the base matrix P is

Number of rows

Line weight

Column weight w_y＝(v-t+1)/(k-t+1)＝3。

2. An encoder for an IRA-QC-LDPC code, the encoder comprising:

the y L long input buffer memory arrays are used for caching the K ═ yL bit information data sequence and starting the encoder to run, and when the information data of K ═ Ly is stored in the y multiplied by L input buffer memory array, the y L long information data are transmitted to the y L long information bit registers and are transmitted to the output end in series;

y information bit registers with length of L, when the information bit register receives the enable signal of '1', the data is output to the data line interweaving network, and when the enable signal is 0, the information is not output;

3 x y L long cycle left shift register arrays for accepting H_d3 x y L x L permutation moments contained in a matrixThe first row of the array completes the initialization of the encoder; the loop left shift register array completes the operation of loop left shift once in parallel under the control of an enable signal E being 1, and a '1' element in each left shift register is used as an enable signal to be output to y L-length information bit registers;

x double summation processing units for receiving information data from the data line interleaving network, wherein the one-bit accumulator firstly processes w_xAccumulating and summing the data, sending the summation result to a one-bit feedback self-adder, simultaneously generating an enable signal E, then accumulating by the one-bit feedback self-adder, storing the calculation result of the check bit, and simultaneously outputting the calculation result of the check bit to x L-long output buffer arrays;

the X L-long output buffer arrays respectively receive the check bits from the X double summation processing units, and sequentially output the information data sequence and the check data sequence through the multi-input single-output switch to form a coding output sequence;

the algebraic structure obtaining method of the IRA-QC-LDPC code comprises the following steps:

the M multiplied by N dimension sparse parity check matrix is designed into a system structure H ═ H_d H_p]H in dimension of M × K × xL × yL corresponding to information bit_dThe matrix is designed into a block submatrix structure with x y L x L dimensions, each block submatrix is a permutation matrix or an all-zero matrix, and M x M (x M) x L dimensions corresponding to the check bits are a dual diagonal matrix H_pDecomposed into x × x L-dimensional block submatrices, x block submatrices on the diagonal being a dual diagonal structure; said H_dMatrix is composed of two compact matrices with smaller size and x y dimension base matrix P and sparse shift matrix S_HRepresents;

the base matrix P is represented by t- (v, k, lambda) in the combined mathematics_t) Constructing a designed incidence matrix; number of rows of the incidence matrix

Number of rows

Line weight

Column weight w_y(v-t +1)/(k-t +1) where t, v, k, λ_tIs a positive integer and satisfies v > k > lambda_t，λ_t＝1；

The sparse shift matrix S_HFrom a base matrix P and a full element shift matrix S_FDetermining that an addition operation alpha multiplied by beta (modq) is introduced to a pixel subfield GF (q) to construct a positive integer matrix of q multiplied by q dimension, and arbitrarily cutting a full element shift matrix of x multiplied by y dimension from the positive integer matrix to construct S_FQ is the smallest prime number greater than y, α, β ═ 0,1,2,. q-1;

the x y base matrix P and the x y full shift matrix S_FCarrying out generalized Hadamard product to generate the sparse shift matrix S with x y dimensions_H，S_HIs valued on GF (q) { -1 };

the sparse shift matrix S_HThe positive integer in (1) is extended by L × L permutation matrix, and the-1 is extended by L × L all-zero matrix to form H_dA matrix;

the base matrix P is represented by t- (v, k, lambda) in the combined mathematics_t) The designed incidence matrix is constructed, and the parameters satisfy v ═ 3k-2t +2 and lambda_tWhen 1, a P matrix with column weights of 3 is generated; when the parameter t is 3, the number of rows of the base matrix P is

Number of rows

Line weight

Column weight w_y＝(v-t+1)/(k-t+1)＝3。

3. The encoder according to claim 2, wherein y L-long input buffer arrays in the encoder are specifically formed by y L-long random access memory units, and configured to buffer input information data to be processed, convert a serial input data sequence, a parallel input data sequence of 8-bit, 16-bit, or 32-bit bytes into a data sequence of segment length L and codeword length K ═ Ly, and store the data sequence, and after a first L-long input buffer is full, automatically store the data sequence into a second L-long input buffer until a y × L buffer array is full of information data of codeword length K ═ Ly; the L-long input buffer can arbitrarily truncate 8-bit, 16-bit or 32-bit bytes, and the L-long input buffer is filled by right shifting; the y L long input buffers respectively complete the output of the L bit data serial of the y input buffers in sequence through a data line, and the data is transmitted to the y L long information bit registers and output to the output end of the encoder in serial.

4. An IRA-QC-LDPC code encoder according to claim 2, characterized in that the 3 x y L long circular shift register arrays in the encoder are formed by 3 x y L long arrays of writable erasable ROM or flash memory cells arranged in y groups of 3L long circular shift registers each for storing H, respectively_dSetting initial values for an encoder for a first row of 3 × y block permutation matrices of dimensions lxl of the matrix; receiving an enable signal E, circularly and leftwards shifting 3 multiplied by y L-length circular left shift registers once, wherein each register has only one 1 element, and the rest elements are 0, and outputting 1 element as an enable control signal of the y L-length information bit registers; the 3 x y L long loop left shift registers run in parallel, and each encoding cycle issues 3 x y enable control signals.

5. The encoder of an IRA-QC-LDPC code according to claim 2, wherein y L long information bit registers in the encoder are formed by y L long random access memory cells, and the y L long information bit registers are serially inputted with L bits from y data lines; each data storage unit of each L-length information bit register is provided with 3 enabling signal control ends and a data output line; information bit register for use with H_dMultiplication of one row of block permutation matrix in matrixOperation, only one of 3 enabling signals of each unit is 1 in each coding period; in one coding period, y information bit registers work in parallel, each information bit register simultaneously outputs 3 data signals to a data line interleaving network, and 3y data signals are output in parallel.

6. An IRA-QC-LDPC code encoder according to claim 2, characterized in that the x double summation processing units in said encoder are composed of x double summers and an enable signal E generator; the dual summer includes w_xThe long shift register, the one-bit accumulator and the one-bit feedback self-adder are arranged in the long shift register; said w_xThe long shift register receives w from the data line interleaving network_xThe data are sent to the one-bit accumulator to be accumulated and summed, the calculated result is stored in the feedback self-adder, and an enable signal E is sent out at the same time₁,E₂,...,E_xThe feedback self-adder carries out one-time circular feedback self-addition on the newly stored data, saves the calculation result of the check bit and transmits the saved current value to the output buffer; the enable signal E generator is composed of an AND gate, and when x enable signals E are generated₁,E₂,...,E_xWhen both are 1, the enable signal generator output E ═ 1, where w_xLine weight is indicated.

7. An IRA-QC-LDPC code encoder according to claim 2, characterized in that the x L long output buffer arrays in said encoder are composed of x L random access memory RAM units; the wiring form is to form x L long serial shift memories, first in first out; and the output end of the output buffer array sequentially outputs the information data sequence and the check data sequence through a multi-input single-output switch to form a coding output sequence.

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