CN107786211A - A kind of Algebraic Structure acquisition methods, coding method and the encoder of IRA QC LDPC codes - Google Patents

Abstract

The invention discloses a kind of the Algebraic Structure acquisition methods of IRA QC LDPC codes, part parallel coding method and encoder.Present invention relates particularly to Sparse Parity-check Matrix H=[H_d H_p] information bit corresponding to H_dMatrix algebra structure obtaining method：By Combinational Mathematics t (v, k, λ_t) incidence matrix in design is set as H_dThe basic matrix P of x × y dimensions of matrix, when parameter meets λ_tDuring=1 and v=3k 2t+2, H_dMatrix column weight is 3；Add operation on limited sub-prime domain GF (q) is used to design full first shift matrix S_F, by basic matrix P and full first shift matrix S_FMake Hadamard products, generate sparse shift matrix S_H, by S_HMatrix extends to obtain H with L × L permutation matrix or L × L full null matrix_dMatrix；By the H of double diagonal line structure_pMatrix decomposition is L × L piecemeal submatrix, and x submatrix on diagonal is still dual diagonal matrix, forms the individual linear serial code algorithms that can be performed parallel of x；The invention also achieves a kind of encoder of IRA QC LDPC codes.Technical solution of the present invention significantly reduces the complexity of encryption algorithm, while also reduces the hardware description complexity of encoder.

Description

A kind of Algebraic Structure acquisition methods, coding method and the encoder of IRA-QC-LDPC codes

Technical field

The invention belongs to communications channel coding technology field, more particularly, to a kind of generation of IRA-QC-LDPC codes Table structure acquisition methods, parallel encoding method and encoder.

Background technology

Low-density checksum (LDPC) code is defined as Sparse Parity-check Matrix H kernel, i.e. Hc^T=0, wherein H Parity matrix is represented, c represents the transposition of codeword sequence, T representing matrixs or vector.Gallager is proposed first within 1962 LDPC code, and its iterative decoding algorithm, but do not provide the building method and encryption algorithm of H-matrix.1995 after more than 30 years Year, it is a kind of good code for approaching shannon limit that Mackay excavates LDPC code again.Hui Jin in 2001 after 6 years are in its doctor Rule is proposed in paper to repeat accumulation (RA) code and irregularly repeat to accumulate (IRA) code, and is demonstrated RA codes in theory and existed Shannon limit is reached on Gaussian white noise channel, IRA codes have reached shannon limit on punctured channel.At the beginning of invention, RA codes and IRA Code is regarded as a species Turbo code.Hereafter, researcher is analyzed its parity matrix, it is found that IRA codes are one The LDPC code of class random structure of the kind with Natural linear serial encoder.Its linear serial codified feature shows as verifying Parity matrix corresponding to position has double diagonal line structure, and its class random character shows as even-odd check corresponding to information bit Matrix is random structure.

At present, in communication industry standard, there is linear codified, system architecture practical LDPC code to be broadly divided into two Class, its corresponding parity check matrix H=[H_d|H_p] also there are two kinds of typical structures.One kind is quasi-circulating low-density parity check (QC-LDPC) code, its parity matrix that is mainly characterized by are made up of piecemeal submatrix, matrix H corresponding to its information bit_d's Piecemeal submatrix is collectively formed by n × n circulant-shift permutation matrix and n × n full null matrix, matrix H corresponding to check bit_p Piecemeal submatrix mainly there is unit matrix, full null matrix and permutation matrix to collectively form, H_pTypical structure be approximate under Triarray structure, using the teaching of the invention it is possible to provide uniform enconding algorithm.Because the QC-LDPC partitioned organization based on cyclic permutation matrices is favourable In the design of the part parallel hardware circuit of encoder and decoder, therefore, by the industrial standard of multiple series of IEEE 802 Adopted.Another kind is IRA-LDPC codes, and it is mainly characterized by matrix H corresponding to information bit_dIt is class random structure, its algebraically Architectural feature and unobvious, it is therefore desirable to store the largely positional parameter on 1 element, matrix H corresponding to its check bit_pIt is Double diagonal line structure, serial linear encryption algorithm can be provided, therefore, be also applied in multiple industrial standards, main bag Include：European second generation digital broadcast television standard DVB-S2, and People's Republic of China's GJB (GJB 7296- 2011) etc..

The code used in a standard, it is respectively provided with the random frame structure of class.Class is with the characteristics of machine frame：As code check and code length Such structural parameters, and parameter as the distribution of the row weight and row weight of parity matrix be to determine, these Parameter constitutes the framework of H-matrix determination；And the particular location distribution of " 1 " element is uncertain in H-matrix, but it is distributed Constrained by frame structure.Therefore, the H-matrix of the random executable code of class in standard, it is more likely that be in corresponding framework about Under beam, search for what is obtained by computer optimization.The H-matrix that so search obtains, which result in partial parameters, to be needed to be previously stored, Occupy internal storage location.Such as in ieee standard, QC-LDPC codes need to store cyclic shift value matrix, all 1 in H-matrix The distribution of element is determined by these cyclic shift values.And in European satellite communication standard, the H of IRA-LDPC codes_dMatrix also takes It is different from the cyclic shift feature of QC-LDPC codes from certain, but needs the parameter that stores far more than QC-LDPC codes；Due to China H in military's standard_dMatrix does not have cycle specificity, therefore the parameter stored is more than the IRA- in European satellite communication standard again The parameter of storage required for LDPC code.

The content of the invention

For the disadvantages described above or Improvement requirement of prior art, the invention provides a kind of algebraically of IRA-QC-LDPC codes Structure obtaining method, coding method and encoder, its object is to by Combinational Mathematics t- (v, k, λ_t) incidence matrix in design It is set as H_dThe basic matrix P of x × y dimensions of matrix, when parameter meets λ_tDuring=1 and v=3k-2t+2, H_dMatrix column weight is 3； Add operation on limited sub-prime domain GF (q) is used to design full first shift matrix S_F, by basic matrix P and full first shift matrix S_F Make Hadamard products, generate sparse shift matrix S_H, by S_HMatrix extends to obtain H with L × L permutation matrix or full null matrix_dSquare Battle array；Thus the complexity of encryption algorithm is significantly reduced, while also reduces the complexity of encoder.

To achieve the above object, according to one aspect of the present invention, there is provided a kind of Algebraic Structure of IRA-QC-LDPC codes Acquisition methods, methods described include：

The Sparse Parity-check Matrix of M × N-dimensional is designed to system architecture H=[H_d H_p], M × K=corresponding to information bit The H of xL × yL dimensions_dThe piecemeal submatrix structure that matrix design is tieed up into x × y L × L, each piecemeal submatrix be permutation matrix or Full null matrix, the dual diagonal matrix H of M × M=xL corresponding to check bit × xL dimensions_pIt is broken down into the piecemeal of x × x L × L dimension Submatrix, x piecemeal submatrix on the diagonal is double diagonal line structure；The H_dMatrix is compact with smaller two The basic matrix P and sparse shift matrix S of matrix x × y dimensions_HRepresent；

T- (v, k, λ in the basic matrix P Combinational Mathematics_t) design incidence matrix construction；The row of the incidence matrix Number is indexed by the quantity of the k- tuples in v element and determined, columns is indexed by the quantity of the t-1 tuples in v element and determined, tool Body is calculated as：Line numberColumnsRow weightWith row weight w_y=(v-t+1)/(k-t+1), Wherein t, v, k, λ_tIt is positive integer, and meets v ＞ k ＞ λ_t, λ_t=1；

The sparse shift matrix S_HBy basic matrix P and full first shift matrix S_FIt is determined that introduce adding on sub-prime domain GF (q) Method computing α × β (mod q) come construct q × q dimension positive integer matrix, from the positive integer matrix arbitrarily interception x × y dimension expires First shift matrix forms S_F, q is greater than y least prime, α, β=0,1,2 ..., q-1；

Full first shift matrix S of basic matrix P and the x × y dimension of x × y dimensions_HGeneralized Hadamard product is carried out, it is raw Into the sparse shift matrix S of x × y dimensions_H, S_HElement on GF (q) ∪ { -1 } value；

The sparse shift matrix S_HIn positive integer extended with L × L permutation matrix, -1 is expanded with L × L full null matrix Exhibition, form H_dMatrix.

Further, t- (v, k, λ in the basic matrix P Combinational Mathematics_t) design incidence matrix construction, parameter meet V=3k-2t+2 and λ_tWhen=1, the P matrixes that row weight is 3 are produced；During parameter t=3, then the line number of the basic matrix PColumnsRow weightRow weight w_y=(v-t+1)/ (k-t+1)=3.

It is another aspect of this invention to provide that providing a kind of coding method of IRA-QC-LDPC codes, methods described is specific For：

Sparse Parity-check Matrix H=[H_d H_p] blocking characteristic specifically, the information sequence of K to be encoded length is divided into Y sections, it is expressed as d=[d₁...d_j...d_y], wherein d_j=[d_j,1,d_j,2,...,d_j,L] it is that the binary message that length is L is sweared Amount；The verification sequence of M length to be solved is divided into x sections, is expressed as p=[p₁...p_i...p_x], wherein p_i=[p_i,1, p_i,2,...,p_i,L] it is the binary system check vector that length is L；Codeword sequence after coding for c=[d p]= [d₁...d_j...d_yp₁...p_i...p_x]；The H_dAnd H_pBlocking characteristic and code definition expression formula Hc^T=0, release x solely Vertical matrix equation：

Wherein,Represent H_dPartitioning of matrix submatrix；Q_iRepresent H_pPiecemeal submatrix on diagonal；T representing matrixs Or the transposition of vector；Each matrix equation forms independent linear serial code algorithm；

Work as H_dMatrix column weight w_y=3, then It is simplified shown asSymbol Number i represents the index of x matrix equation, i=1,2 ..., x；Symbol j represents y piecemeal submatrix rope in i-th of matrix equation Draw, j=1,2 ..., y；Symbol m and l represent it in submatrix respectivelyIn line index and column index, m, l=1,2 ..., L；G=1,2 .., w_y=1,2,3 be H_dThe index of rectangular array weight 3；I-th of linear equation of the x independent matrix equations In, check vector p_i=[p_i,1,p_i,2,...,p_i,L] calculation expression beThe check bit of the first row is by passing Return summation expression formulaCalculate, pass through the follow-up L-1 check bit of recurrence read group total, each check bit Row weight w only need to be completed_xThe addition of individual data and a recurrence superposition, wherein m=2,3 ..., L represent each independent square Battle array equation has L check bit p_m,iSerial computing, i=1 are wanted, 2 ..., x indicates that x independent equation concurrently completes L serially Check bit p_m,iCalculating.

It is another aspect of this invention to provide that providing a kind of encoder of IRA-QC-LDPC codes, the encoder includes：

The input buffer array of y L length, for the caching of K=yL positions information data sequence, and start encoder fortune OK, when K=Ly information data is filled with y × L input buffer arrays, then y L long messages data transfer to y L is grown Information bit register, while serial transfer is to output end；

The information bit register of y L length, when it is " 1 " that information bit register, which receives enable signal, then by data output extremely Data wire interleaving network, when the enable signal received is 0, then not output information；

3 × y L long circulating moves to left register array, for receiving H_dThe displacement square for 3 × y L × L that matrix is included The first row of battle array, completes the initialization of encoder；The ring shift left register array under enable signal E=1 control, and Row completes the operation of ring shift left once, and " 1 " element each moved to left in register exports what is grown to y L as enable signal Information bit register；

X double summation process units, for receiving the information data from data wire interleaving network, one therein cumulative Device is first to w_xIndividual data carry out cumulative summation, and summed result is delivered into a feedback adds device certainly, while generates enable signal E, Then add device to carry out the cumulative of itself certainly by a feedback, and preserve the result of calculation of check bit, while check bit is calculated and tied Fruit is exported to the output state array of x L length；

The output state array of x L length, the check bit from x double summation process units is received respectively, by entering more Singly go out switch, information data sequence and the verification of data sequences are sequentially output, form encoded output sequence.

Further, the random memory unit that the input buffer array of y L length is specifically grown by y L in the encoder Form, for caching the pending information data of input, by serial input data sequence, 8,16 or 32 bit bytes it is parallel Input data sequence is converted to section length L and code word size K=Ly data sequence storage, the input of first segmentation L length After buffer is filled with, second segmentation input buffer is automatically credited, until a long K=Ly of code word information data is filled with y × L cache arrays；The input buffer of the L length can arbitrarily be blocked to 8,16 or 32 bit bytes, by moving to right Input buffer full of L length；The long input buffers of y L are each sequentially completed y input-buffer by a data lines respectively The output of device L positions serial mode, pass data to y L length information bit register and Serial output to encoder output End.

Further, 3 × y L long circulating moves to left the writable and eresable that register array is grown by 3 × y L in the encoder The ROM or flash memory cell array removed is formed, and is arranged in y groups, the ring shift left register of every group of 3 L length, is respectively used to store H_d The first row of the piecemeal permutation matrix of 3 × y L × L dimensions of matrix, initial value is set for encoder；Receive enable signal E, 3 × y L The long equal ring shift left of ring shift left register once, only has 1 element, remaining element is all 0, defeated in each register Go out enabled control signal of 1 element as the y L information bit registers grown；The ring shift left deposit of the 3 × y L length Device is run parallel, and each code period sends 3 × y enabled control signals.

Further, the information bit register of y L length is made up of the y L random memory units grown in the encoder, y The information bit register of individual L length inputs information data by y data lines L Bits Serials；Each the information bit register of L length is every Individual data storage cell has 3 enable signal control terminals and a single data output line；Information bit register is used for and H_dIn matrix A line of piecemeal permutation matrix do multiplying, each code period, it is 1 that 3 enable signals of each unit, which only have one,； In a code period, the work of y information bit register, each information bit register export 3 numbers simultaneously it is believed that Number data wire interleaving network is arrived, altogether 3y data-signal of parallel output.

Further, x double summation process units are produced by x double summers and an enable signal E in the encoder Raw device composition；Double summers include w_xLong shift register, a bit accumulator and a feedback add device certainly；The w_xIt is long to move Bit register receives the w from data wire interleaving network_xIndividual data, and be sent into a bit accumulator and carry out cumulative summation meter Calculate, result of calculation deposit feedback is simultaneously emitted by enable signal E from adding in device₁,E₂,...,E_x, feedback from plus device to being newly stored in Data carry out one cycle feedback and added certainly, and preserve the result of calculation of check bit, and it is slow that the currency preserved is delivered into output In storage；The enable signal E generators, formed by one with door, as x enable signal E₁,E₂,...,E_xWhen being 1, make Can signal generator output E=1, wherein w_xRepresent row weight.

Further, the output state array that x L grows in the encoder is by x × L random storage ram cell group Into；Connection type is to form the long serial shift memories of x L, FIFO；The output end of the output state array passes through Enter more and singly go out switch, information data sequence and the verification of data sequences are sequentially output, form encoded output sequence.

In general, by the contemplated above technical scheme of the present invention compared with prior art, have following technology special Sign and beneficial effect：

(1) matrix H of the present invention_dUsing t- (v, k, the λ in Combinational Mathematics_t) design, the odd even school corresponding to information bit can be made The maximum column weight for testing matrix is 3, with ieee standard quasi- circulation QC structures H-matrix compared with, the number of its " 1 " element Amount has reached minimum level, compared with the H-matrix of IRA-LDPC codes in European satellite communication standard, in close code length and same code In the case of rate, H_dThe quantity of " 1 " element has 20%-30% reduction in matrix, therefore, significantly reduce encryption algorithm and The computation complexity of decoding algorithm, while also reduce the hardware complexity of encoder and decoder；

(2) H of the present invention_dMatrix is to be based on quasi-cyclic piecemeal submatrix structure, the double diagonal line H matched_pMatrix also can Block form is designed to, causes encoder to carry out part parallel encoder design according to partitioned organization, significantly reduces The execution time of encoder；

(3) structure of H-matrix of the present invention combines the design feature of both IRA-LDPC codes and QC-LDPC codes, can picture QC-LDPC codes equally realize the part parallel processing of decoder hardware circuitry, base of the and can in IRA code division block double diagonal line structures Part parallel uniform enconding is carried out on plinth, encoder and decoder reduce hardware implementation complexity and delay.

Brief description of the drawings

Fig. 1 is the schematic block circuit diagram of inventive encoder；

Fig. 2 is inventive encoder input buffer array circuit theory diagram；

Fig. 3 is inventive encoder information bit register circuit theory diagram；

Fig. 4 is inventive encoder ring shift left register array schematic block circuit diagram；

Fig. 5 is the double summation process element circuit theory diagrams of inventive encoder；

Fig. 6 is inventive encoder output state array circuit theory diagram.

Embodiment

In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, not For limiting the present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below that Conflict can is not formed between this to be mutually combined.

First introduce the general principle of the present invention：

Parity matrix has system architecture, i.e. H=[H in the present invention_d|H_p], wherein H_pMatrix has following piecemeal double Diagonal structure,

Each of which submatrix is identical L × L double diagonal line square formation,

H_dMatrix is M × K=xL × yL matrix in block form forms,

Wherein subscript a_i,jCyclic shift value is represented, when span is a_i,jDuring ∈ { 0,1,2 ..., L-1 }, submatrixIt is L × L permutation matrix, therefore a_i,jThe position coordinates where the first row " 1 " element of L × L permutation matrix is also illustrated that, This L × L permutation matrix presses row ring shift right a by L × L unit matrixs_i,jIt is secondary to obtain；Work as a_i,jWhen=- 1,It is L × L Full null matrix, i=1,2 ..., x, j=1,2 ..., y.

If from H_dPermutation matrix is extracted out in matrix, H_dTwo matroids, the i.e. basic matrix of x × y dimensions can be further reduced to The shift matrix S of P and x × y dimensions.The constituted mode of P matrixes is：When being permutation matrix, the submatrix in (3) formulaWith 1 Element substitutes；WhenWhen being full null matrix, submatrixSubstituted with 0 element, therefore, P matrixes can be write as P=[p_i,j], p_i,j∈ { 0,1 }, i=1,2 ..., x, j=1,2 ..., y.The constituted mode of s-matrix is：By (3) formula H_dThe subscript of matrix carries The shift matrix S for forming following x × y dimensions is taken out,

If all a_i,j∈ { 0,1,2 ..., L-1 }, then S is to expire first shift matrix, by S_FRepresent.If there is certain A bitSo S is sparse shift matrix, by S_HRepresent.Here one of main task is design H_dSquare Sparse shift matrix S corresponding to battle array_H, and require H_dMeet that ranks constrain with H, i.e., without 4 girths.

The present invention comes with mathematical tools such as Combination Design, the mould n computings of finite field levels and generalized Hadamard products Design H_dMatrix.Construct H_dThe basic ideas of matrix are：First with the Steiner series structures H of Combination Design_dThe group moment of matrix Battle array P；H is constructed using the mould n computings of finite field levels_dFull first shift matrix S of matrix_F；Then moved by basic matrix P and full member Bit matrix S_FMake generalized Hadamard product, try to achieve sparse shift matrix S_H；Finally gone with L × L permutation matrixes and L × L full null matrix Extend S_H, obtain H_d。

The present invention, which is described first below, needs 3 basic mathematical instruments using, including Combination Design Steiner systems, by Addition mould n computings on sub-prime domain GF (q) produce q × q positive integer matrix and not on same area two matrixes Quadrature methods, i.e., Generalized Hadamard product.

Combination Design Steiner systems basic theories：

The present invention Combination Design Steiner systems to be used are described as follows.

Define 1：If t, v, k, λ_tIt is positive integer, and meets v ＞ k ＞ λ_t.In the presence of a two tuple D=(X, B), X is one V metasets, B={ B₁,B₂,...,B_bIt is the set for including b k tuple, the set meets following condition：

(a)|B_i|=k, 1≤i≤b；

(b) to any one t tuple on X, the number comprising the t tuples is constant λ in B_t；

It is t- (v, k, a λ on set X then to claim B_t) design, wherein B_iA packet in referred to as set B；To parameter λ_t=1 t designs are also known as Steiner systems, are expressed as S (t, k, v).

Theorem 1：If D=(X, B) is t- (v, k, a λ_t) design, μ is arbitrary integer in [0, t], then to X any μ Tuple, the packet count δ of the μ tuples is included in B_μIt is calculated as follows：

As μ=0, t- (v, k, λ_t) design packet count be

Present invention provide that λ_t=1, if D=(X, B) represents an arbitrary t- (v, k, 1) or Steiner systems S (t, k, v) Design, (t-1) incidence matrix for defining two tuple D is L_t-1(D)=(l_i,j), l_i,j∈ { 0,1 }, binary matrix L_t-1(D) Line number be equal to set B packet count b, columns be equal to set X v element in all t-1 tuples quantity；And if only if with When the member in element k tuples corresponding with the i-th row in (t-1) tuple corresponding to jth row is known as common factor, l_i,j=1；Otherwise l_i,j =0.As can be seen here, matrix L_t-1(D) haveOK,Row, and there is equal row weight w_r= λ_t(v-t+1)/(k-t+1) and equal row weightLine index is i=1,2 ..., b, column index j=1, 2 ..., r, i.e. matrix L_t-1(D) be b × r dimension matrix.

Because the degree of rarefication of application claims parity matrix reaches minimum level, to make H=[H_d|H_p] matrix " 1 " number of elements reaches minimum degree with all compared with LDPC code, it is therefore an objective to is reached by reducing the quantity of " 1 " element Reduce the implementation complexity of codec.Provide H_dThe maximum column weight configuration of matrix is 3, that is, sets w_r=(v-t+1)/(k-t+1) =3, thus try to achieve v=3k-2t+2.In other words, when parameter t, v, k positive integer value meet v=3k-2t+2, by Steiner systems S (t, k, v) two tuple D=(X, B) incidence matrix L_t-1(D) H constructed_dMatrix meets maximum column weight For 3 constraints.

Lemma 1：If D=(X, B) is a S (t, k, v), then matrix L_t-1(D) meet that ranks constrain.

In lemma 1, meet that ranks constraint is meant that：The L being defined on binary field_t-1(D) matrix encloses not comprising 4 Line (i.e. without 4-girth).L_t-1(D) the reason for meeting ranks constraint is regulation parameter lambda_t=1.

Finite field gf (q) basic theories：

Present invention provide that constructing positive integer matrix on limited sub-prime domain GF (q), its method is described as follows.

In order to construct full first shift matrix S_F, it is necessary to design positive integer matrix.Roughly, when q is prime number, GF (q) The finite field of q element is represented, the addition on GF (q) and multiplication are defined as below：

Define 1：To each a ≠ 0, a ∈ GF (q), meet na=0 minimum positive integer n, referred to as field element a feature. Element a so in domain, there is following form under addition and multiplication：

Multiplication：a,a²,a³,...,a^m=1, a, a²..., wherein m is a feature.

Addition：A, 2a, 3a ..., na=0, a, 2a ..., wherein n is a feature.

From the foregoing, it will be observed that for addition, all elements also form circulation Abel and add group in sub-prime domain.

According to define 1 add operation on sub-prime domain GF (q), may be constructed q × q matrix V, if V line index by The multiple value of add operation is formed, if with α=0,1,2 ..., q-1 represents a different multiples, if V column index is transported by addition The value a ∈ GF (q) of calculation={ 0,1 ..., q-1 } is formed, if with β=0,1,2 ..., q-1 represents a different values, thus structure Into q × q matrix V=[α × β] (mod q).

It is worth noting that full first shift matrix S_FAnd the value on positive integer domain, therefore, as long as considering S_FSize Restricted problem, i.e. S_FIt is the positive integer matrix of x × y dimensions, then intercept S in the positive integer matrix V that can is tieed up from q × q_FMatrix. Another constraints for needing to consider is the girth feature of positive integer matrix V.Following theorem 3 and inference 1 gives just whole Matrix number V girth feature.

Theorem 3：If q is prime number, if being gone to extend q × q positive integer square with dimension q × q binary system permutation submatrix Battle array V, then the matrix on GF (2) obtained by after extension is to meet that ranks constrain, i.e., without 4 contours of closure in matrix (girth)。

Inference 1：If q is prime number, L is the prime number more than q, is gone to extend q × q positive integer with dimension L × L permutation matrix Matrix V, resulting matrix meets that ranks constrain after extension.

Reasoning 1 shows if L is prime number, is gone to extend q × q positive integer matrix V institute with L × L binary system permutation matrix Obtained binary matrix necessarily meets that ranks constrain, and can serve as the parity-check matrix of LDPC code；If L is not to be element Number, then the binary matrix after extension cannot be guaranteed to meet that ranks constrain.

Generalized Hadamard product：

Present invention provide that basic matrix P and full first shift matrix S on positive integer domain on binary field GF (2)_FDo multiplication, To form the sparse shift matrix S for meeting ranks constraint_H.The concept of generalized Hadamard product is introduced for this.

If matrix U=[u_ij] it is the binary matrix that x × y is tieed up, if matrix V=[v_ij] it is the positive integer matrix that x × y is tieed up. Define generalized Hadamard product W=[w_ij]=UV=[u_ij][v_ij] so that working as u_ijWhen=1, w_ij=v_ij, show w_ijIt is just whole Number, when the matrix being extended to the matrix W on positive integer domain in binary field, w_ijSubstituted with permutation matrix；Work as u_ijWhen=0, If w_ij=-1, shows w_ijIt is not positive integer, then use -1 represents, is extended to when by the matrix W on positive integer domain in binary field When, w_ijSubstituted with full null matrix.

As can be seen here, the generalized Hadamard product defined here is on two multiplication of matrices fortune on different two domains Calculate, its operation result is to produce sparse positive integer matrix, and two domains here refer to binary field and positive integer domain.By above-mentioned side The matrix W that method obtains is sparse, as long as U=[u_ij] and V=[v_ij] meeting that ranks constrain, then W necessarily meets ranks about Beam.Therefore, matrix W can be used for constructing sparse shift matrix S_H。

A kind of complete Algebraic Structure acquisition methods of IRA-QC-LDPC codes, comprise the following steps：

(1) the Sparse Parity-check Matrix H of IRA-QC-LDPC codes structure is designed：Specific method is that matrix H has M × N The system architecture of dimension, i.e. H=[H_d|H_p], wherein M × K=xL corresponding to information bit × yL dimension matrix Hs_dWith quasi-cyclic piecemeal Submatrix architectural feature, H_dIt is made up of x × y piecemeal submatrix, the size of each piecemeal submatrix is L × L square formation, piecemeal The structure of submatrix can be the full null matrix of L × L dimensions or the binary system permutation matrix of L × L dimensions, and each permutation matrix is by unit Matrix circular moves to right a_i,jIt is secondary to obtain, as cyclic shift value a_i,jWhen=0, L × L permutation matrixes are unit matrixs；Work as span It is a_i,jDuring ∈ { 1,2 ..., L }, a_i,jThe coordinate position of " 1 " element is given in the first row of L × L permutation matrixes, by L × L The unit matrix of dimension presses row ring shift right a_i,jIt is secondary to obtain this L × L permutation matrix；Work as a_i,jWhen=- 1, H_ai,jIt is L × L complete Null matrix, i=1,2 ..., x, j=1,2 ..., y.M × M=xL corresponding to check bit × xL dimension matrix Hs_pIt is double right with piecemeal Diagonal structure feature, H_pIt is made up of x × x piecemeal submatrix, in H_pEach piecemeal submatrix on diagonal is the double of L × L dimensions Diagonal matrix, each piecemeal submatrix on off-diagonal are the full null matrix of L × L dimensions.

(2) M × K dimensions H is designed_dThe basic matrix P of x × y dimensions corresponding to matrix：Specific method be by Combination Design S (t, k, V) the incidence matrix L of two tuple D=(X, B) in Steiner systems_t-1(D) it is set as H_dThe basic matrix P of matrix, parameter designing is such as Under：If P=[p_i,j], i=1,2 ..., x, j=1,2 ..., y, p_i,j∈GF(2)；IfProvide the row of P matrixes Number；IfProvide P matrix column numbers；If w_y=(v-t+1)/(k-t+1) represents P matrix column weight；If Represent the row weight of P matrixes；Provide λ_t=1, P matrix do not include 4 contours；Regulation parameter t, v, k value meet expression formula v= 3k-2t+2, obtain H_dMatrix column weight is w_y=(v-t+1)/(k-t+1)=3；Provide the association in two tuple D=(X, B) Matrix L_t-1(D) in design, k tuple-sets B design obtains from Combinational Mathematics handbook and the research paper delivered, Can also designed, designed, as long as meeting λ_t=1 and v=3k-2t+2 all S (t, k, v) designs, are applied to the present invention；It is right The sequence regulation of all elements arranges according to lexicographic order in set B b k tuple, obtains set B={ B₁,B₂,...,B_b}； The design of the invention for especially emphasizing t=3, it is desirable to which parameter meets λ_t=1, t=3 and v=3k-4, corresponding incidence matrix, It is basic matrix P=L_t-1(D)=L₂(D).The columns of basic matrix byCalculate；Present invention provide that α ＜ β, and α, β ∈ [1, v], if several to (x_α,x_β)_aSubscript a represent two tuples sequence number, a=0,1 ..., v (v-1)/2-1, Element per number centering is from value in { 1,2 .., v } is gathered, and per number to being arranged according to lexicographic order, it is arranged general Form is：

The often distribution of row " 1 " element and the packet B corresponding to the row in basic matrix P_iThe above-mentioned binary that middle element is formed Group is relevant.With the 0th behavior example, packet count corresponding to the 0th row is B₁；B₁In include four element x₁, x₂, x₃, x₄.This 4 elements Form 6 two tuples, they it is above-mentioned it is several to several in sequence to form and its subscript serial number (x₁,x₂)₀, (x₁,x₃)₁, (x₁,x₄)₂, (x₂,x₃)₇, (x₂,x₄)₈, (x₃,x₄)₁₃, then in basic matrix the column of " 1 " element of the 0th row position by this 6 The subscript sequence number 0,1,2,7,8,13 of individual two tuple determines.

(3) M × K dimensions H is designed_dFull first shift matrix S of x × y dimensions corresponding to matrix_F：Specific method is to introduce finite field Add operation on GF (q) designs full first shift matrix S of x × y dimensions_F.If S_F=[s_i,j], i=1,2 ..., x, j=1, 2 ..., y, s_i,j∈GF(q).If q is greater than y least prime, q × q positive integer matrix V=[α × β] (mod q) is constructed, α, β=0,1,2 ..., q-1.X rows and preceding y row before being taken from q × q V matrixes, form full first shift matrix S of x × y dimensions_F。 Because the V matrixes being defined on sub-prime domain GF (q) meet that ranks constrain, so, intercept out x × y dimensions from q × q V matrixes S_FMatrix is also to meet what ranks constrained；X × y dimensions S is intercepted out from q × q V matrixes_FOther methods of matrix are：By x × y's Matrix regards a window as, and whole window frame can slide on q × q V matrixes, can arbitrarily be intercepted from q × q V matrixes Size is that x × y positive integer matrix serves as S_FMatrix.

(4) M × K dimensions H is designed_dThe sparse shift matrix S of x × y dimensions corresponding to matrix_H：If S_H=[w_i,j], i=1, 2 ..., x, j=1,2 ..., y, w_{I, j}∈GF(q)∪{-1}.X × y Wiki matrixes P and x × y are tieed up into full first shift matrix S_FEnter Row generalized Hadamard product, thus generate the sparse shift matrix S of x × y dimensions_H, present invention provide that S_H=P × S_F=[p_i,j× s_i,j]=[w_i,j], work as p_i,jWhen=1, w_i,j=s_i,j；Work as p_i,jWhen=0, w_i,j=-1.

(5) go to extend sparse shift matrix S with L × L piecemeal submatrixs tieed up_HTo design H_dMatrix：Specific method is to S_H =[w_i,j], i=1,2 ..., x, j=1,2 ..., y, w_{I, j}∈ GF (q) ∪ { -1 }, work as w_i,jDuring ∈ GF (q), by unit matrix Cyclic shift w_i,jIt is secondary, obtain corresponding to w_i,jL × L of shift value permutation matrix, works as w_i,j=-1, L × L full null matrix is formed, X × y so L × L permutation matrix and full null matrix are substituted into S_HIn corresponding element w_i,j, obtain M × K=xL × yL dimensions H_dMatrix.H_dThe line number of matrix isH_dMatrix column number isH_dThe row weight of matrix Measure and beH_dMatrix column weight is w_y=(v-t+1)/(k-t+1).By H=[H_d H_p] IRA-QC- that defines of matrix LDPC code has code length N=K+M=yL+xL, and code check is R=K/ (K+M)=y/ (y+x).

A kind of coding method of IRA-QC-LDPC codes, comprises the following steps：

For the IRA-QC-LDPC codes of the linear block codes of system form, such as present invention, the process of coding is actually With information sequence and H_dMatrix multiple calculates the process of verification sequence.Include double diagonal line H_pH=[the H of matrix character_d|H_p] Matrix has natural linear serial code algorithm, when serial code refers to calculate check bit, is the calculating of one one, calculates Current check bit is primarily due to work as H, it is necessary to use the result of calculation of a bit check position_pMatrix has double diagonal line knot During structure feature, the encryption algorithm released is recursive function in itself.If the time for calculating a bit check position is set as cycle T, Referred to as code period, then the time of serial computing M bit checks position is exactly MT.The present invention is by H_dMatrix design is piecemeal submatrix Form, it is the linear serial of LT by x calculation scale exactly in order to which from MT are shortened into LT the calculating time of serial code algorithm Encryption algorithm performs parallel, therefore the parallel execution algorithm of referred to as x linear serial code algorithms.It is parallel to perform x linear volumes The Concurrent Feature of code algorithm depends on H_dMatrix and H_pMatrix is made up of L × L piecemeal submatrix, and its linear character takes Certainly in H_pThe double diagonal line piecemeal submatrix of matrix still has double diagonal line architectural feature.

According to H=[H_d|H_p] partitioning of matrix feature, segmentation expression is carried out to information sequence to be encoded, K=yL length Information data sequence one is divided into y sections, is L per segment length, is designated as d=[d₁...d_j...d_y], wherein d_jIt is the binary system of L length Sequence of vectors.Equally, the verification bit sequence that will be solved is segmented, and the check bit data sequence one of M=xL length is divided into x Section, it is L per segment length, is designated as p=[p₁...p_i...p_x], wherein p_iIt is the binary sequence vector of L length.In the defeated of encoder Go out end by signal bit sequence d=[d₁...d_j...d_y] and verification bit sequence p=[p₁...p_i...p_x] merge, after being encoded Codeword sequence c=[d p]=[d₁...d_j...d_yp₁...p_i...p_x].According to Hc^T=0, obtain Hc^T=[H_d|H_p][d|p]^T= 0, H can be released_dd^T+H_pp^T=0, under the conditions of binary arithmetic operation, it can release：

H_dd^T=H_pp^T (6)

By (1) formula, (3) formula and sequence d=[d₁...d_j...d_y] and p=[p₁...p_i...p_x] bring (6) formula into, and according to (6) formula is expanded into following form by the form of matrix in block form：

(7) formula is further obtained into following x independent matrix sides by matrix in block form and the formal expansion of segmentation vector Journey：

Each of which matrix equation all comprising the L linear equations that are mutually related, forms a uniform enconding algorithm.This X independent matrix equations it is each, comprising L linear equation can be utilized respectively the double diagonal line that the x L × L on the right tie up Matrix Q₁,Q₂,...,Q_xThe check vector p that x length corresponding to solving is L₁...p_i...p_x.A matrix side is derived first Linear serial code algorithm caused by L independent linearity equation group in journey.From general angle, with x matrix Exemplified by i-th of matrix equation in equation, if j-th of vector representation that length is all in L y information sequence vector is d_j= [d_j,1,d_j,2,...,d_j,L]；If i-th of vector representation that length is all in L x check bit sequence of vectors is p_i=[p_i,1, p_i,2,...,p_i,L]；If j-th of L × L of i-th of matrix equation verification submatrixThere is following form：

WhereinUpper first symbol of target represents the index of x matrix equation, there is i=1,2 ..., x, second symbol Number represent that y piecemeal submatrix indexes in i-th of matrix equation, there is j=1,2 ..., y；Lower two element difference tables of target Show it in submatrixIn line index and column index, m, l=1,2 ..., L.Thus, i-th of matrix equation can in (8) formula To be write as lower column matrix formation：

By the 1st row of above-mentioned i-th of matrix equation, first linear side that i-th of matrix equation is included can be obtained First check bit p corresponding to journey_1,i

Remaining L-1 check bit p can similarly be obtained_m,i, m=2,3 ..., L

The solution expression formula of L check bit of i-th of matrix equation can be abbreviated as the summation table of following recursive more than Up to formula,

(10) formula and (11) formula constitute the linear serial code algorithm for calculating L check bit, wherein (10) formula calculates i-th The check bit of the first row of individual independent matrix equation, (11) formula represent recursively to calculate remaining L-1 of i-th of matrix equation Check bit, work as i=1,2 ..., x, can be by x independent linear serial code algorithm parallel computations.It is noted that calculate each Capable linear equation, actually calculates H_dA line of matrix and the product of K=yL positions information bit, then sum, as this again Sample calculates first check bit p of i-th of matrix equation with (10) formula first_1,i, (11) formula could be used to calculate second verification Position p_2,i, that is to say, that to calculate m-th of check bit, it is necessary to the m-1 check bit is first calculated, here it is linear recurrence calculating, Form linear serial code algorithm.

For λ_t=1 and v=3k-2t+2 Combination Design, corresponding to H_dMatrix column weight is w_y=3, row weight isDesign, H_dMatrix only has 3y=w_xX permutation matrix participates in the calculating of (10) and (11) formula.If H_dRectangular array The index of weight is g=1,2 .., w_y=1,2,3, then H_dThe element of permutation matrix can be simplified shown as in matrixDue to derivation be i-th of independent equation general expression, upper first symbol of target can save Slightly, lower first symbol of target is indexed using row weight, such H_dPermutation matrix in matrix can be arranged in 3 × y=w_x×x Array, (10) formula and (11) formula only have w_xIndividual product term participates in summation

(12) formula and (13) formula are by considering H_dThe situation of the openness of matrix, row weight and row weight simplifies calculating, Mainly H_dMatrix is not carried out in K=yL positions with the summation operation of K=yL positions information bit per a line, but works as H_dSquare When having 1 element in every a line of battle array, just need to calculate.It follows that the x independent matrix equations of (8) formula are deployed into by turn During calculating, the x linear serial code algorithms of (12) formula and (13) formula are formed.

A kind of encoder of IRA-QC-LDPC codes：

Multiplying is can also be seen that from (12) formula and (13) formulaIt need not calculate, because in L × L dimensions point In block submatrix, it is 1 there was only an element per a line, and remaining element is 0, therefore w_xItem multiplying is actually to retain to divide Information digit evidence in block submatrix corresponding to that element of each behavior " 1 ".Main calculating task is to complete summation fortune CalculateAnd this summation operation is also w_xItem summation, it is not the summation of L items.Further, since H_dThe structure of matrix is It is made up of cyclic shift submatrix, only needs to store the first of y L × L submatrix of each independent matrix equation in advance OK, remaining each row often comes a clock cycle under the code period control of setting, and ring shift right once, produces L × L dimension The next line of matrix.The schematic circuit construction of the parallel execution of x linear serial code algorithms is as follows：

Be as shown in Figure 1 encoder circuit the general frame, the schematic circuit bag of x linear parallel execution of serial encoder Include：Y × L input buffers array, information bit register, the 3 × y L long circulating of y L length move to left register array, x simultaneously Capable double summation process unit and x × L output state arrays.

Operation principle：By H_dThe first row deposit ring shift left for 3 × y known L × L permutation matrixes that matrix includes is posted Storage array, complete the initialization of encoder；Input K=yL positions information data sequence and start encoder, the long input-buffers of y L Device is filled with L long messages position, then can be from trend information bit register serial input data；The information bit register of y L length is filled with L After the data of position, then start to be H_dEvery a line of matrix and the multiplication of K=yL positions information bit and and read group total；Each circulation is left The corresponding units for moving unit to information bit register in register for 1 send enable signal, then the information data of the unit is defeated Go out；Each unit of L long message bit registers only has a data lines to be connected with x parallel double summation process units, each Double summation process units are connected with the six roots of sensation data wire from information bit register, therefore, in the information bit register of y L length L × y data lines interleaving networks are formed between x parallel double summation process units；3 × y L long circulating moves to left register Array is divided into y groups, and every group of 3 L long circulatings move to left register array, can be run parallel with the information bit register of y L length, 3 × y L long circulating move to left register each receive enabled control signal E, then ring shift left once, starts next verification The calculating process of position；In ring shift left each time, each information bit register has 3 unit output information datas to pass through number Be delivered to the parallel double summation process units of x according to line interleaving network, each code period, altogether 3 × y number of output it is believed that Breath；Each of x parallel double summation process units receives w_xIndividual data-signal, x × w is inputted altogether_x=3 × y signal； Each double summation process units complete two kinds of summation operations, are to w first_xIndividual data-signal carries out cumulative summation, completesCalculating, will try to achieve and be sent into feedback from plus device in preserves, be simultaneously emitted by enable signal E₁,E₂,...,E_x, when E₁,E₂,...,E_xWhen being all 1, export an enable signal E=1 and move to left register array to 3 × y L long circulating, it is parallel to complete One cycle moves to left, and starts to calculate next time；Complete H_dCertain a line of matrix is counted with the multiplication of K=yL positions information bit and summation Calculation is analyzed as follows, it is necessary to consume the clock cycle：Ring shift left register array receives enable signal, it is necessary to which a machine cycle enters Row ring shift left operates, and sends enable signal triggering information bit register output data, it is necessary to consume a machine cycle, starts First adder of double summation process units needs a clock cycle, and w is completed in adder_xAdding up for individual data, is needed Consume w_xThe individual machine cycle, therefore completeCalculating needs w_x+ 3 machine cycles, referred to as a code period.

It should be noted that input buffer array and the information bit register storage binary number of y L length that y L grows According to mode be lowest order on the right, highest order is on the left side, it is therefore desirable to which 3 × y L long circulating moves to left register array from the right side While start to store H_dThe first row of matrix, it was the permutation matrix of ring shift right originally, the circulating register in hardware design Need to be designed to ring shift left.

It is illustrated in figure 2 input buffer array, the RAM random access memory structures that y × L input buffers array is grown by y L Into for inputting the caching of pending information data, its function is by serial input data sequence or 8,16 or 32 The parallel input data sequence of bit byte is converted to the data sequence storage for being suitable for code length L and code word size K=Ly；Will 8,16 or 32 data transmitted from data parallel input port are sequentially stored into the input buffer of y L length, as first L After long input buffer is filled with, automatically into second input buffer, ensure the continuous uninterrupted storage of inter-area traffic interarea, Until a long K=Ly of code word information data is filled with y × L cache arrays, it is desirable to which buffer system can be to 8,16 Or 32 bit byte arbitrarily blocked, to meet the requirement being continuously filled with of the long buffers of L, L is likely to be prime number, is not word Section 2^eMultiple, e=3 here, 4,5；When code word K=Ly information is filled with y × L input buffer arrays, next K Long code word start be probably parallel one byte in input port a part, cache array can still store next successively K long code words.Only when K=Ly information is filled with y × L input buffer arrays, output operation, y L length input can be just carried out Each of buffer passes through respective data lines I respectively₁,I₂,...,I_yCompletion y data lines are parallel, L positions serial data Capable data output operation, data are transmitted to the information bit register of y L length.

Information bit register group is illustrated in figure 3, the structure of information bit register group is by the shift register of y L length Form, its input mode is the shift register of each L length by an independent data wire I_j, j=1,2 ..., y serial inputs Information data from input buffer；L-th of information bit location of j-th of information bit register has three enabled control signals Input port and a data-signal output port, three enable signals come from circulating register group, because row weight is 3, wherein j=1,2 ..., y, l=0,1,2 ..., L-1.Its operation principle is：When it is 1 to receive enable signal, then by data Output, when the enable signal received is 0, then closing information bit location, not output information.

Although each information bit location has three enabled input signals, but an each code period, in three enable signals An only enable signal is high level " 1 ", and other two is low level " 0 "；Each code period, the shift LD of y L length Each of device, there are three element output signals, therefore, each code period exports 3y data message altogether.

It is illustrated in figure 4 ring shift left register array, the ring shift left that circulating register array is grown by 3 × y L Register is formed, and forms y groups, the ring shift left register array of every group of 3 L length.Data entry mode is S_HMatrix first row In 3 ring shift left registers of the first row data deposit rightmost of three corresponding submatrixs, 3 × y L is grown successively Ring shift left register array stores H respectively_dThe first row of the piecemeal permutation matrix of 3 × y L × L dimensions of matrix, completes coding The initialization of device.Its operation principle is：3 × y ring shift left register receives enable signal E=1 simultaneously, completes ring shift left Operation once；1 element in each ring shift left register exports as enable signal, for controlling corresponding informance position to deposit The output of certain a data of device.Only an element is 1 in each ring shift left register, and remaining element is 0；3 × y Ring shift left register has identical enable signal E=1, and carries out ring shift left simultaneously.

Be illustrated in figure 5 the double summation process units of x, summation process unit by x run parallel include two kinds of additions The computing unit and enable signal E generators of device are formed.Wherein, x double summation process units are by a w_xLong shift register, One bit accumulator and a feedback add device to form certainly.Each double summation process units are received from data wire interleaving network w_xIndividual data are stored in w_xIn long shift register, then w is completed in a bit accumulator_xAdding up for individual data, actually exists Completed in accumulatorRead group total, and by result of calculation make a gift to someone feedback from plus device in preserve, while the parallel fortune of x A capable bit accumulator each sends enable signal E₁,E₂,...,E_x, this x enable signal enter with door, when input signal is complete For 1 when, with door export an E=1 enable signal；Feedback, will from the task of device is added actually in a code period w_xIndividual product termSummed resultIt is added, is completed in (13) formula with the check bit of last timeCalculating.Except the first row, need not to do feedback outer from being subject to, and often obtains a check bit, then general Check bit is stored in feedback certainly plus in device, while exports this check bit into output buffer.

Output state array is illustrated in figure 6, output state array is made up of x × L random storage ram cell, Connection type is to form the long serial shift memories of x L, receives the check bit from x double summation process units respectively and calculates As a result, FIFO, the L check value serial input output states calculated, right shift, Serial output；Each coding Cycle, the output state of x L length each obtain the input of a check bit data.In the output of the long output states of x L End, connection one x+1 enter one go out enter singly go out switch, first will more enter singly go out switch, connect information bit data wire, by K= The information data output of yL length, then in turn switches on the output end of the output state of x L length, is sequentially output M=xL verification Position, this just completes coding work, exports coding codeword c=[d p]=[d₁...d_j...d_yp₁...p_i...p_x]。

In order that technical scheme and implementation steps are more apparent, the reality with reference to instantiation to the present invention The mode of applying is further described.It should be noted that following instance is merely to illustrate the present invention, but it is not used in the limitation present invention.

It is known firstly the need of the t- (v, k, 1) or S (t, k, v) Steiner systems determined in Combination Design.Set in combination In the mathematics handbook of meter and related Research Literature, all known t- (v, k, λ_t), as long as parameter t, k, v and corresponding odd even school The parameter matching of matrix is tested, is used equally for the technology of the present invention to realize.

If t=3, k=4, v=8, λ₃=1 obtains known 3- (8,4,1) Combination Designs or Steiner systems S (3,4,8). Two tuple D=(X, B) are generated with this known Combination Design, it is assumed that the element set table of 3- (8,4,1) Combination Design first It is shown as X={ x₁,x₂,...,x₈}.Calculate basic matrix P line numberAssuming that Grouping set is expressed as B={ B₀,...,B_i,...,B₁₃, wherein t=3 tuples occur one in set B each k=4 tuples It is secondary, i.e. λ₃=1；According to lexicographic order and parameter request, each k=4 members packet in B is arranged, obtains following 14 tuple structures Into 4- tuple-sets：

B₀={ x₁,x₂,x₃,x₄, B₁={ x₅,x₆,x₇,x₈, B₂={ x₁,x₂,x₅,x₆, B₃={ x₃,x₄,x₇,x₈, B₄= {x₁,x₄,x₅,x₈, B₅={ x₂,x₃,x₆,x₇, B₆={ x₁,x₂,x₇,x₈, B₇={ x₃,x₄,x₅,x₆, B₈={ x₁,x₄,x₆, x₇, B₉={ x₂,x₃,x₅,x₈, B₁₀={ x₁,x₃,x₅,x₇, B₁₁={ x₂,x₄,x₆,x₈, B₁₂={ x₁,x₃,x₆,x₈, B₁₃= {x₂,x₄,x₅,x₇}。

Construct the incidence matrix L of S (3,4,8) Steiner systems₂(D)：14 are grouped the row for providing incidence matrix in set B Index, i.e. i=1,2 ..., x, x=b=14.There are 8 elements in set X, its t-1=2 tuples (x_α,x_β) one sharedGive L₂(D) columns.And L can be calculated₂(D) row weight is L₂(D) row weight is w_x=(v-t+1)/(k-t+1)=3.The indexed mode of the row of design 28 below.If α ＜ β, and α, β ∈ [1, 8], it is if several to (x_α,x_β)_jSubscript j represent two tuples sequence number, each t-1=2 tuples (x_α,x_β)_jOnly occur once, there is word Allusion quotation sequence provides the arrangement modes of 28 numbers pair and is：

(x₁,x₂)₀,(x₁,x₃)₁,(x₁,x₄)₂,(x₁,x₅)₃,(x₁,x₆)₄,(x₁,x₇)₅,(x₁,x₈)₆,(x₂,x₃)₇,(x₂, x₄)₈,(x₂,x₅)₉,(x₂,x₆)₁₀,(x₂,x₇)₁₁,(x₂,x₈)₁₂,(x₃,x₄)₁₃,(x₃,x₅)₁₄,(x₃,x₆)₁₅,(x₃,x₇)₁₆,(x₃, x₈)₁₇,(x₄,x₅)₁₈(x₄,x₆)₁₉,(x₄,x₇)₂₀(x₄,x₈)₂₁,(x₅,x₆)₂₂,(x₅,x₇)₂₃,(x₅,x₈)₂₄,(x₆,x₇)₂₅,(x₆, x₈)₂₆,(x₇,x₈)₂₇。

As j-th of two tuple (x_α,x_β)_jI-th 4- tuple of two elements in set B when occurring, in L₂(D) square I-th row jth of battle array lists existing 1 element, as (x_α,x_β)_jElement and B_iElement when not occuring simultaneously, L₂(D) it is right in matrix It is 0 element to answer position, thus constructs L₂(D) incidence matrix (14) the, if x × y=14 thus constructed × 28L₂(D) matrix fills Work as H_dThe basic matrix P of matrix.

If q=29, it is greater than L₂(D) incidence matrix columns y=28 least prime, with the addition on sub-prime domain GF (29) Computing constructs the positive integer matrix V of q × q=29 × 29, such as (15) formula.The square of x × y=14 × 28 is intercepted from positive integer matrix V Battle array serves as H_dFull first shift matrix S of matrix_F, interception way is that 14 rows 28 in the upper left corner arrange, resulting S_FMatrix is shown in (16) Formula.

Full first shift matrix S that the basic matrix P that (14) formula x × y=14 × 28 are tieed up is tieed up with (16) formula x × y=14 × 28_F Generalized Hadamard product is done, obtains sparse shift matrix S_H, see (17) formula.To S_HMatrix is extended, by positive integer value therein Filled with the permutation matrix of corresponding L × L dimensions, therein -1 is filled with the full null matrix of L × L dimensions, then obtains required H_d Matrix, and form H=[H_d H_p] matrix, it is that a code length is N=K+M=28L to have IRQ-QC-LDPC codes defined in the matrix + 14L=42L, code check R=28L/42L=2/3, maximum column weight are 3, and row weight is 8, and the weight of the first row is 7, is not had The irregular IRA-QC-LDPC codes of four sides cycles.

Above-mentioned IRA-QC-LDPC codes may be constructed the serial encoder of 14 parallel L bit lines, the input-buffer grown by L Device array is to L long message bit register serial input datas, 28 data wire I₁,I₂,...,I₂₈Parallel transmission.In a coding In cycle, 3 × y=3 × 28 L long circulatings move to left register, there is provided 3 × 28 enable signals, post the information bit of 28 L length Storage exports 3 × 28 data has 3 unit output datas to data wire interleaving network, the information bit register of each L length.Number It is made up of according to line interleaving network 28 × L data lines, in a code period, there is 3 × 28=w_x× x=6 × 14 data exist Transmitted on data wire interleaving network.One shares 14 double summation process units performs parallel, in a code period, Mei Geshuan Summation process unit receives and comes from data wire interleaving network w_x=6 data, it is stored in w_xIn the shift register of position, then by one Bit accumulator is summed, and is completedCalculate, by result of calculation deposit feedback from adding in device, be simultaneously emitted by enable signal E₁, E₂,...,E₁₄, work as E₁,E₂,...,E₁₄When being 1, enable signal generator sends enable signal E=1 with door.The enabled letter Number 3 × y=3 × 28=84 L long circulating is moved to left register ring shift left once, start next code period, weight Multiple said process, is obtained nextIt is sent into feedback and adds device certainly, with previous storage result feedback from adding, obtains down The result of calculation of one check bit.

Above content as it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, It is not intended to limit the invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc., It should be included in the scope of the protection.

Claims (9)

1. a kind of Algebraic Structure acquisition methods of IRA-QC-LDPC codes, it is characterised in that methods described includes：

The Sparse Parity-check Matrix of M × N-dimensional is designed to system architecture H=[H_d H_p], M × K=xL corresponding to information bit × The H of yL dimensions_dThe piecemeal submatrix structure that matrix design is tieed up into x × y L × L, each piecemeal submatrix are permutation matrix or complete zero Matrix, the dual diagonal matrix H of M × M=xL corresponding to check bit × xL dimensions_pIt is broken down into the sub- square of piecemeal of x × x L × L dimension Battle array, x piecemeal submatrix on the diagonal is double diagonal line structure；The H_dTwo smaller compact matrix of matrix The basic matrix P and sparse shift matrix S of x × y dimensions_HRepresent；

T- (v, k, λ in the basic matrix P Combinational Mathematics_t) design incidence matrix construction；The line number of the incidence matrix is by v The quantity index of k- tuples in individual element determines that columns is indexed by the quantity of the t-1 tuples in v element and determined, specific meter It is：Line numberColumnsRow weightWith row weight w_y=(v-t+1)/(k-t+1), wherein t、v、k、λ_tIt is positive integer, and meets v ＞ k ＞ λ_t, λ_t=1；

The sparse shift matrix S_HBy basic matrix P and full first shift matrix S_FIt is determined that the addition fortune introduced on sub-prime domain GF (q) α × β (mod q) is calculated to construct the positive integer matrix of q × q dimensions, the full member of arbitrarily interception x × y dimensions is moved from the positive integer matrix Bit matrix forms S_F, q is greater than y least prime, α, β=0,1,2 ..., q-1；

Full first shift matrix S of basic matrix P and the x × y dimension of x × y dimensions_HGeneralized Hadamard product is carried out, described in generation The sparse shift matrix S of x × y dimensions_H, S_HElement on GF (q) ∪ { -1 } value；

The sparse shift matrix S_HIn positive integer extended with L × L permutation matrix, -1 is extended with L × L full null matrix, is formed H_dMatrix.

2. the Algebraic Structure acquisition methods of a kind of IRA-QC-LDPC codes according to claim 1, it is characterised in that described T- (v, k, λ in basic matrix P Combinational Mathematics_t) design incidence matrix construction, parameter meets v=3k-2t+2 and λ_tWhen=1, production Raw row weight is 3 P matrixes；During parameter t=3, then the line number of the basic matrix PColumnsRow weightRow weight w_y=(v-t+1)/(k-t+1)=3.

3. a kind of part parallel coding method of IRA-QC-LDPC codes, it is characterised in that methods described is specially：Sparse parity Check matrix H=[H_d H_p] blocking characteristic specifically, the information sequence of K to be encoded length is divided into y sections, be expressed as d= [d₁...d_j...d_y], wherein d_j=[d_j,1,d_j,2,...,d_j,L] it is the binary message vector that length is L；M length to be solved Verification sequence be divided into x sections, be expressed as p=[p₁...p_i...p_x], wherein p_i=[p_i,1,p_i,2,...,p_i,L] it is that length is L Binary system check vector；Codeword sequence after coding is c=[d p]=[d₁...d_j...d_yp₁...p_i...p_x]；The H_d And H_pBlocking characteristic and code definition expression formula Hc^T=0, release x independent matrix equations：

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Wherein,Represent H_dPartitioning of matrix submatrix；Q_iRepresent H_pPiecemeal submatrix on diagonal；T representing matrixs or arrow The transposition of amount；Each matrix equation forms independent linear serial code algorithm；

Work as H_dMatrix column weight w_y=3, thenIt is simplified shown asSymbol i Represent the index of x matrix equation, i=1,2 ..., x；Symbol j represents y piecemeal submatrix index in i-th of matrix equation, J=1,2 ..., y；Symbol m and l represent it in submatrix respectivelyIn line index and column index, m, l=1,2 ..., L；g =1,2 .., w_y=1,2,3 be H_dThe index of rectangular array weight 3；In i-th of linear equation of the x independent matrix equations, Check vector p_i=[p_i,1,p_i,2,...,p_i,L] calculation expression beThe check bit of the first row is asked by recurrence And expression formulaCalculate, by the follow-up L-1 check bit of recurrence read group total, each check bit only needs Complete row weight w_xThe addition of individual data and a recurrence superposition, wherein m=2,3 ..., L represent each independent matrix side Journey has L check bit p_m,iSerial computing, i=1 are wanted, 2 ..., x indicates that x independent equation concurrently completes L serial verifications Position p_m,iCalculating.

4. a kind of encoder of IRA-QC-LDPC codes, it is characterised in that the encoder includes：

The input buffer array of y L length, for the caching of K=yL positions information data sequence, and start encoder operation, work as K When=Ly information data is filled with y × L input buffer arrays, then the information bit grown y L long messages data transfer to y L Register, while serial transfer is to output end；

The information bit register of y L length, when it is " 1 " that information bit register, which receives enable signal, then by data output to data Line interleaving network, when the enable signal received is 0, then not output information；

3 × y L long circulating moves to left register array, for receiving H_dThe of the permutation matrix for 3 × y L × L that matrix is included A line, complete the initialization of encoder；The ring shift left register array is parallel to complete under enable signal E=1 control The operation of ring shift left once, " 1 " element each moved to left in register are exported to the information bit of y L length as enable signal Register；

X double summation process units, for receiving the information data from data wire interleaving network, a bit accumulator therein is first First to w_xIndividual data carry out cumulative summation, and summed result is delivered into a feedback adds device certainly, while generates enable signal E, then Add device to carry out the cumulative of itself certainly by a feedback, and preserve the result of calculation of check bit, at the same check bit result of calculation is defeated Go out to the output state array of x L length；

The output state array of x L length, the check bit from x double summation process units is received respectively, by entering singly to go out more Switch, information data sequence and the verification of data sequences are sequentially output, and form encoded output sequence.

5. the encoder of a kind of IRA-QC-LDPC codes according to claim 4, it is characterised in that y in the encoder The input buffer array of L length is specifically made up of the random memory unit of y L length, for caching the pending Information Number of input According to serial input data sequence, 8, the parallel input data sequences of 16 or 32 bit bytes are converted into section length L and code Word length K=Ly data sequence storage, after the input buffer that first segmentation L grows is filled with, it is automatically credited second segmentation Input buffer, until a long K=Ly of code word information data is filled with y × L cache arrays；The input-buffer of the L length Device can arbitrarily be blocked to 8,16 or 32 bit bytes, and the input buffer of L length is full of by moving to right；Y L length input is slow Storage is each sequentially completed the output of y input buffer L positions serial mode by a data lines respectively, passes data to Output end of the information bit register and Serial output that y L grows to encoder.

A kind of 6. encoder of IRA-QC-LDPC codes according to claim 4, it is characterised in that 3 in the encoder × Y L long circulating moves to left the ROM that register array removes by the 3 × y L writable and eresables grown or flash memory cell array is formed, and is arranged in Y groups, the ring shift left register of every group of 3 L length, it is respectively used to store H_dThe piecemeal permutation matrix of 3 × y L × L dimensions of matrix The first row, set initial value for encoder；Receive enable signal E, the equal ring shift left one of ring shift left register of 3 × y L length It is secondary, there was only 1 element in each register, remaining element is all 0, the information bit that 1 element of output is grown as the y L The enabled control signal of register；The ring shift left register operation of the 3 × y L length, each code period are sent 3 × y enabled control signals.

7. the encoder of a kind of IRA-QC-LDPC codes according to claim 4, it is characterised in that y in the encoder The information bit register of L length is made up of the y L random memory units grown, and the information bit register of y L length is by y data lines L Input information data to Bits Serial；Each data storage cell of the information bit register of each L length has 3 enable signal controls End and a single data output line；Information bit register is used for and H_dA line of piecemeal permutation matrix in matrix does multiplying, Each code period, it is 1 that 3 enable signals of each unit, which only have one,；In a code period, y information bit deposit Device concurrent working, each information bit register export 3 data-signals to data wire interleaving network simultaneously, altogether parallel output 3y data-signal.

8. the encoder of a kind of IRA-QC-LDPC codes according to claim 4, it is characterised in that x in the encoder Double summation process units are made up of x double summers and an enable signal E generator；Double summers include w_xLong shift Register, a bit accumulator and a feedback add device certainly；The w_xLong shift register receives the w from data wire interleaving network_x Individual data, and be sent into a bit accumulator and carry out cumulative read group total, result of calculation deposit feedback is sent out simultaneously from adding in device Go out enable signal E₁,E₂,...,E_x, feed back certainly plus device carry out one cycle feedback to the data being newly stored in and added certainly, and preserve verification The result of calculation of position, the currency preserved is delivered in output state；The enable signal E generators, by one with Door is formed, as x enable signal E₁,E₂,...,E_xWhen being 1, the output of enable signal generator E=1, wherein w_xRepresent row weight Amount.

9. the encoder of a kind of IRA-QC-LDPC codes according to claim 4, it is characterised in that x in the encoder The output state array of L length is made up of x × L random storage ram cell；Connection type is to form the long serial shifts of x L to deposit Reservoir, FIFO；The output end of the output state array singly goes out switch more by entering, by information data sequence and verification Data sequence is sequentially output, and forms encoded output sequence.