KR101216075B1 - Apparatus and method for decoding using channel code - Google Patents

Abstract

The present invention relates to an encoding and decoding method. More specifically, the present invention relates to an encoding and decoding method and apparatus for improving performance without occupying a large amount of memory, and for reducing hardware complexity in implementation and improving performance of encoding and decoding.

An encoding method according to an embodiment of the present invention includes: receiving an encoded signal from a transmitting side; And decoding the received signal using a parity check matrix, wherein the non-zero components of each layer do not overlap each other in a column direction between a specific number of layers ( It is characterized by consisting of a non-overlapped layer.

Encoding, Decoding, Parallel Processing, Parity Check Matrix

Description

Apparatus and method for decoding using channel code}

1 is a diagram showing a parity check matrix H through a bipartite graph.

2A is an example in which the technical features of the present invention are applied to a wireless communication system.

2B is an example in which the technical features of the present invention are applied to an encoding apparatus.

FIG. 3 is a diagram illustrating that a base matrix is formed by a plurality of permutation matrices or zero matrices of z × z dimension.

4 is a diagram illustrating a method of shifting all rows (or columns) of a basic permutation matrix by a predetermined interval according to the present invention.

5A through 5F are diagrams showing basic matrices according to an embodiment of the present invention.

6 is a diagram illustrating a basic matrix when the code rate 1/2 is formed by shortening the size of the basic matrix when the code rate is 3/4.

7 is a diagram illustrating another basic matrix according to an embodiment of the present invention.

8 is another embodiment of the base matrix when the code rate is 3/4.

FIG. 9 is a diagram illustrating an example of a parity check matrix divided in units of layers.

10A is a diagram illustrating the concept of parallel processing.

10B is a diagram illustrating the concept of memory access collision according to parallel processing.

11 is another embodiment of a base matrix when the code rate is 1/2.

12 is another embodiment of the base matrix when the code rate is 1/2.

13A to 13D are diagrams showing an example of a parity check matrix capable of parallel processing according to the present invention.

FIG. 14 illustrates another embodiment of the base matrix when the code rate is 2/3. FIG.

15 is a diagram illustrating a base matrix obtained by exchanging rows of the base matrix proposed in the present invention.

16 is a block diagram illustrating an embodiment of an LDPC decoder according to an embodiment of the present invention.

17 is a diagram illustrating a memory structure of an LDPC decoder according to an embodiment of the present invention.

18 is a diagram illustrating a connection form between hardware of an LDPC decoder according to an embodiment of the present invention.

19A to 19H illustrate a process of performing one iteration during an initialization process when performing LDPC decoding.

20A to 20H illustrate a process of performing one iteration during an initialization process when performing LDPC decoding with parallel processing.

The present invention relates to an encoding and decoding method. More specifically, low density parity check (LDPC) code can be used to improve performance without taking up a large amount of memory, and to reduce hardware complexity in implementation and improve the performance of encoding and decoding. The present invention relates to an encoding and decoding method and an apparatus thereof.

Recently, a coding method using an LDPC code has emerged. The LDPC code was proposed by Gallager in 1962 as a linear block code with a low density, with most of the elements of the parity check matrix H being zero. Since the LDPC code is very complex, it has been forgotten because it was impossible to implement with the technology at the time of the suggestion, and since the LDPC code has been rediscovered in 1995 and proved to be very excellent in performance, studies on the LDPC code have been actively conducted recently. (Reference: [1] Robert G. Gallager, "Low-Density Parity-Check Codes", The MIT Press, September 15, 1963. [2] DJC Mackay, Good error-correcting codes based on very sparse matrices, IEEE Trans Inform.Theory, IT-45, pp. 399-431 (1999)).

Since the parity check matrix of the LDPC code is very small, it can be decoded through iterative decoding even in a very large block size. When the block size becomes very large, the performance is close to Shannon's channel capacity limit like a turbo code. The number of 1's included in a row or a column in the parity check matrix is referred to as a weight.

The LDPC code can be described by the (n-k) × n parity check matrix Η. The generator matrix 하는 corresponding to the parity check matrix ƒ can be obtained from Equation 1 below.

[Equation 1]

Η · Ｇ = 0

In the encoding and decoding method using the LDPC code, the transmitting side can encode the input data according to Equation (2) using the parity check matrix H and the generating matrix G in the relation of Equation (1).

&Quot; (2) "

c = G x (where c is a codeword and x is an information bit)

Hereinafter, a decoding method using the H matrix according to the related art will be described.

The decoder of the receiving end finds the information bit (x) in the codeword (c), which is the encoding result of the transmitting end, using the property that Hc = 0. That is, when the received codeword is c ', the value of Hc' is calculated, and if the result is 0, the previous k bits of c 'are determined as decoded information bits. If the value of Hc 'is not 0, we find c' whose value of Hc 'is 0, using a sum-product algorithm, a belief propagation algorithm, etc. Restore x. The check equation Hc '= 0 may be changed to c'H ^T = 0 according to the relation between the information bit and the G matrix, and the check equation may be changed according to the relation between the information bit and the G matrix .)

1 is a diagram showing a parity check matrix H through a bipartite graph. 1, the CNU represents a check node unit, and the VNU represents a variable node unit. The process of applying an algorithm on a dichotomous graph to decode can be roughly described in three steps.

1. Updating a probability value from a check node to a variable node

2. Updating probability value from bit node to check node

3. Determination of decoding value through bit node probability

First, in order to perform the first process, a first process of performing an update of the check node is performed through an initialization step in which a probability value received from a channel is input. After the first process is performed, if the probability value from the variable node to the check node is updated, the second process is performed. After performing the first and second processes, a decoding value is determined using a probability value received from the channel and a probability value updated through the first and second processes.

When the decoding value c 'determined in the third step satisfies the check expression Hc' = 0 in the third step after the first and second processes, the decoding process determines the value c 'as the correctly received decoding value. Otherwise, the first and second processes are repeated until the inspection equation is satisfied a predetermined number of times. The updating process of the probability values in the first and second processes repeats the updating process for each number of nonzero components, i.e., 1, belonging to each row or column of the parity check matrix. That is, a check to variable update of the first process and a variable to check update of the second process are performed at a position corresponding to the weight of the parity check matrix H. As the first and second processes are repeated, the reliability of the probability value between the check node and the bit node increases, resulting in a close proximity to the true value of the codeword to be obtained.

Recently, in LDPC coding, a method of encoding input data using the parity check matrix H instead of the generation matrix G is generally used. Therefore, as described above, the parity check matrix H is the most important factor in the encoding method using the LDPC code. Since the parity check matrix H has a size of about 1000 x 2000 or more, many operations are required in the encoding and decoding processes, and the implementation is complicated and requires a large storage space.

The present invention has been proposed to improve the prior art as described above, and an object of the present invention is to provide an LDPC encoding and decoding method and apparatus for performing LDPC encoding and decoding using a parity check matrix that can be easily processed in parallel. To provide.

Summary of the Invention

A decoding method according to an embodiment of the present invention includes: receiving a signal encoded using a parity check matrix from a transmitting side; And decoding the received signal by using the parity check matrix, wherein the parity check matrix is composed of a plurality of layers and nonzero in the direction of a column between the layers. The elements are characterized in that they are non-overlapped, and one layer is characterized by including at least one row.

Another example of a decoding method according to an embodiment of the present invention includes: receiving a signal encoded using a parity check matrix; And a parity check matrix including a plurality of layers, the non-overlapped non-overlapped elements in the direction of a column between the layers. And decoding the received signal in units of a specific number of layers not included, wherein one layer includes at least one row.

A decoding apparatus according to an embodiment of the present invention includes a receiving module for receiving a signal encoded using a parity check matrix; A memory for storing information of a parity check matrix including a plurality of layers, the non-overlapped non-overlapped elements in the direction of a column between the layers; And a decoding module configured to decode a received signal in units of a specific number of layers that do not overlap each other by using information of the parity check matrix obtained from the memory, wherein one layer includes at least one row. Characterized in that.

Preferred of the present invention Example

Hereinafter, preferred embodiments of a coding method using a Low Density Parity Check (LDPC) code according to the present invention will be described with reference to the accompanying drawings. 2A is a view for explaining a preferred embodiment of the present invention, which is an example in which the technical features of the present invention are applied to a wireless communication system. Embodiments described below are merely examples for explaining the features of the present invention, and it is apparent to those skilled in the art that the technical features of the present invention may be applied to all fields requiring encoding.

In FIG. 2A, the transmitter 10 and the receiver 30 perform communication via the radio channel 20. In the transmitter 10, the k-bit source data u output from the data source 11 becomes an n-bit codeword c by LDPC encoding in the LDPC encoding module 13. The codeword c is wirelessly modulated by the modulation module 15 and transmitted through the antenna 17 and received by the antenna 31 of the receiver 30 through the radio channel 20. The receiver 30 undergoes the reverse of the process that occurred at the transmitter 10. That is, the received data can be demodulated by the demodulation module 33 and decoded by the LDPC decoding module 35 to finally obtain the source data u. It is apparent to those skilled in the art that the data transmission and reception process as described above has been described within the minimum range necessary to explain the features of the present invention, and there are many other processes necessary for data transmission.

The parity check matrix ƒ used to encode input source data in the LDPC encoding module has a dimension of (nk) × n. K denotes the length (bit unit) of the source data input to the LDPC encoding module 13, and n denotes the length (bit unit) of the coded codeword c. The parity check matrix ƒ is composed of a number of permutation matrices or zero matrices in the z × z dimension, as shown in FIG. 3. That is, in FIG. 3, P _{i, j} means a permutation matrix or a zero matrix of z × z dimension.

The plurality of permutation matrices are formed by modifying a predetermined rule from at least one base permutation matrix. Advantageously, said basic permutation matrix is an identity matrix. In addition, the plurality of permutation matrices including the one or more basic permutation matrices preferably have a weight of one row and one column. That is, it is preferable that only one element is 1 and the remaining elements are 0 among all elements of all rows and columns of the plurality of permutation matrices.

As a constant rule for modifying the at least one basic permutation matrix to form the plurality of permutation matrices, the present invention considers a method of shifting all rows (or columns) of the basic permutation matrix by a predetermined interval. do. 4 is a diagram for explaining an example thereof. That is, in FIG. 4, all rows of the basic permutation matrix of FIG. 4 (a) are shifted downward by 5 rows (n _s = 5) (or all columns by 3 columns to the right) to FIG. 4 (b). To form the permutation matrix of. According to this method, it is possible to form (z-1) permutation matrices according to the interval of rows (or columns) shifted with respect to the basic permutation matrix in the z × z dimension (hence, the basic permutation matrix is included. Z permutation matrices are formed). Given the basic permutation matrix, each of the z permutation matrices including the basic permutation matrix may be represented by one integer. For example, the basic permutation matrix is represented by 0, the permutation matrix is shifted by one row to all rows of the basic permutation matrix by 1, and all the rows of the basic permutation matrix are shifted by 2 rows. All permutation matrices are expressed as a single integer, for example, by expressing the permutation matrices as 2.

As described above, the type of a plurality of permutation matrices formed from the basic permutation matrix can be simply expressed by one integer according to the number of rows (or columns) shifted. It is obvious that the types of the plurality of permutation matrices are represented by one integer and can be represented by other methods.

According to the present invention, in the encoding or decoding using the parity check matrix Η, a plurality formed by shifting each row (or column) of the at least one basic permutation matrix and the at least one basic permutation matrix by a predetermined interval. The at least one base permutation matrix and the base matrix Η every time encoding or decoding is required at the transmitting side or the receiving side with the type of the permutation matrices of is stored in a base matrix Η _b . _A parity check matrix ƒ is generated using _b , and encoding or decoding is performed using the generated parity check matrix. In FIG. 2B, a preferred embodiment of an encoding apparatus using an LDPC code according to the present invention includes a memory module 131, a parity check matrix generation module 132, and an encoding module 134. The memory module 131 stores the basic permutation matrix and the basic matrix. The base matrix generation module 132 generates the parity check matrix by using the base permutation matrix and the base matrix stored in the memory module 131. The encoding module 134 encodes input source data using the parity check matrix generated by the parity check matrix generation module 132. It will be apparent to those skilled in the art that the parity check matrix generation module 132 and the encoding module 134 may be implemented by software or hardware according to each function.

When the basic matrix Η _b is divided into two parts Η _d and Η _p having the structure of [H _d ｜ H _p ], the Η _p part generally uses a block dual diagonal matrix. It is preferred, but not limited to. The block double diagonal matrix means that the main diagonal and the diagonal immediately below or above the main diagonal are both unitary matrices and the rest are all zero matrices. When the Η _p portion is a block double diagonal matrix, a column having a column weight of 1 is generated in the Η _p portion. In order to avoid this, it is preferable to replace one or two zero matrices with a unit matrix.

The H _d portion of the base matrix Η _b is composed of a combination of a plurality of permutation matrices and a zero matrix formed by shifting each row of the base permutation matrix and the base permutation matrix by a predetermined interval. When combining the three types of matrices to form the basic matrix _f , it is preferable to consider the following matters in terms of encoding or decoding performance.

First, the difference between the number of any two types of the plurality of permutation matrices with respect to the entire base matrix ν _b should be less than or equal to a predetermined first threshold value. That is, it is preferable that the number of each permutation matrix is the same or similar to the entire base matrix ƒ _b . The smaller the first threshold value is, the more preferable but a range of 3 to 7 may be acceptable.

Secondly, it is desirable to minimize or minimize 4-cycles or 6-cycles in the parity check matrix ƒ. In particular, the parity check matrix preferably does not have four cycles. In addition, the parity check matrix ƒ preferably has a six-cycle less than or equal to the second predetermined threshold value C _max . 4-cycle means a case where any two rows of the parity check matrix ƒ have 1 at two points at the same time. The six-cycle means a case where all two combinable rows selected from any three rows of the parity check matrix ƒ have 1 at the same point.

Third, the column weight and / or row weight should be regular with respect to the entire parity check matrix ƒ. By using a unit matrix of z × z as the basic permutation matrix, column weights and / or row weights may be regular for the parity check matrix ƒ.

Fourth, the base matrix ν _b should be constructed by combining the three kinds of matrices so as to have good encoding or decoding performance for all code rates and all codeword sizes. Recently, since a variable code rate and codeword size are applied in a mobile communication system, a plurality of permutes formed by shifting the basic matrix Η _b by each interval of the basic permutation matrix and each row of the basic permutation matrix are formed by a predetermined interval. When constructed by a combination of a presentation matrix and a zero matrix, it must be optimized to have good performance for all code rates and all codeword sizes.

5a to 5f show preferred embodiments of the base matrix ƒ _b with the characteristics as described above. 5A to 5F are basic matrices when the code rate is 3/4, where '0' is a unit matrix of z × z dimension and '-1' is a z × z dimension An integer of 1 or more means a permutation matrix formed by shifting each row of the unit matrix of the z × z dimension by the integer.

As shown in FIG. 6, the base matrix Η _b when the code rate is 1/2 may be formed by shortening the size of the base matrix when the code rate is 3/4.

Fig. 7 shows another example of the basic matrix Η _b having the characteristics as described above. The example shown in FIG. 7 is a basic matrix when the code rate is 2/3, and the meanings of '0', '-1' and other one or more integers are the same as in the example of FIGS. 5A to 5F.

The basic permutation matrix has to change its dimension (ie, z value) as the codeword length changes. It is memory-saving to make the basic matrix for the basic permutation matrix of all dimensions and store them all for encoding. There is an undesirable aspect in terms of storing only the first base matrix for the first base permutation matrix with the largest dimension (z _max ) and the base matrix for the second base permutation matrix with another dimension (z). Is generated using the first basic matrix whenever necessary for encoding or decoding.

In this case, the first basic matrix may have two or more types of permutation matrix as its elements. That is, the type of permutation matrix optimized for each range is set by dividing the entire range of the dimension z of the basic permutation matrix, which is varied, into two or more ranges. For example, when the total range of z to be varied is 10 to 96, the entire range is divided into 10 to 53 and 54 to 96 to form a first basic matrix optimized for each range. In this case, two first basic matrices are provided, and two values are stored as each element of one first basic matrix instead of each other, thereby improving encoding or decoding performance and saving memory.

8 is another embodiment of the base matrix when the code rate is 3/4. The characteristic of the base matrix shown in FIG. 8 is to minimize the number of 4 cycles and 6 cycles, to make the column weight regular, and that each element of the base matrix has all the code rates and The basic permutation matrix is shifted to have a good performance with respect to codeword size. In the example of FIG. 8, compared with the example of FIGS. 5A to 5F, the simulation resulted in almost the same performance even though the size was reduced to 1/4.

Hereinafter, a method of decoding an LDPC code using the basic matrix ƒ _b as described above will be described. The decoding of a conventional LDPC code is mainly performed by repeating a process of increasing reliability by updating probability values between check nodes and bit nodes on a dichotomous graph, which is another representation of a parity check matrix. In the decoding method using a dichotomy graph, which is another representation of the parity check matrix, the codeword is determined based on the updated probability value. Therefore, the process of updating the probability value that determines the codeword is a performance of the decoder. Will have a direct impact on

The reliability update process can be roughly divided into a process of updating the probability value from the check node to the bit node and a process of updating the probability value to the check node in the bit node. In the case of updating the probability value from the check node to the bit node or updating the probability value from the bit node to the check node, a probability value placed in the same column excluding the value of the own node to which the probability value is updated , And updates its probability value using a probability value placed in the same row. At this time, depending on how much the probability value used is updated, a more reliable result, that is, a more positive effect, is applied to the decoder.

Hereinafter, an LDPC decoding method that has a more positive effect on the decoding method will be described. According to an embodiment of the present invention, when the LDPC-coded received signal is decoded using the parity check matrix, a method of decoding the received signal in units of layers, which is a bundle of rows of the parity check matrix. (Hereinafter referred to as 'Layered decoding'). The layered decoding is characterized in that, when updating a probability value from a bit node to a check node, when there is a value updated in the same column of the parity check matrix, the probability value is updated using the updated value.

The layered decoding is a method of repeatedly decoding a row of a parity check matrix used for encoding and decoding an LDPC code, by dividing the layer by layer. The layer represents a group of each row when grouping and dividing rows of the parity check matrix. That is, when grouping the rows of the parity check matrix into several groups, one group may be referred to as a layer. The layer may be one row.

9 is a diagram illustrating basic matrices divided in units of layers. The illustrated basic matrix is an example for explaining the layered decoding method, and the illustrated number represents a type of a plurality of permutation matrices formed from the basic permutation matrix as a shift number.

The layered decoding updates reliability by using probability values that have all been updated in the same row in reliability update of the parity check matrix H in the same row. That is, the probability value update between the check node and the bit node is performed on the dichotomous graph as in the conventional LDPC decoding method. However, in the process of updating the probability value from the bit node to the check node (that is, the process of updating the probability value of the column of the parity check matrix H), the probability value is updated in units of layers and included in a specific layer. When updating a probability value, there is a feature of using a probability value included in a layer that has already been updated. The layered decoding performs decoding on a layer basis. When the probability value is updated for all layers included in the parity check matrix, one iteration for LDPC decoding is performed. The layered decoding is a result calculated in one layer, that is, reliability when an operation for updating a probability value is already performed for one layer and an operation for updating a probability value for a next layer. By using the updated message result in the calculation of the next layer, a more reliable message is used in the decoding process, that is, the probability value update process. As a result, when such probability value update is repeated, a more reliable message is used to update the probability value, thereby increasing the reliability of the probability value between the check node and the bit node, thereby improving the performance of the decoder. 9 is a general basic matrix. The matrix of FIG. 9 can sequentially decode each layer by a layered decoding method, for example, Layer 1-> Layer 2-> Layer 3-> Layer 4-> Layer 5-> Layer 6 Decoding can be performed in the order of-> Layer 7-> Layer 8.

Hereinafter, the basic concept of parallel processing used in the present invention and the prerequisites for performing layered decoding in a parallel processing method will be described.

10A is a diagram schematically illustrating the concept of parallel processing. Parallel processing means that a plurality of arithmetic units divide and process a task that one arithmetic unit processes in performing one arithmetic operation. As a result of the parallel processing, there is a positive effect that the time required to perform one operation decreases in proportion to the number of operation blocks used in the parallel processing. However, when parallel processing is performed, a dependency problem between a memory conflict and data to be processed in parallel occurs, and the above problems must be solved in order to parallel process layered decoding according to the present invention.

Hereinafter, a problem according to the parallel processing of the above-described layered decoding and a solution according to the present invention will be described.

10B is a diagram illustrating the concept of memory conflict according to parallel processing. In the case of the serial processing method, since a single operation unit uses a block of memory, there is no problem in reading a value to be calculated or storing a result of the calculation. However, in a parallel processing method in which a plurality of operation units are simultaneously operated, a memory collision may occur when two or more operation units simultaneously access a memory block in the same position. If the probability value updating units for LDPC decoding simultaneously access a memory at the same location, the memory collision may occur.

In order to apply the parallel processing method to the LDPC decoding, there must be not only a problem of simultaneous access to the memory block, but also a dependency between data to be processed simultaneously. That is, if the output value of any one of the plurality of operation blocks must be the input value of the other operation block at the same time, the operation value must be sequentially calculated according to the dependency thereof, not at the same time.

In one embodiment of the LDPC decoding method according to the present invention, the parity check matrix is divided into layer units and each layer is sequentially processed in a specific order, For example, the specific layer is decoded in a parallel processing manner by solving the above-described problem between memory conflict and data to be processed in parallel. An embodiment of the present invention provides a parity check matrix that does not have overlapping portions between specific layers in order to perform data processing in a parallel processing manner with respect to the specific layers. In the parity check matrix according to an embodiment of the present invention, non-zero elements of a specific layer of the parity check matrix are present at different positions in the column direction. That is, for a particular layer, positions where the weight of the parity check matrix exists are different in the column direction.

As described above, in the decoding of a general LDPC code, the probability value is updated in all rows of the H matrix, and then the probability value is updated for each and every column. On the other hand, the layered decoding updates the probability value in a pre-divided group unit (i.e., in a layer unit) when updating the probability value of each row. In such a decoding method, when updating the probability values corresponding to the second and subsequent groups, the decoding performance is improved by using a probability value that is more reliable and has already been updated in the previous group. Although there is such an advantage in the layered decoding, if the conventional parity check matrix is divided into specific layer units and data is processed in a parallel processing manner with respect to the specific layer, parallelization of the specific layer is performed. In order to avoid the above-described problem of memory conflict and the problem of dependency between parallel processing data, only one layer needs to be processed at the same time, so a delay occurs in decoding. However, as proposed in this embodiment, if the parity check matrix is designed such that the positions of the weights of columns do not overlap between specific layers, parallel processing for multiple layers is performed simultaneously. can do.

Hereinafter, a method of processing layered decoding in parallel using a parity check matrix that does not overlap with respect to a specific layer will be described.

11 is another embodiment of the base matrix when the code rate is 1/2. The embodiment groups the rows of the parity check matrix generated by the base matrix of FIG. 11 into one layer according to the size of the base permutation matrix for the base matrix. That is, the above embodiment is an example in which the layer of the parity check matrix generated by using the basic matrix of FIG. 11 and the basic permutation includes as many rows as the number of rows of the basic permutation matrix. . As a result, the number of rows included in one layer in FIG. 11 is equal to the number of rows in the basic permutation matrix according to the basic matrix of FIG. 11. The basic matrix of FIG. 11 is proposed for effective parallel processing. In layered decoding, a row order of the base matrix of FIG. 11 is determined as (1 → 7 → 2 → 8 → 3 → 9 → 4 → 10 → 5 → 11 → 6 → 12). In this case, the 'non-zero' elements do not overlap in any column direction with respect to any two rows of the base matrix (eg, the first row and the seventh row). . In the basic matrix, components having shift numbers greater than or equal to zero for any two rows (eg, the first row and the seventh row) do not overlap in the column direction. For example, it can be seen that the eighth row does not overlap each other with components having a shift number greater than or equal to zero in any column direction when compared to the second row or the third row. In addition, referring to the parity check matrix generated by the base matrix of FIG. 11, one row of the base matrix represents one layer of the generated parity check matrix. Between each layer of the matrix, the position where the weight exists does not overlap in the column direction.

12 is another embodiment of the base matrix when the code rate is 1/2. The basic matrix of FIG. 12 is proposed for more effective parallel processing. The base matrix of FIG. 12 includes two pairs of rows (1, 7), (2, 8), (3, 9), (4, 10), (5, 11), and (6). , 12) are designed so that components with shift numbers greater than or equal to zero do not overlap in any column direction. According to the embodiments of FIGS. 11 and 12, an efficient parallel processing may be performed in an implementation process for layered decoding.

Hereinafter, according to another embodiment of the present invention, the order of the layers of the base matrix having no overlapping portion for a specific layer is adjusted, and the parity check matrix generated by the adjusted base matrix is adjusted. A method of parallel processing of layered decoding will be described.

13A illustrates an embodiment of a base matrix for layered decoding according to an embodiment of the present invention. In the basic matrix, '-1' represents a zero matrix and '#' represents an arbitrary permutation matrix formed by shifting the basic permutation matrix in a row or column direction by any integer of 0 or more. 13 groups the rows of the parity check matrix generated by the base matrix of FIG. 13 into one layer according to the size of the base permutation matrix for the base matrix. That is, the number of rows included in each layer is equal to the number of rows of the basic permutation matrix according to the basic matrix of FIG. 13. Thus, one layer of the parity check matrix generated by the base matrix corresponds to one row of the base matrix. Hereinafter, a method of designing a new parity check matrix by adjusting the order of the rows of the base matrix so that positions at which weights exist between adjacent layers of the parity check matrix do not overlap. Since a dual diagonal portion exists in the base matrix, a parity check matrix according to an embodiment of the present invention can be designed by changing the order of rows that do not affect the LDPC decoding performance. FIG. 13B is an example of a basic matrix in which the order of the rows is adjusted so that components having zero or more shift numbers do not overlap each other among the specific rows of FIG. 13A, that is, the weight of a column becomes 1 or less for a specific row. In the case of FIG. 13B, the positions where the weights of the columns exist for Layer 0 and Layer 3 do not overlap. FIG. 13C is a diagram illustrating the basic matrix illustrated in FIG. 13B in units of layers capable of parallel processing. When LDPC decoding is performed using the parity check matrix generated by the base matrix shown in FIG. 13B or 13C, the two layers (for example, Layer 0 and Layer 3) are simultaneously operated. can do. That is, as illustrated in FIG. 13D, Layers 0, 6, 4, 2 and Layers 3, 1, 7, and 5 may be processed in parallel with each other to simultaneously process each layer. As a result, when performing LDPC decoding using the parity check matrix according to an embodiment of the present invention, it is possible to obtain the same effect as decoding two LDPC codes at once through two operation units, and the decoding time is maximum. A reduction of up to 50% can be achieved.

14 shows another embodiment of the base matrix when the code rate is 2/3. In the basic matrix, '-1' represents a zero matrix and an arbitrary integer represents an arbitrary permutation matrix formed by shifting the basic permutation matrix in a row or column direction by any integer of 0 or more. In the basic matrix of FIG. 14, 'X' is a value representing an arbitrary integer from 0 to 95, and is preferably one of 86, 89, and 95. Most preferably X = 95. The basic matrix of FIG. 14 has a parallel processing feature and has been proposed to have high performance. The parallel processing feature means that a decoding method for processing layered decoding in parallel can be applied according to the present invention. The embodiment groups the rows of the parity check matrix generated by the base matrix of FIG. 14 into one layer according to the size of the base permutation matrix for the base matrix. That is, the number of rows included in each layer in FIG. 14 is the same as the number of rows in the basic permutation matrix according to the basic matrix of FIG. 14. When dividing the rows of the base matrix according to the index of 1,2,3,4,5,6,7,8, the base matrix generated by exchanging the rows is zero or more between adjacent rows. The components with shift numbers do not non-overlapping with each other. For example, when the first row is compared with the fourth row, it can be seen that components having a shift number of 0 or more in any column direction do not overlap each other. In addition, referring to the parity check matrix generated by the base matrix of FIG. 14, one row of the base matrix represents one layer of the generated parity check matrix. Between each layer of the matrix, the position where the weight exists does not overlap in the column direction.

FIG. 15 is one of several examples of the base matrix created by the exchange of rows satisfying the conditions described above in the base matrix of FIG. The basic matrix of FIG. 15 is an example in which the indices of the basic matrix of FIG. 14 are exchanged in the order of 1-4-7-2-5-8-3-6. Figure 15 adds the first row to easily compare the first row with the last row of the base matrix in index order of 1-4-7-2-5-8-3-6. (Ie, 1-4-7-2-5-8-3-6- (1)).

All base matrices generated by exchanging rows of the base matrix shown in FIG. 15 will define the same LDPC code as the LDPC code defined by the base matrix of FIG. 14. Accordingly, in decoding and encoding, decoding and encoding having the same performance as that of the basic matrix of FIG. 8 can be performed using the basic matrix in which rows are interchanged.

High performance in the above description means that the Frame Error Rate (FER) is good, for example. In addition, decoding with the same performance means a decoding method showing the same decoding performance, and encoding with the same performance means generating the same codeword.

Hereinafter, an LDPC decoder for performing an LDPC decoding operation using various basic matrices proposed by the present invention will be described. 16 is a block diagram illustrating an embodiment of an LDPC decoder according to the present invention. The LDPC decoder 1000 includes a check node update unit (CNU) block 1100, a control block 1200, a variable node update unit (VNU) block 1300, and a memory block 1400. The Check Node Update Unit (CNU) block 1100 performs a check node update of a check node and includes at least one Check Node Update Unit (CNU) 1110. The CNU 1110 is a processing unit for performing a probability value update of the check node. The control block 1200 may include a control unit 1210 for controlling an operation of each unit of the decoder 1000, and the CNU block 1100 and the memory block 1400 according to a structure of a parity check matrix. A parity check matrix index storage for storing CNU routing network 1220 for controlling, the VNU routing network 1230 for controlling the VNU block 1100 and the memory block 1400, and information on the structure of the parity check matrix. A unit 1240 includes a hard decision unit 1250 for determining a decoding value using the updated probability value and checking the determined decoding value. The Variable Node Update Unit (VNU) block 1100 performs a variable node update of a bit node and includes at least one Variable Node Update Unit (VNU) 1310. The VNU 1310 is a processing unit for performing a probability value update of the check node. The CNU 1110 and the VNU 1310 controlled by the control block 1200 calculate and update a probability value for a non-zero component of the H matrix. The calculated probability value is updated by the memory unit 1400 ). The memory unit 1400 includes an R-memory 1410 storing a probability value calculated for updating a probability value from a check node to a bit node, and a probability calculated for updating a probability value from a bit node to a check node. Received LLR memory 1420, which stores a value (e.g., a Log Likelihood Ratio value received from a wireless channel) and a calculated probability value for updating the probability value from the bit node to the check node. Q-memory 1430 is included.

)를 저장하며, 상기 Q-메모리(1430)는 특정한 비트 노드에서의 확률 값 갱신(variable node update)의 결과(

)를 저장한다. 상기 제어유닛(1210)은 각 유닛의 동작 순서 및 각 유닛의 동작 타이밍을 제어하며, 상기 패리티 검사 행렬 인덱스 저장부(1240)는 상기 패리티 검사 행렬의 무게(weight)의 위치 등에 관한 정보를 저장한다. 또한, 상기 CNU 라우팅 네트워크(1220)는, 상기 패리티 검사 행렬 인덱스 저장부(1240)로부터 상기 패리티 검사 행렬에 관한 정보를 획득하여, 상기 CNU(1110)와 상기 메모리부(1400)의 메모리들을 적절히 연결한다. 또한, 상기 VNU 라우팅 네트워크(1230)는, 상기 패리티 검사 행렬 인덱스 저장부(1240)로부터 상기 패리티 검사 행렬에 관한 정보를 획득하여, 상기 VNU(1310)와 상기 메모리부(1400)의 메모리들을 적절히 연결한다. 상기 경판정부(1250)는, 상기 Q-메모리(1430)를 이용하여 복호 값을 결정하고, 상기 결정된 복호 값(c')을 검사하는 유닛 으로, 상기 복호 값(c')이

의 검사식을 만족하는 경우 상기 복호 값(c')을 참값으로 출력하고, 만약 상기 검사식을 만족하지 못하는 경우 일정한 최대 반복 복호 횟수 이내에서 복호를 반복한다. Each of the above units will be described as follows. The received LLR memory 1420 is a memory capable of storing a probability value for a received signal to be decoded, for example, an LLR value for a codeword of a received signal. In addition, the R-memory 1410 stores the result of the check node update at a specific check node

, And the Q-memory 1430 stores the result of the variable node update at a specific bit node

). The control unit 1210 controls the operation sequence of each unit and the operation timing of each unit, and the parity check matrix index storage unit 1240 stores information on the position and the like of the weight of the parity check matrix . The CNU routing network 1220 obtains information on the parity check matrix from the parity check matrix index storage unit 1240 and appropriately connects the memories of the CNU 1110 and the memory unit 1400 do. The VNU routing network 1230 obtains information on the parity check matrix from the parity check matrix index storage unit 1240 and connects the memories of the VNU 1310 and the memory unit 1400 do. The hard decision unit 1250 is a unit that determines a decoded value by using the Q-memory 1430 and checks the determined decoded value c '.

And outputs the decoded value c 'as a true value. If the check expression is not satisfied, decoding is repeated within a certain maximum iterative decoding number.

The decoder 1000 of FIG. 16 decodes a received signal using a parity check matrix stored in a separate memory (not shown) or the parity check matrix index storage unit 1240, or generates a base signal and a base permutation matrix. The received signal may be decoded using the parity check matrix. When generating a parity check matrix through the base matrix and the base permutation matrix, the decoder 1000 may store a base unit and a base permutation matrix, and a storage unit (not shown) and the base matrix and the base permutation matrix. It is preferable to include a parity check matrix generator (not shown) for generating the parity check matrix by using. In addition, the decoder 1000 of FIG. 16 may generate a new parity check matrix by adjusting the order of rows of the parity check matrix (for example, the order of layers). In this case, the decoder 1000 preferably includes a parity check matrix adjusting unit (not shown) for adjusting the order of rows of the parity check matrix.

Hereinafter, the operation of the LDPC decoder 1000 will be described. The LDPC decoder 1000 may perform decoding using a Log BP (Log Belief Propagation) algorithm, which is one of the LDPC decoding algorithms. The decoder 1000 performs operations according to an initialization step, a check node update step, a variable node update step, and a hard decision step. In the initializing step, the probability value for the received signal transmitted from the transmitter is stored in the reception LLR memory 1420, and the probability value stored in the reception LLR memory 1420 is stored in the parity check matrix index storage unit 1240. And storing information on the weight of the parity check matrix stored in the memory at a specific position of the Q-memory 1430. The check node update step performs check node update, i.e., update from the check node to the bit node, using the probability value stored in the Q-memory 1430, and outputs the result to the R- (1410). The variable node update step performs bit node update, that is, update from the bit node to the check node, using the probability value stored in the R-memory 1410, and outputs the result to the Q- (1430). The hard decision step may temporarily determine a decoded value c 'using the probability value stored in the Q-memory 1430, check the determined decoded value c' And outputting the true value when the value c 'is a true value, and repeating the check node update step and the variable node update step within a specific number of iterative decoding cycles if the true value is not true .

&Quot; (3) "

When the parity check matrix H used by the decoder 1000 is equal to Equation 3, the R-memory 1410 and the Q-memory 1430 are non-zero components of the parity check matrix. That is, 1 stores the value of the position of the component present. Accordingly, the R-memory 1410 and the Q-memory 1430 store the values of the following locations.

However, since the R-memory 1410 and the Q-memory 1430 only need to store a value corresponding to the position of the non-zero component, the result of the operation for updating the probability value in the structure as shown in FIG. 17. Can be stored. Therefore, the memory required for LDPC decoding is proportional to the weight of the H matrix. Position information regarding the weight of the parity check matrix illustrated in FIG. 17 is stored in the parity check matrix index storage 1240. As described above, the decoder 1000 generates a parity check matrix using a base matrix and a basic permutation matrix to perform a decoding operation, or performs a decoding operation using a parity check matrix stored in a specific memory. The decoding operation may be performed using the parity check matrix generated by any method. The parity check matrix described below refers to the actual parity check matrix, not the base matrix. There is no limitation on the method of generating the parity check matrix, and the parity check matrix may be generated using a base matrix and a basic permutation matrix, or may be generated by obtaining a parity check matrix stored in a specific memory or an external device.

18 is a diagram illustrating an example of a connection form of a CNU, a VNU, and a memory of a decoder that performs decoding by using the H matrix of Equation 3 above. The decoder of FIG. 18 is an example in the case of having four CNUs and eight VNUs. 19A to 19H illustrate a process of performing one iteration during an initialization process in which a probability value for a received signal is input when decoding is performed using the decoder illustrated in FIG. 18. Coordinates displayed on the R-memory 1410 and the Q-memory 1430 of FIGS. 19A to 19H indicate a memory address when the memory is configured as shown in FIG. 17.

19A is a diagram illustrating an initialization step in LDPC decoding. The component shown in the figure represents a nonzero component in the H matrix, and the probability value received from the transmitting side is input to a memory address corresponding to the nonzero component.

19B to 19E are diagrams illustrating probability value updates from check nodes to bit nodes. The probability value update of the specific position is an operation of updating the own component using the remaining components except for the own component in a specific row. 19F to 19H are diagrams illustrating probability value updates from bit nodes to check nodes. Updating the probability value of the specific position is an operation of updating its own component by using components other than its own component in a specific column.

After the process up to FIG. 19H, the codeword is temporarily determined with reference to the Q-memory 1430, and the temporarily determined codeword c 'satisfies the check expression Hc' = 0. Check whether or not. If the test equation is not satisfied, the processes of FIGS. 19B to 19H are repeated. If there is a predetermined number of iterations or a codeword satisfying the check expression is obtained, the process is terminated.

Hereinafter, the operation of the LDPC decoder 1000 for parallelly processing layered decoding with parallel processing will be described.

In accordance with an embodiment of the present invention, the CNU 1110 and the VNU 1310 of the LDPC decoder 1000 update the probability value through an operation as shown in Equation (4). Equation 4 below is an equation used to perform one iteration decoding.

&Quot; (4) "

The variables used in the above equation are as follows.

: m번째 variable node에서 j번째 check node로 연결된 LLR(Log Likelihood Ratio) 값

: Log Likelihood Ratio (LLR) value connected to the jth check node at the mth variable node

: j번째 variable node의 사후 LLR 값 (a posterior LLR value)

: the posterior LLR value of the jth variable node (a posterior LLR value)

: j번째 check node에서 m번째 variable node로 연결된 LLR 값

: LLR value connected from the jth check node to the mth variable node

: j번째 check node에서 m번째 variable node로 연결된 LLR 값을 계산하기 위한 중간변수(dummy variable)

: Dummy variable to calculate the LLR value connected from the j th check node to the m th variable node

: j번째 check node에서 m번째 variable node로 연결된 LLR 값들의 부호를 계산하기 위한 중간변수(dummy variable)

: a dummy variable for computing the sign of the LLR values connected to the mth variable node at the jth check node,

:check node Index of Parity check matrix

: check node Index of parity check matrix

: Variable node index of Parity check matrix

: Variable node index of parity check matrix

Equation (5) is an example of LLR (Log Likelihood Ratio) of a received signal, and Equation (6) is an example of a parity check matrix used by the decoder 1000 according to an embodiment of the present invention.

[Equation 5]

&Quot; (6) "

The matrix of Equation (6) is an example of a parity check matrix used in the decoder 1000 according to an embodiment of the present invention. In the matrix, one row of the parity check matrix represents one layer. Each of the layers does not overlap with a layer adjacent to each other. The number of the CNU 1110 and the VNU 1310 of the decoder 1000 may be determined according to the structure of the parity check matrix. In addition, the non-overlapping layers are parallelized, and the number of CNUs 1110 is more preferably the number of rows included in the paralleled layers, and the number of VNUs 1310 is More preferably, it is the number of columns of the parity check matrix. Therefore, it is preferable that the number of CNUs 1110 of the decoder 1000 using Equation (6) is 2, and that the number of VNUs 1310 is 24.

,

값을 저장하는 메 모리의 상태를 나타내며, '###'는 아직 특정한 값으로 정해지지 않은 임의의 값을 나타낸다. 상기 도 20a 내지 도 20i의 Q-메모리(1430)와 R-메모리(1410)는, 도 17에 도시된 형태와 같이 0이 아닌 성분의 위치에 해당하는 연산 값만을 저장할 수 있다. 20A to 20I illustrate a process of performing one iteration when decoding is performed by the LDPC decoding method of the present invention. Q and R of FIG. 20A to FIG. 20I are represented by Equation 4

,

It represents the state of memory that stores a value, and '###' represents any value that has not been set to a specific value yet. The Q-memory 1430 and the R-memory 1410 of FIGS. 20A to 20I may store only operation values corresponding to positions of non-zero components, as shown in FIG. 17.

20A illustrates an initialization step in LDPC decoding according to an embodiment of the present invention. The received probability value is stored in the received LLR memory 1420, and the received probability value is stored in the parity check matrix stored in the parity check matrix index storage unit 1240 (for example, memory 1430 in accordance with the positional information on the Q-memory 1430. [ 20A illustrates a probability value input to the Q memory through the initialization step.

20B illustrates a process of updating probability values from check nodes to bit nodes for Layer 0 and Layer 3 of the H matrix. The CNU 1110 performs an operation of updating a probability value from a check node to a bit node with respect to Layer 0 and Layer 3 of the H matrix. As described above, two CNUs 1110 operate, and two CNUs 1110 perform a check node update process for Layer 0 and Layer 3. The result of the operation is stored in the R-memory 1410.

20c illustrates a process of updating a probability value from a bit node to a check node for Layer 0 and Layer 3 of the H matrix. Unlike the conventional LDPC decoding process, the process of updating the probability value from the bit node to the check node has a probability value of the current layer using the probability value of the layer already updated in the same iteration step. Update the. Since Layer 0 and Layer 3 do not overlap with each other, there is no memory conflict due to parallel processing or dependency between parallel processing data. Therefore, the probability value updating process from the bit node to the check node for the layer 0 and the probability value updating process from the bit node to the check node for the layer 3 can be performed in parallel. As described above, the decoder performs operations on Layer 0 and Layer 3 using 24 VNUs 1310. 20c shows a probability value for updating a probability value from a check node to a bit node for layer 6 and layer 1 together with a result of performing a probability value update from a bit node to a check node for the layer 0 and layer 3. This shows the result of the setting step being input.

FIG. 20D illustrates a process of updating a probability value from a check node to a bit node with respect to Layer 6 and Layer 1 of the H matrix, and FIG. 20E illustrates a probability from a bit node to a check node with respect to Layer 6 and Layer 1 of the H matrix. FIG. 20F illustrates a process of updating a probability value from a check node to a bit node for Layer 4 and Layer 7 of the H matrix, and FIG. 20G illustrates a bit node for Layer 4 and Layer 7 of the H matrix. Shows a process of updating the probability value from the check node to the bit node for Layer 2 and Layer 5 of the H matrix, and FIG. 20I shows the process of updating the probability value from the check node to the bit node. For layer 5, the process of updating the probability value from the bit node to the check node is shown. The value stored in the Q-memory 1430 is an operation value obtained through one iteration. The hard decision unit 1250 temporarily determines a codeword c 'with reference to the Q-memory 1430 after performing the process up to FIG. 20i, and the codeword c' is a check expression ( Check whether Hc '= 0) is satisfied. If the test equation is not satisfied, the decoder repeats the process of FIGS. 20B to 20I. If there is a maximum number of iterations or if a codeword satisfying the check expression is obtained, the process ends and the codeword c 'is output to the outside.

The decoding method illustrated in FIG. 20 has the following differences as compared to the decoding method illustrated in FIG. 19. The decoding method illustrated in FIG. 19 performs a check node update process and a bit node update process using a maximum number of CNUs and VNUs according to the size of the parity check matrix. The illustrated decoding method includes as many CNUs as the number of Layers without data dependency, that is, the number of layers that do not overlap each other in the parity check matrix, and according to the number of Layers without data dependency. Parallel processing may be performed on a check node update process.

In addition, while the decoding method shown in FIG. 19 initializes the entire area of the Q-memory 1430 by using the probability value of the received signal, the decoding method shown in FIG. 20 is capable of parallel processing at the same time. Initialize the layer and use the result of the layers as the initial value for the next layer.

It will be apparent to those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the above detailed description should not be construed as limiting in all aspects and should be considered as illustrative. The scope of the invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the invention are included in the scope of the invention.

According to the encoding and decoding method using the LDPC code according to the present invention, there is an effect that the performance at the time of encoding or decoding data at the transmitting or receiving side can be improved.

Claims (21)

In the decoding method using Low-Density Parity-Check (LDPC), Receiving a signal encoded using the parity check matrix H; And Decoding the received signal using the parity check matrix H, The rows of the parity check matrix H are grouped into a plurality of layers, each layer comprising one or more columns, The decoding step simultaneously decodes the received signal in parallel in units of a predetermined number of layers that do not overlap, The parity check matrix H is generated by extending a base matrix H _b defined as follows:

, Wherein -1 represents a zero matrix, a non-negative integer represents a shift number that is a shifted amount of a row or column of the basic permutation matrix, and X is an integer between 0 and 95, Decryption method. The method of claim 1, Non-zero elements in the predetermined number of layers do not overlap in a column direction, Decryption method. delete The method of claim 1, The base matrix H _b is for a code rate of 2/3, Decryption method. The method of claim 1, One row of the base matrix H _b corresponds to one layer of the parity check matrix H, Characterized in that, among the rows of the basic matrix H _b , rows having a shift number greater than zero do not overlap in the column direction correspond to the predetermined number of layers simultaneously decoded in parallel. Decryption method. The method according to any one of claims 1, 2, 4 and 5, If the rows of the base matrix H _b are indexed as 1 and 2, 3, 4, 5, 6, 7, 8, then

The rows of the base matrix H _b are permutated as follows so that a component with a shift number greater than zero does not overlap between any two adjacent rows.

, Wherein the permuted base matrix is used in the decoding step, Decryption method. In the decoding method using Low-Density Parity-Check (LDPC), Receiving a signal encoded using the parity check matrix H; And Decoding the received signal using the parity check matrix H, The parity check matrix H is generated from a base permutation matrix and a base matrix H _b , The base matrix H _b is defined as follows:

, Wherein -1 represents a zero matrix, a non-negative integer represents a shift number that is a shifted amount of a row or column of the basic permutation matrix, and X is an integer between 0 and 95, Decryption method. The method of claim 7, wherein The base matrix H _b is for a code rate of 2/3, Decryption method. In the encoding method using Low-Density Parity-Check (LDPC), Generating a parity check matrix H using a base permutation matrix and a base matrix H _b ; And Encoding source data using the parity check matrix H, The base matrix H _b is defined as follows:

, Wherein -1 represents a zero matrix, a non-negative integer represents a shift number that is a shifted amount of a row or column of the basic permutation matrix, and X is an integer between 0 and 95, Encoding method. 10. The method of claim 9, The base matrix H _b is for a code rate of 2/3, Encoding method. In a decoding apparatus using low-density parity check (LDPC), A receiving module, configured to receive a signal encoded using the parity check matrix H; And A decoding module configured to decode the received signal using the parity check matrix H; The rows of the parity check matrix H are grouped into a plurality of layers, each layer comprising one or more columns, The decoding module is configured to simultaneously decode in parallel in units of a predetermined number of layers that do not overlap the received signal, The decoding module uses a matrix generated by extending a base matrix H _b defined as the parity check matrix H:

, Wherein -1 represents a zero matrix, a non-negative integer represents a shift number that is a shifted amount of a row or column of the basic permutation matrix, and X is an integer between 0 and 95, Decryption device. 12. The method of claim 11, Non-zero elements in the predetermined number of layers do not overlap in a column direction, Decryption device. delete 12. The method of claim 11, The base matrix H _b is for a code rate of 2/3, Decryption device. 12. The method of claim 11, One row of the base matrix H _b corresponds to one layer of the parity check matrix H, Characterized in that, among the rows of the basic matrix H _b , rows having a shift number greater than zero do not overlap in the column direction correspond to the predetermined number of layers simultaneously decoded in parallel. Decryption device. The method according to any one of claims 11, 12, 14 and 15, If the rows of the base matrix H _b are indexed as 1 and 2, 3, 4, 5, 6, 7, 8, then

The rows of the base matrix H _b are permutated as follows so that a component with a shift number greater than zero does not overlap between any two adjacent rows.

, Wherein the permuted base matrix is used in the decoding step, Decryption device. In a decoding apparatus using low-density parity check (LDPC), A receiving module, configured to receive a signal encoded using the parity check matrix H; And A decoding module configured to decode the received signal using the parity check matrix H, The decoding module uses a matrix generated from a base permutation matrix and a base matrix H _b , wherein the parity check matrix H is. The base matrix H _b is defined as follows:

, Wherein -1 represents a zero matrix, a non-negative integer represents a shift number that is a shifted amount of a row or column of the basic permutation matrix, and X is an integer between 0 and 95, Decryption device. 18. The method of claim 17, The base matrix H _b is for a code rate of 2/3, Decryption device. In the encoding device using a low-density parity check (LDPC), A parity check matrix generator configured to generate a parity check matrix H using a base permutation matrix and a base matrix H _b ; And An encoding module configured to encode source data using the parity check matrix H, The parity check matrix is configured to use as the base matrix H _b a matrix defined as follows:

, Wherein -1 represents a zero matrix, a non-negative integer represents a shift number that is a shifted amount of a row or column of the basic permutation matrix, and X is an integer between 0 and 95, Encoding device. 20. The method of claim 19, The base matrix H _b is for a code rate of 2/3, Encoding device. delete

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