CN103036577B - A kind of low-density checksum LDPC code coding circuit structure of low complex degree - Google Patents

Abstract

A low-density checksum LDPC code coding circuit structure for low complex degree, the coding circuit structure of this LDPC code comprises multiplying operational circuit, adder operation circuit, and control circuit.This coding circuit is undertaken by row operation by the original uncoded information sequence of input and the check matrix of LDPC code, finally asks for verification sequence to realize.This coding circuit structure is greater than 0.5 for code check, there is the quasi-cyclic LDPC code of near lower triangular form, adopt the mode according to the row operation of advancing of LDPC check matrix, reduce hardware resource, and adopt the compute mode of part parallel, ensure the data throughout of coding circuit, realize the low encoding complexity of the quasi-cyclic LDPC code had close to lower triangular form.

Description

A kind of low-density checksum LDPC code coding circuit structure of low complex degree

Technical field

The invention belongs to digital signal and system regions, relate to the realization of the LDPC code error correcting code circuitry in transfer of data error correcting technique.Being specifically related to the realization of the coding circuit of the LDPC code for the quasi-cyclic with near lower triangular form, is a kind of coding circuit structure of LDPC code of low complex degree.

Background technology

The object of communication is that ignorant for the other side message is sent to the other side in time reliably, improves reliability and the validity of information transmission, is the target that communication work is pursued all the time.Chnnel coding is transmission reliability in order to ensure communication system, overcome Noise and Interference in channel and the jamproof techniques and methods of a custom-designed class.The verification code element adding some necessity that it is artificial in information code element to be sent according to certain rule, at receiving terminal, utilizes the law discovery of these inspection code elements and information code element and corrects mistake, to improve the reliability of information code element transmission.Code element information to be sent is information code element, and artificial adds unnecessary code element for verification code element.The object of chnnel coding attempts to exchange for minimum verification code element the raising of maximum reliability.

In a communications system, error correction coding is used to the reliability and the power utilization that improve transmission, and LDPC (Low-density Parity-check, low-density checksum) code is a kind of error correction coding of better performances.LDPC code is proposed by Gallager at first, but do not cause enough attention, until after Turbo code proposition, people are when studying the iterative decoding of Turbo code, both discoveries have identical characteristic, namely retrain the characteristic of random code set and iterative decoding, start the research climax of LDPC code subsequently.

LDPC code is approached the performance of shannon limit with it and can be realized the feature of iterative decoding by complete parallel, performance is better than other channel coding/decodings in many situations, become the focus of channel error correction encoding research in wireless sense network just gradually, many Systematic selection have been had to use LDPC code, as satellite digital video broadcast standard DVB-S2 and next generation mobile communication system at present.

Be different from other linear block codess, LDPC code is represented by its H matrix.The characteristic of H matrix directly has influence on the encoder complexity of LDPC code.The subject matter that LDPC code faces is its higher encoder complexity and encoding time delay.If adopt common coded system, LDPC code encoder has the encoder complexity becoming quadratic power with code length, and when code length is longer, this is difficult to accept.Therefore, when practical application, main consideration has the LDPC code of the check matrix of ad hoc structure.

LDPC code is a kind of linear error correction code with sparse check matrix.The element of its check matrix except sub-fraction be except 1, other overwhelming majority are zero.Be different from other linear block codess, LDPC code is represented by its check matrix H, and general coded system is also that generator matrix G is converted to check matrix H to complete coding.The common encryption algorithm of LDPC code has: G matrix implementation method, RU decomposition algorithm, LU predecomposition algorithm etc.Wherein RU decomposition algorithm is the most frequently used encryption algorithm of structurized LDPC code.

Summary of the invention

The problem to be solved in the present invention is: be greater than at code check in the LDPC code coding circuit of 0.5 and adopt the coded system of part parallel by row to have great advantage, and current LDPC code coding circuit adopts full parellel or the compute mode of pressing row part parallel, code check being greater than to the LDPC code of 0.5, needing more barrel shifter and accumulator element by row coding compared to encoding by row.

Technical scheme of the present invention is: a kind of low-density checksum LDPC code coding circuit structure of low complex degree, is characterized in that:

Applying the input information from information source that this circuit structure carries out encoding is: the information sequence s of input and verification sequence p is divided into k by z position _b=n _b-m _bindividual group, then therefore whole code word can be expressed as: $c=\left[\begin{array}{cc}s& p\end{array}\right]=[s_0,s_1,....,s_{k_b-1},p_0,p_1,....,p_{m_b-1}]$

If check matrix H is expressed as: H=[H ₁h ₂], H ₁corresponding to information sequence part, H ₂corresponding to check code word part, h _{i, j}for the matrix in block form in check matrix H, a point block size is z;

According to Hc ^t=0 and H ₁and H ₂feature obtain

Definition i=0,1 ..., m _b-1, equation above can be expressed as,

According to p ₀try to achieve: p ₁=λ ₀+ ∏ ₁p ₀

$p_{m_b-1}={\mathrm{\λ}}_{m_b-1}+{\mathrm{\Π}}_1{p}_0$

p _x+1＝λ _x+p ₀+p _x

p _i+1=λ _i+p _ii≠0,x,m _b-1

Wherein x is corresponding verification sequence part H in check matrix H ₂in first be classified as the element place of 0 row value;

Wherein parameter declaration is as follows:

Z is point class value of low density parity check code;

K _bfor inputting the group number that information sequence to be encoded carries out according to z position dividing into groups;

N _bfor the sequence after encoded carries out the group number that divides into groups according to z position;

M _bfor check code word carries out the group number that divides into groups according to z position;

S is information sequence, obtains by after the grouping of z position:

P is check code word, obtains by after the grouping of z position:

P _ifor i-th grouping of pressing after the grouping of z position of check code word p;

C be encoded after whole codeword sequence;

H is check matrix, H ₁corresponding to information sequence part, H ₂corresponding to check code word part;

X is corresponding verification sequence part H in check matrix H ₂in first matrix in block form be the line number at the row place of " 0 ".

According to the computational methods of check code word above, the information sequence of input is according to the grouping input of z position;

This circuit structure comprises check matrix memory 801, barrel shifter group 802, accumulator group 803, first-in first-out buffer memory 804, first data selector 805, check code word computing module 806, second data selector 807, address counter 808, control circuit 809 and input control module 810;

Described barrel shifter group 802 comprises m _bindividual identical barrel shifter group; Accumulator group 803 comprises m _bindividual identical accumulator; m _bvalue identical with the line number of the check matrix of LDPC code; The corresponding accumulator of each barrel shifter group;

The information sequence of input is according to the grouping input of z position, and each group information sequence of input is through the check matrix by row corresponding multiplying of barrel shifter group 802 with the LDPC code be stored in check matrix memory 801; This multiplying is completed by barrel shifter, and the operation result of barrel shifter is h _{i, j}s _j;

The operation that input control circuit 810 controls is: often input one group of information sequence, complete multiplication operation, and the address of check matrix memory 801 adds 1 simultaneously, provides the value of check matrix next column;

Each organizes the result of information sequence through multiplying through accumulator group 803, adds up by corresponding row;

After the input of all information sequences, the grouping by row namely completing the information sequence position corresponding to check matrix of input is multiplied and accumulating operation, and result cumulative is by row λ _i;

Control circuit 809, first data selector 805 and check code word computing module 806 pass through to add up, be shifted and register circuit, the result λ cumulative to piecemeal _iagain selectively carry out rear adding up of adding up or be shifted, section technique goes out check code word p thus; Namely the process of whole coding is completed;

Finally, the information sequence of input, through first-in first-out buffer memory 804, is exported continuously by the second data selector 807 with check code word, obtains the code word with fault-tolerant ability.

Accompanying drawing explanation

Fig. 1 is LDPC code position in a communications system;

Fig. 2 is a kind of check matrix with the LDPC code of the near lower triangular form of quasi-cyclic;

Fig. 3 is the coding circuit structure of the LDPC code of low complex degree;

Fig. 4 is the implementation of the matrix multiplication operation of LDPC code.

Embodiment

In order to understand the present invention better, make a more detailed description below in conjunction with embodiment and place system.

Technical scheme of the present invention is a kind of error correcting code circuitry structure being applied to the low density parity check code of communication system, this circuit structure is according to LDPC check matrix, carry out a point row operation, then ask for the check code word of input message sequence, realize the low encoding complexity with the quasi-cyclic LDPC code of near lower triangular form; Specific as follows:

This coding circuit structure is the quasi-cyclic LDPC code of near lower triangular form for check matrix; The check matrix H with the LDPC code of this characteristic generally adopts the form of piecemeal to represent, each matrix-block wherein after piecemeal, and the overwhelming majority is null matrix, and other matrix is the result after the unit matrix cyclic shift of z position, and z is the size of the partitioning of matrix;

In the process of coding, the information sequence of input is also according to the grouping input of z position, and each group information sequence of input carries out corresponding multiplying by row through barrel shifter group with the check matrix of LDPC code, and this multiplying is completed by each barrel shifter.In barrel shifter group, the quantity of barrel shifter is identical with the line number of the check matrix of LDPC code.

Input control circuit controls often to input one group of information sequence, completes multiplication operation, and the address of check matrix memory adds 1 simultaneously, provides the value of check matrix next column.Each group information sequence, through the result of multiplying, through accumulator group, adds up by the row of correspondence, and after the input of all information sequences, the grouping by row namely completing the information sequence position corresponding to check matrix of input is multiplied and accumulating operation.

Control circuit control the 1st data selector, and check code word calculating module, by circuit such as cumulative, displacement and registers, the result cumulative to piecemeal above carries out rear adding up of adding up or be shifted again selectively, and section technique goes out check code word thus.Finally, the information sequence of input, through first-in first-out buffer memory, is exported by the 2nd data selector continuously with the check code word calculated, and finally obtains the code word that information sequence has fault-tolerant ability after the check matrix coding of this LDPC code.

Fig. 1 is telecommunication system transceiver structure chart, after LDPC is coded in the information source of transmitter, before modulation, for improving the reliability of transfer of data, receiver section corresponding have LDPC decoding circuit.

Fig. 2 (a) and (b) are a kind of check matrix with the LDPC code of the near lower triangular form of quasi-cyclic, giving a kind of code check in Fig. 2 (a) is 2/3, code length is the check matrix H of the LDPC code of 576, this check matrix adopts the form of the partitioning of matrix to represent, the result that in Fig. 2 (a) figure, the unit matrix of each data representation length z=24 of form is undertaken after ring shift right by the numerical value in form, such as, in Fig. 2 (a), the data of the first row first row carry out the result after ring shift right, are the matrix shown in Fig. 2 (b).Can see from Fig. 2 (a), the most elements in form are zero, also illustrate that the openness of the check matrix of LDPC code.

Fig. 3 is the coding circuit structure with the LDPC code of low complex degree provided, in the process of coding, the information sequence of input is also according to the grouping input of z position, each group information sequence of input carries out corresponding multiplying by row through barrel shifter group 802 with the check matrix 801 of LDPC code, and this multiplying is completed by barrel shifter.In barrel shifter group 802, the quantity of barrel shifter is identical with the line number of the check matrix of LDPC code.

Input control circuit 810, control often to input one group of information sequence, complete multiplication operation, the address of check matrix memory adds 1 simultaneously, provides the value of check matrix next column.Each group information sequence, through the result of multiplying, through 803 accumulator groups, adds up by the row of correspondence, and after the input of all information sequences, the grouping by row namely completing the information sequence position corresponding to check matrix of input is multiplied and accumulating operation.

Control circuit 809, the first data selector 805, and check code word computing module 806, by cumulative, the circuit such as displacement and register, the result cumulative to piecemeal above selectively carries out rear adding up of adding up or be shifted again, and section technique goes out check code word thus.Finally, the information sequence of input, through first-in first-out buffer memory, is exported by the second data selector 807 continuously with the check code word calculated, and finally obtains the code word that information sequence has fault-tolerant ability after the check matrix coding of this LDPC code.

Fig. 4 is the barrel shifter carrying out matrix multiplication operation, and above-mentioned matrix multiplication operation can adopt the barrel shift structure provided in figure to realize.The figure place of the barrel shifter provided in figure is z=8, input data a0-a7, and barrel shifter controls the situation of displacement by input data s0-s2, and the mux finally obtained in the data d0 that is shifted-d7, figure is the data selector of alternative.

Claims (1)

1. a low-density checksum LDPC code coding circuit structure for low complex degree, is characterized in that:

Apply this circuit structure, the information sequence s of input and verification sequence p is divided into k by z position _b=n _b-m _bindividual group, then $s=[s_0,s_1,....s_{k_b-1}],p=[p_0,p_1,....,p_{k_b-1}],$ Therefore whole code word can be expressed as:

$c=\left(\begin{array}{cc}s& p\end{array}\right]=[s_0,s_1,....,s_{k_b-1},p_0,p_1,....,p_{m_b-1}];$

If check matrix H is expressed as: H=[H ₁h ₂], H ₁corresponding to information sequence part, H ₂corresponding to check code word part, h _i,jfor the matrix in block form in check matrix H, i=0,1 ..., m _b-1, j=0,1 ..., k _b-1, a point block size is that z, i represent line number, and j represents row number, according to Hc ^t=0 and H ₁and H ₂feature obtain

Definition i=0,1 ..., m _b-1, equation above can be expressed as,

According to p ₀try to achieve: p ₁=λ ₀+ ∏ ₁p ₀

$p_{m_b-1}={\mathrm{\λ}}_{m_b-1}+{\mathrm{\Π}}_1{p}_0$

p _x+1＝λ _x+p ₀+p _x

p _i+1＝λ _i+p _ii≠0,x,m _b-1

Wherein parameter declaration is as follows:

Z is point class value of low density parity check code;

K _bfor inputting the group number that information sequence to be encoded carries out according to z position dividing into groups;

N _bfor the sequence after encoded carries out the group number that divides into groups according to z position;

M _bfor check code word carries out the group number that divides into groups according to z position;

S is information sequence, obtains by after the grouping of z position:

P is check code word, obtains by after the grouping of z position:

P _ifor i-th grouping of pressing after the grouping of z position of check code word p;

C be encoded after whole codeword sequence;

H is check matrix, H ₁corresponding to information sequence part, H ₂corresponding to check code word part;

X is corresponding verification sequence part H in check matrix H ₂in first matrix in block form be the line number at the row place of " 0 ";

According to the computational methods of check code word above, the information sequence of input is according to the grouping input of z position;

This circuit structure comprises check matrix memory 801, barrel shifter group 802, accumulator group 803, first-in first-out buffer memory 804, first data selector 805, check code word computing module 806, second data selector 807, address counter 808, control circuit 809 and input control module 810;

Described barrel shifter group 802 comprises m _bindividual identical barrel shifter group; Accumulator group 803 comprises m _bindividual identical accumulator; m _bvalue identical with the line number of the check matrix of LDPC code; The corresponding accumulator of each barrel shifter group;

The information sequence of input is according to the grouping input of z position, and each group information sequence of input is through the check matrix by row corresponding multiplying of barrel shifter group 802 with the LDPC code be stored in check matrix memory 801; This multiplying is completed by barrel shifter, and the operation result of barrel shifter is h _i,js _j;

The operation that input control module 810 controls is: often input one group of information sequence, complete multiplication operation, and the address of check matrix memory 801 adds 1 simultaneously, provides the value of check matrix next column;

Each organizes the result of information sequence through multiplying through accumulator group 803, adds up by corresponding row;

After the input of all information sequences, the grouping by row namely completing the information sequence position corresponding to check matrix of input is multiplied and accumulating operation, and result cumulative is by row λ _i;

Control circuit 809, first data selector 805 and check code word computing module 806 pass through to add up, be shifted and register circuit, the result λ cumulative to piecemeal _iagain carry out rear adding up of adding up or be shifted, section technique goes out check code word;

Finally, the information sequence of input, through first-in first-out buffer memory 804, is exported continuously by the second data selector 807 with check code word, obtains the code word with fault-tolerant ability.