TWI719880B - Apparatus and method for programming data of page groups into flash units - Google Patents

Abstract

A method for programming data of page groups into flash modules is introduced to include: storing, by a host interface controller, user data of multiple pages in a random access memory (RAM) through bus architecture, and simultaneously outputting, by the host interface controller, the user data of the pages to an engine through an interface, thereby enabling the engine to calculate parities of a page group according to the user data of the pages.

Description

Device and method for writing data of page group to flash memory module

The invention relates to a storage device, in particular to a device and method for writing data of a page group to a flash memory module.

Flash memory is generally divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address to access the NOR flash memory on the address pin, and obtain the data stored at that address from the data pin of the NOR flash memory in time data. On the contrary, NAND flash memory is not random access, but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processing unit needs to write the value of the sequence of bytes (Bytes) into the NAND flash memory to define the type of request command (Command) (such as , Read, write, erase, etc.), and the address used in this command. The address can point to a page (the smallest data block for a write operation in the flash memory) or a block (the smallest data block for an erase operation in the flash memory).

Flash memory controllers usually use Error Correcting Code (ECC) to repair errors that occur when user data passes through the channel or is stored. When data is written, the flash memory controller encodes user data to generate redundant information of error correction codes. This redundant information allows the flash memory controller to correct a limited number of error bits that occur anywhere in the user data when reading data, without the need for rereading. In order to prevent the user data from reading the page from containing more than the error correction code can correct the error bits and the major error occurs, the flash memory controller can make a preset number of pages form a page group, and according to The user data of the page group generates the parity check code of the page group. However, because the calculation of the parity check code of the page group is a cross-page resource Material calculation operations require a lot of time and computing resources. Therefore, the present invention provides an apparatus and method for writing data of a page group to a flash memory module, which is used to reduce the time and computing resources required for generating the parity check code of the page group.

In view of this, how to reduce or eliminate the deficiencies in the above-mentioned related fields is indeed a problem to be solved.

This specification relates to a method for writing data of a page group to a flash memory module, which is executed by the flash memory controller, and includes: the host interface controller obtains user data of the page group from the host, wherein the page group includes multiple Page; the host interface controller stores the user data of the page to the random access memory through the bus architecture, and outputs the user data of the page to the engine through the interface, so that the engine calculates the parity of the page group based on the user data of the page Code verification; the direct memory access controller obtains the parity check code of the page group from the engine, and stores the parity check code of the page group to the random access memory through the bus architecture; and the flash memory interface controller uses the bus The row structure obtains the user data of the page and the parity check code of the page group from the random access memory, and writes the user data of the page and the parity check code of the page group to the flash memory module.

This specification also relates to a device for writing data of a page group to a flash memory module, which includes: a bus architecture; an engine; and a host interface controller. The host interface controller includes a first interface coupled to the bus structure; a second interface coupled to the host terminal; a third interface coupled to the engine; and a controller. The controller drives the second interface to obtain the user data of the page group from the host. The page group contains multiple pages; drives the first interface to store the user data of the page to the random access memory through the bus architecture, and drives at the same time The third interface outputs the user data of the page to the engine, so that the engine calculates the parity check code of the page group based on the user data of the page.

One of the advantages of the above embodiment is that by using the host interface controller to directly output the user data of the page to the engine to calculate the parity code, it can save the engine from reading from the random access memory through the bus architecture. The time when the user data of the page was fetched.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

10: Electronic device

110: host side

130: flash memory controller

131: Host Interface Controller

132: bus architecture

134: Processing Unit

135: Direct Memory Access Controller

136: Random Access Memory

137: Redundant Array of Independent Disks Error Correction Code Engine

139: flash memory interface controller

150: Flash memory module

530: flash memory controller

531: Host Interface Controller

535: Direct Memory Access Controller

537: Redundant Array of Independent Disks Error Correction Code Engine

610,650,673,677: interface

Figure 1 shows the logical data organization diagram of the page, the parity check code page and its error correction code.

FIG. 2 is a system architecture diagram of an electronic device according to some embodiments.

FIG. 3 is a schematic diagram of the generation and writing of user data and parity check codes of the page group based on the system architecture of FIG. 2.

Fig. 4 is an operation sequence diagram based on the execution steps shown in Fig. 3.

FIG. 5 is a system architecture diagram of an electronic device according to an embodiment of the invention.

FIG. 6 is a schematic diagram of interface connections of components in a flash memory controller according to an embodiment of the present invention.

FIG. 7 is a timing diagram of transmitting multiple pages of user data from a host interface controller to a redundant array of independent disks error correction code engine according to an embodiment of the present invention.

FIG. 8 is a timing diagram of transmitting the parity check code of the page group from the redundant array of independent disks error correction code engine to the direct memory controller according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of the generation and writing of user data and parity check codes of the page group based on the system architecture of FIG. 5.

The following descriptions are preferred implementations for completing the invention, and their purpose is to describe the basic spirit of the invention, but not to limit the invention. The actual content of the invention must refer to the scope of the claims that follow.

It must be understood that the words "including" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, elements, and/or components, but they do not exclude the possibility of adding More technical features, values, method steps, job processing, components, components, or any combination of the above.

Words such as "first", "second", and "third" in the claims are used to modify the elements in the claims, not to indicate that there is a priority, prerequisite relationship, or an element Prior to another element, or the chronological order of execution of method steps, is only used to distinguish elements with the same name.

It must be understood that when an element is described as being “connected” or “coupled” to another element, it can be directly connected or coupled to other elements, and intervening elements may appear. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other terms used to describe the relationship between elements can also be interpreted in a similar manner, such as "between" versus "directly between", or "adjacent" versus "directly adjacent" and so on.

In order to achieve data fault tolerance, the flash memory controller can generate an Error Correcting Code (ECC) based on the user data of each page, and write the user data together with the error correction code into the flash memory module so that it can be corrected in the future User data with error bits read from the flash memory module. The error correction code can be a Low-Density Parity Check Code (LDPC), BCH code (Bose-Chaudhuri-Hocquenghem Code) or other types of codes. Taking user data per 1K byte as an example, the BCH code can provide correction capability of up to 72 error bits, while LDPC can provide correction capability of up to 128 error bits. However, the user data of the read page may contain more error bits than the error correction code can correct. Therefore, the flash memory controller allows a preset number of pages to form a page group, and generates a parity page according to the user data of the page group. Referring to the example data organization shown in FIG. 1, seven pages P#0 to P#6 form a page group, each page contains 4096 bits of user data, and the corresponding ECC is generated accordingly. For example, the error correction code of the 0th page P#0 is ECC#0, the error correction code of the 1st page P#1 is ECC#1, and so on. It should be noted here that the example shown in Figure 1 is a logical point of view, and does not mean that the user data and its error correction code of a page group, the parity code page and its error correction code are actually stored in the same In the physical block. In order to optimize system performance, the user data page and its error correction code, parity check code page and its error correction code of a page group may be stored in parallel in different channels with multiple logical unit numbers (Logical Number Unit, LUN), the present invention is not limited thereby. The data of the parity check code page can be generated using formula (1): P _j = d _p0,j ⊕d _p1,j ⊕d _p2,j ⊕d _p3,j ⊕d _p4,j ⊕d _p5,j ⊕d _{p6 ,j} , where j is any integer from 0 to 4095, p0 represents page 0, p1 represents page 1, p2 represents page 2, P _j represents the value of the j-th bit in the parity code page, d _p0,j represents the value of the jth bit in the 0th page, d _p1,j represents the value of the jth bit in the first page, and d _p2,j represents the value of the jth bit in the second page . When the error bits in a page cannot be corrected by the corresponding error correction code, the flash memory controller can discard the page and use the exclusive OR operation based on the content of the other pages in the page group and the parity check code page. Generate the repaired user data for this page. Assuming that the error bit in the first page cannot be corrected with the corresponding error correction code, the formula (2) can be used to reply to the error page: d _p1,j = d _p0,j ⊕d _p2,j ⊕d _p3,j ⊕ d _p4,j ⊕d _p5,j ⊕d _p6,j ⊕P _j . The parity check code of the page group can also be called the Redundant Array of Independent Disks (RAID ECC) according to its function.

In order to complete the two-dimensional protection described above, FIG. 2 shows the system architecture of some embodiments. The electronic device 10 includes a host side 110, a flash memory controller 130, and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as a device side. The electronic device 10 can be implemented in electronic products such as a personal computer, a laptop PC, a tablet computer, a mobile phone, a digital camera, and a digital video camera. The host interface controller (Host Interface Controller) 131 of the host side 110 and the flash memory controller 130 can be attached to a universal serial bus (USB), advanced technology attachment (ATA), and serial advanced technology attachment (serial advanced). technology attachment, SATA), fast peripheral component interconnect express (PCI-E), universal flash storage (Universal Flash Storage, UFS), fast non-volatile memory (Non-Volatile Memory Express, NVMe), embedded Communication protocols such as Embedded Multi-Media Card (eMMC) communicate with each other. The flash memory interface controller (Flash Interface Controller) 139 and the flash memory module 150 of the flash memory controller 130 can communicate with each other through the Double Data Rate (DDR) communication protocol. This communication, for example, open NAND flash (Open NAND Flash Interface, ONFI), double data rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (for example, a single processor, a multi-processor with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and When executing software and/or firmware commands, it provides the functions described later. The processing unit 134 receives host commands, such as Read Command, Write Command, Erase Command, etc., through the host interface controller 131, schedules and executes these commands. The flash memory controller 130 further includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM) or a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, used to configure the space as a data buffer to store user data (also called host data) and parity code read from the host 110 and to be written into the flash memory module 150 It stores the user data read from the flash memory module 150 and will be output to the host 110, and stores the ECC and parity check codes read from the flash memory module 150 for data restoration. The random access memory 136 can also store data needed during execution, such as variables, data tables, Host-to-Flash (Host-to-Flash, H2F Table), and Flash-to-Host comparison table (Flash-to-Host). , F2H Table) and so on. The flash memory interface controller 139 includes a NAND Flash Controller (NFC), and provides functions required when accessing the flash memory module 150, such as a command sequencer (Command Sequencer), an ECC encoder, an ECC decoder, and the like. The ECC encoder is used to generate the corresponding ECC based on the content of a user data page or RAID ECC page.

The flash memory controller 130 can be configured with a bus architecture 132 for coupling between components to transfer data, addresses, control signals, etc. These components include a host interface controller 131, a processing unit 134, and RAM 136. Direct Memory Access (DMA) controller 135, flash memory interface controller 139 Wait. In some embodiments, the host interface controller 131, the processing unit 134, the RAM 136, the DMA controller 135, and the flash memory interface controller 139 may be coupled to each other through a single bus. In other embodiments, a high-speed bus may be configured in the flash memory controller 130 for coupling the processing unit 134, the DMA controller 135, and the RAM 136 to each other, and a low-speed bus may be configured for the processing unit 134, DMA The controller 135, the host interface controller 131, and the flash memory interface controller 139 are coupled to each other. The bus bar includes parallel physical lines to connect more than two components in the flash memory controller 130. The bus is a shared transmission medium. At any time, only two devices can use these lines to communicate with each other for data transmission. Data and control signals can propagate in both directions along the data and control lines between components, but on the other hand, address signals can only propagate in one direction along the address line. For example, when the processing unit 134 wants to read data at a specific address of the RAM 136, the processing unit 134 transmits the address to the RAM 136 on the address line. Then, the data at this address will reply to the processing unit 134 on the data line. In order to complete the data reading operation, the control signal will be transmitted using the control line.

The flash memory controller 130 may include a RAID ECC engine 137, including mutual exclusion or gates and registers, for completing the above-mentioned formula (1), formula (2) or similar operations. The DMA controller 135 may include an instruction queue (Instruction Queue). The processing unit 134 can issue data access commands to the DMA controller 135 through the bus architecture 132, and the DMA controller 135 stores these commands in the command queue according to the arrival time. Each data access command can include source component, source address, destination component, destination address and other information. The DMA controller 135 transfers specified data between components through the bus architecture 132 according to the data access command, for example, reads the data of a specific address and length in the RAM 136 and inputs it to the RAID ECC engine 137 to generate the RAID ECC engine 137 The parity check code is stored in a specific address in RAM 136, etc.

The flash memory module 150 provides a large amount of storage space, usually hundreds of gigabytes (GB), or even several terabytes (Terabytes, TB) for storing large amounts of user data. For example, high-resolution pictures, videos, etc. Flash memory module Group 150 includes a control circuit and a memory array. The memory cells in the memory array can include single level cells (SLCs), multiple level cells (MLCs), and triple level cells. Cells, TLCs), Quad-Level Cells (QLCs) or any combination of the above. The processing unit 134 writes user data to the designated address (destination address) in the flash memory module 150 through the flash memory interface controller 139, and reads the user from the designated address (source address) in the flash memory module 150 data. The flash memory interface controller 139 uses several electronic signals to coordinate the data and command transfer between the flash memory controller 130 and the flash memory module 150, including data lines, clock signals, and control signals. . The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transfer Chip Enable (CE), Address Latch Enable (ALE), and command extraction to enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

However, the architecture of the embodiment shown above requires the DMA controller 135 to wait for the host interface controller 131 to store a page of user data to the specified address of the RAM 136 before it can read it from the specified address of the RAM 136. The user information on the page is input to the RAID ECC engine 137. In detail, refer to the steps shown in FIG. 3.

Step (1): The host interface controller 131 obtains a page of user data from the host terminal 110, and stores the user data of this page to a designated address in the RAM 136.

Step (2): The DMA controller 135 reads a page of user data from the designated address in the RAM 136 and inputs it to the RAID ECC engine 137. Steps (1) and (2) will be continuously cyclically executed in the flash memory controller 130 until the user data of a page group is input to the RAID ECC engine 137 for calculation.

Step (3): The DMA controller 135 obtains the parity check code of the page group from the RAID ECC engine 137 and stores it in the designated address of the RAM 136.

Step (4): The flash memory interface controller 139 reads these from the designated address in the RAM 136 The user data of the page and the parity check code of the page group are written into the flash memory module 150.

The execution of step (1) and step (2) needs to wait for each other, which lengthens the time for data writing. Referring to FIG. 4, for example, the operation P#1(W) of the host interface controller 131 to write the user data of the first page to the RAM 136 requires the user to wait for the DMA controller 135 to read the 0th page from the RAM 136 The data read operation P#0(R), the DMA controller 135 reads the user data of the first page from the RAM 136. The read operation P#1(R) needs to wait for the host interface controller 131 to write the first page Operation P#1(W) of RAM 136 from the user data to RAM 136, and so on. In addition, since the host interface controller 131 and the DMA controller 135 need to compete for the control rights of the bus architecture 132, there may be due to other components (for example, the processing unit 134, the flash memory interface controller 139) between step (1) and step (2). Etc.) occupy the resources of the bus architecture 132 and further lengthen its lead time (time interval ts as shown in FIG. 4).

In order to solve the problems of the above-mentioned embodiments, the embodiment of the present invention proposes a new flash memory controller, which modifies the interface settings among the host interface controller 131, the DMA controller 135, and the RAID ECC engine 137 to avoid passing through the DMA controller. 135 occupies the resources of the bus architecture 132 to read the user data of the page group from the RAM 136 and input it to the RAID ECC engine 137. Referring to the electronic device 50 shown in FIG. 5, the host interface controller 531 and the RAID ECC engine 537 add interfaces to each other to allow the host interface controller 531 to obtain a page of user data from the host terminal 110 and then use the bus The framework 132 stores the user data of this page to a designated address in the RAM 136, and at the same time transmits the user data of this page to the RAID ECC engine 537 through the newly configured interface. After the host interface controller 531 sends the user data of a page group to the RAID ECC engine 537, it sends a control signal to the DMA controller 535 so that the DMA controller 535 obtains the parity of the page group from the RAID ECC engine 537 The code is stored in the designated address of the RAM 136 through the bus structure 132.

Refer to Figure 6 for the interface connection diagram. RAID ECC engine 537 setting interface 673, connection The interface 610 in the host interface controller 531 is used to directly obtain the user data of each page in the page group from the host interface controller 531 to encode the parity check code of the page group without any DMA control The device is obtained from RAM 136. Before starting the data transmission, the host interface controller 531 may enter the initialization phase, and inform the RAID ECC engine 537 of how many pages each page group contains, the operation mode, and other information through the interface 610. With reference to the timing diagram in Figure 7, in detail, for the total number of pages set in a page group, the RAID ECC engine 537 can enable the Set RAID Ready Signal (Set RAID Ready Signal, set_raid_rdy) to take effect (assert) for a period of t71 and notify the host The interface controller 531 can set the total number of pages during this period. During the period t71, the host interface controller 531 can place the total number of pages on the group size data lines (Group Size Data Lines, grp_size[2:0]) and generate one on the set pulse signal (Set Pulse Signal, set_raid_pls) The square wave is used to allow the RAID ECC engine 537 to extract the total number of pages of the page group on the group capacity data line and store the total number of pages in the register therein. For the operation mode setting, the RAID ECC engine 537 can enable the Set Mode Ready Signal (set_mode_rdy) to take effect for a period of t73, and notify the host interface controller 531 that the operation mode can be set during this period. During the period t73, the host interface controller 531 can place the operation mode (for example, encoding mode mode=0) on the operation mode data lines (Operation Mode Data Lines, op_mode[1:0]) and set the pulse signal (Set A square wave is generated on the Mode Pulse Signal (set_mode_pls), which is used for the RAID ECC engine 537 to extract the indicated operation mode from the operation mode data line on the rise of the square wave and store it in the register therein.

After completing the initialization phase, the RAID ECC engine 537 can enable the Encode Ready Signal (enc_rdy) to take effect until the user data of a page group is received (for example, during t75), which is used to notify the host interface controller 531 that it can Send user data during the effective period. The host interface controller 531 can enable the Encode Enabling Signal (enc_en) to take effect until the user data of the last page is transmitted (for example, during t77). During t77, the host interface controls The device 531 can be used with a clock signal (Clock Signal, not shown in FIG. 7) to place the user data of each page on the Encode Data Lines (enc_dat[63:0]) for the RAID ECC engine 537 to extract. The RAID ECC engine 537 can use the formula (1) to calculate the extracted user data to generate the parity check code of the page group. The host interface controller 531 may include a transmission counter, which is initially 0 and increments by 1 after the user data of a page is transmitted. When the value of the transfer counter is equal to the total number of pages in the page group, the host interface controller 531 can let the termination confirmation signal (Termination Valid Signal, term_valid) take effect for a period of time, and notify the DMA controller 535 that it can start to obtain the page group from the RAID ECC engine 537 The parity check code of the group is stored in the designated address of the RAM 136 through the bus architecture 132.

In the initialization phase, the controller (not shown in FIG. 5 and FIG. 6) in the RAID ECC engine 537 can drive the interface 673 to allow the setting engine ready signal to take effect for a period of time, and to allow the setting mode ready signal to take effect for a period of time. The controller in the host interface controller 531 (not shown in Figures 5 and 6) can drive the interface 610 to detect and set the engine ready signal, place the total number of pages on the group capacity data line, and generate a pulse signal on the set engine Square wave, detect the setting mode ready signal, put the operation mode on the operation mode data line, and generate a square wave on the setting mode pulse signal.

During the data transmission phase, the controller (not shown in FIGS. 5 and 6) in the RAID ECC engine 537 can drive the interface 673 to enable the encoding ready signal for a period of time. The controller (not shown in FIGS. 5 and 6) in the host interface controller 531 can drive the interface 610 to enable the encoding enable signal for a period of time, put the user data of each page on the encoding data line, and let the end Confirm that the signal takes effect for a period of time.

It should be noted here that the host interface controller 531 can also be provided with a first interface (not shown in FIGS. 5 and 6) connected to the host terminal 110 and a second interface (not shown in the figure) connected to the bus structure 132. 5 and Figure 6). The controller in the host interface controller 531 (not shown in FIGS. 5 and 6) can drive the first interface to obtain user data of each page from the host 110 using the communication protocol, and drive the second interface to use advanced can The Advanced eXtensible Interface (AXI) communication protocol is used to obtain the control right of the bus architecture 132, and the user data of each page is stored to the designated address in the RAM 136 through the bus architecture 132. The circuit structures and functions of the controller, the first interface and the second interface in the host interface controller 531 are well-known techniques of those skilled in the art, and will not be repeated for the sake of brevity.

Refer to Figure 6 for the interface connection diagram. The RAID ECC engine 537 is provided with an interface 677, which is connected to the interface 650 in the DMA controller 535, and is used to output the parity check code of the page group to the DMA controller 535. With reference to the timing diagram of Figure 8, in detail, when the DMA controller 535 receives the end confirmation signal, the DMA controller 535 can make the end output valid signal (Termination Out Valid, term_out_valid) take effect until the end of the page group is received. The parity check code (for example, period t81) is used to notify the RAID ECC engine 537 that the parity check code of the page group can be transmitted during the effective period. The RAID ECC engine 537 can enable the Termination Out Enabling Signal (term_out_en) to take effect until the parity check code of the page group is transmitted (for example, the period t83). During the period t83, the RAID ECC engine 537 can be used with a clock signal (Clock Signal, not shown in Figure 8) to place the parity check code of the page group on the Termination Out Parity Data Lines (Termination Out Parity Data Lines, term_out_pty[ 63:0]), let the DMA controller 535 extract.

During the transmission phase of the parity check code, the controller (not shown in FIGS. 5 and 6) in the DMA controller 535 can drive the interface 650 to detect the end confirmation signal and make the end output valid signal valid for a period of time. The controller in the RAID ECC engine 537 (not shown in Figures 5 and 6) can drive the interface 677 to enable the end output enable signal to take effect for a period of time, and place the parity check code of the page group in the end output parity code Data line.

It should be noted here that the DMA controller 535 can also be provided with an interface connected to the bus structure 132 (not shown in FIGS. 5 and 6). The controller in the DMA controller 535 (not shown in Figures 5 and 6) can drive this interface to use the advanced and expandable interface protocol to obtain control of the bus architecture 132, and store the page group through the bus architecture 132 of Parity check code to the designated address in RAM 136. The circuit structure and functions of the controller and the interface in the DMA controller 535 are well-known techniques of those skilled in the art, and will not be repeated for the sake of simplicity.

According to the architecture of the embodiment of the present invention, in detail, refer to the steps shown in FIG. 9.

Step (5): The host interface controller 531 obtains the user data of a page from the host 110, and stores the user data of this page to the specified address in the RAM 136 through the bus framework 132, and outputs the data through the interface 610 The user data of the page is encoded in the RAID ECC engine 537. Step (5) is continuously executed in the flash controller 530 in a loop until the user data of a page group is input to the RAID ECC engine 537 for calculation.

Step (6): The host interface controller 531 sends an end confirmation signal to the DMA controller 535 via the interface 610, informing the DMA controller 535 that it can start acquiring the parity code of the page group from the RAID ECC engine 537.

Step (7): The DMA controller 535 obtains the parity check code of the page group from the RAID ECC engine 537 through the interface 650, and stores it to the designated address of the RAM 136 through the bus architecture 132.

Step (8): The flash memory interface controller 139 reads the user data of these pages and the parity check codes of the page groups from the designated address in the RAM 136, and writes them into the flash memory module 150. The flash memory interface controller 139 can further generate an error correction code according to the user data of each page, generate an error correction code according to the parity check code of the page group, and combine the error correction code of each page and the error correction code of the parity check code. The wrong code is written into the flash memory module 150.

Compared with the timing diagram shown in FIG. 4 corresponding to the previous embodiment, the application of the new architecture of the embodiment of the present invention can save the previously designed DMA controller 135 from reading multiple pages of RAM 136. P#0(R ) To P#6(R), in addition, it can also avoid collisions between other components and the DMA controller 135 due to competing for control of the bus architecture 132, and avoid other components waiting for these read operations P#0(R) The lead time required to complete P#6(R).

Although the above-described elements are included in Figures 5 to 6 and 9, it is not ruled out that they do not violate the invention. Under the spirit of using more other additional components, a better technical effect has been achieved. In addition, although the steps in FIG. 9 are executed in a specified order, those skilled in the art can modify the order of these steps on the premise of achieving the same effect without violating the spirit of the invention. Therefore, the present invention does not It is limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of applied claims must be interpreted in the broadest way to include all obvious modifications and similar settings.

50: electronic device

110: host side

132: bus architecture

134: Processing Unit

136: Random Access Memory

139: flash memory interface controller

150: Flash memory module

531: Host Interface Controller

535: Direct Memory Access Controller

537: Redundant Array of Independent Disks Error Correction Code Engine

Claims (10)

A method for writing data of a page group to a flash memory module, executed by a flash memory controller, includes: a host interface controller obtains a user data of a page group from a host side, wherein the page group Contains multiple pages; the host interface controller stores the user data of the page group to a random access memory through a bus architecture, and outputs the user data of the page group to an engine through an interface, Wherein, the engine calculates a parity check code of the page group according to the user data of the page group; a direct memory access controller obtains the parity check code of the page group from the engine, and Store the parity check code of the page group in the random access memory through the bus architecture; and a flash memory interface controller acquires the use of the page group from the random access memory through the bus architecture The user data and the parity check code of the page group, and the user data of the page group and the parity check code of the page group are written to a flash memory module. The method for writing data of a page group to a flash memory module according to claim 1, wherein the host interface controller does not output the user data of the page group to the engine through the bus architecture. The method for writing data of a page group to a flash memory module as described in claim 1, comprising: the host interface controller outputs the user data of the page group to the engine through the interface, and then through another The interface sends an end confirmation signal to the direct memory access controller to notify the direct memory access controller to start acquiring the parity check code of the page group from the engine. The method for writing data of a page group to a flash memory module as described in claim 1, comprising: the flash memory interface controller generates a first error correction code according to the user data of each of the pages, and according to the page group The group of the parity check codes generates a second error correction code, and the first error correction code and the second error correction code are written to the flash memory module. A device for writing data of a page group to a flash memory module includes: a bus architecture; an engine; and a host interface controller, including: a first interface coupled to the above bus architecture; and a second interface , Coupled to a host; a third interface, coupled to the engine; and a first controller, wherein the first controller drives the second interface to obtain a user data of a page group from the host The page group includes a plurality of pages; the first interface is driven to store the user data of the page group to a random access memory through the bus architecture, and the third interface is driven to output the data of the page group The user data is sent to the engine, wherein the engine calculates a parity check code of the page group according to the user data of the page group. The device for writing data of a page group to a flash memory module as described in claim 5 includes: a direct memory access controller, including: a fourth interface coupled to the above-mentioned bus structure; and a fifth interface , Coupled to the engine and the host interface controller; and A second controller, wherein the second controller drives the fifth interface to obtain the parity code of the page group from the engine, and drives the fourth interface to store the parity of the page group through the bus architecture The parity check code is stored in the random access memory. The device for writing the data of the page group to the flash memory module as described in claim 6, wherein the first controller outputs the user data of the page group to the engine through the third interface, An end confirmation signal is sent to the direct memory access controller through the third interface for informing the direct memory access controller to start acquiring the parity check code of the page group from the engine. The device for writing data of a page group to a flash memory module according to claim 6, comprising: a flash memory interface controller, coupled to the above-mentioned bus architecture, and obtaining the above-mentioned random access memory from the above-mentioned random access memory through the above-mentioned bus architecture The user data of the page group and the parity code of the page group, and the user data of the page group and the parity code of the page group are written to a flash memory module. The device for writing data of a page group to a flash memory module according to claim 8, wherein the flash memory interface controller generates a first error correction code according to the user data of each of the pages, and according to the page group The group of the parity check codes generates a second error correction code, and the first error correction code and the second error correction code are written to the flash memory module. The device for writing data of a page group to a flash memory module according to any one of claim items 5 to 9, wherein the engine does not obtain the user data of the page group through the bus architecture.

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