CN112988449B

CN112988449B - Device and method for writing page group data into flash memory module

Info

Publication number: CN112988449B
Application number: CN202010267832.5A
Authority: CN
Inventors: 李安邦
Original assignee: Silicon Motion Inc
Current assignee: Silicon Motion Inc
Priority date: 2019-12-16
Filing date: 2020-04-08
Publication date: 2023-08-15
Anticipated expiration: 2040-04-08
Also published as: TW202125511A; TWI719880B; CN112988449A

Abstract

The application relates to a method and a device for writing page group data into a flash memory module, wherein the method for writing page group data into the flash memory module comprises the following steps: the host interface controller stores user data of a plurality of pages to the random access memory through the bus architecture, and simultaneously outputs the user data of the pages to the engine through the interface, so that the engine calculates parity codes of page groups according to the user data of the pages, the direct memory access controller acquires the parity codes of the page groups from the engine, and stores the parity codes of the page groups to the random access memory through the bus architecture, and the flash interface controller acquires the user data of the pages and the parity codes of the page groups from the random access memory through the bus architecture, and writes the user data of the pages and the parity codes of the page groups to the flash memory module. Thus, the time and operation resources required for generating the parity code of the page group are reduced.

Description

Device and method for writing page group data into flash memory module

Technical Field

The present application relates to a memory device, and more particularly, to a device and method for writing page group data into a flash memory module.

Background

Flash memory is generally classified into NOR flash memory and NAND flash memory. The NOR flash memory is a random access device, and a central processing unit (Host) can provide any address accessing the NOR flash memory on an address pin, and timely obtain data stored on the address from a data pin of the NOR flash memory. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory, like NOR flash memory, cannot access any random addresses, but instead the cpu needs to write serial byte values into the NAND flash memory for defining the type of Command (Command) (e.g., read, write, erase, etc.), and the address used on the Command. The address may point to one page (the smallest block of data for a write operation in flash) or one block (the smallest block of data for an erase operation in flash).

Flash controllers typically use error correction codes (Error Correcting Code, ECC) to repair errors that occur when user data passes through a channel or stores. At the time of data writing, the flash memory controller encodes user data to generate redundant information of the error correction code. These redundant information allow the flash memory controller to correct a limited number of erroneous bits occurring anywhere in the user data during data reading without re-reading. To prevent significant errors from occurring in the user data of the read Page beyond the error bits that the error correction code is able to correct back, the flash memory controller may cause a default number of pages to form a Page Group (Page Group) and generate a parity for the Page Group based on the user data of the Page Group. However, since the calculation of the parity of the page group is a data calculation operation across pages, a large amount of time and operation resources are required. Therefore, the present application provides an apparatus and method for writing data of a page group to a flash memory module, which is used for reducing the time and operation resources required for generating parity codes of the page group.

Disclosure of Invention

In view of this, how to alleviate or eliminate the above-mentioned drawbacks of the related art is a real problem to be solved.

The application relates to a method for writing data of page groups into a flash memory module, which is executed by a flash memory controller and comprises the following steps: the host interface controller obtains user data of a page group from a host end, wherein the page group comprises a plurality of pages; the host interface controller stores the user data of the page into the random access memory through the bus architecture, and simultaneously outputs the user data of the page to the engine through the interface, so that the engine calculates the parity check code of the page group according to the user data of the page; the direct memory access controller acquires the parity codes of the page group from the engine and stores the parity codes of the page group into the random access memory through the bus architecture; and the flash memory interface controller acquires the user data of the page and the parity code of the page group from the random access memory through the bus architecture, and writes the user data of the page and the parity code of the page group into the flash memory module.

The application also relates to a device for writing data of a page group to a flash memory module, comprising: a bus architecture; an engine; and a host interface controller. The host interface controller comprises a first interface coupled with the bus architecture; the second interface is coupled with the host end; a third interface coupled to the engine; and a controller. The controller drives the second interface to acquire user data of a page group from the host end, wherein the page group comprises a plurality of pages; the first interface is driven to store the user data of the page to the random access memory through the bus architecture, and the third interface is driven to output the user data of the page to the engine, so that the engine calculates the parity check code of the page group according to the user data of the page.

One of the advantages of the above embodiment is that by using the host interface controller to directly output the user data of the page to the engine for parity calculation as described above, the time for the engine to read the user data of the page from the random access memory through the bus architecture can be saved.

Other advantages of the present application will be explained in more detail in connection with the following description and accompanying drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application.

FIG. 1 shows a logical data organization schematic of a page, a parity page, and an error correction code therefor.

Fig. 2 is a system architecture diagram of an electronic device of some embodiments.

FIG. 3 is a schematic diagram of the generation and writing of user data and parity codes thereof based on a page group under the system architecture of FIG. 2.

Fig. 4 is a sequence diagram of operations based on the execution steps shown in fig. 3.

Fig. 5 is a system architecture diagram of an electronic device according to an embodiment of the application.

FIG. 6 is a schematic diagram illustrating the interfacing of components in a flash memory controller according to an embodiment of the present application.

FIG. 7 is a timing diagram of transmitting user data for multiple pages from a host interface controller to a RAID error correction code engine in accordance with an embodiment of the present application.

FIG. 8 is a timing diagram of transmitting parity for a page group from a RAID error correction code engine to a direct memory controller in accordance with an embodiment of the present application.

FIG. 9 is a schematic diagram of the generation and writing of user data and parity codes thereof based on a page group under the system architecture of FIG. 5.

Wherein the symbols in the drawings are briefly described as follows:

10. 50: an electronic device; 110: a host end; 130: a flash memory controller; 131: a host interface controller; 132: a bus architecture; 134: a processing unit; 135: a direct memory access controller; 136: a random access memory; 137: an independent disk redundancy array error correction code engine; 139: a flash memory interface controller; 150: a flash memory module; 530: a flash memory controller; 531: a host interface controller; 535: a direct memory access controller; 537: an independent disk redundancy array error correction code engine; 610. 650, 673, 677: an interface.

Detailed Description

Embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like reference numerals designate identical or similar components or process flows.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, values, method steps, operation processes, components, and/or groups, but do not preclude the addition of further features, values, method steps, operation processes, components, groups, or groups of the above.

In the present application, terms such as "first," "second," "third," and the like are used for modifying elements of the claims, and are not intended to denote a prior order, a first order, or a sequence of steps of a method, for example, for distinguishing between elements having the same name.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between components may also be interpreted in a similar fashion, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

To achieve data fault tolerance, the flash memory controller may generate error correction codes (Error Correcting Code, ECC) from the user data of each page and write the user data to the flash memory module along with the error correction codes so that the user data containing the error bits read from the flash memory module can be corrected in the future. The error correction Code may be a Low-density parity-check Code (Low-Density Parity Check Code, LDPC), a BCH Code (Bose-Chaudhuri-Hocquenghem Code), or other kind of Code. Taking user data of every 1 kbyte as an example, BCH codes can provide correction capability of up to 72 error bits, while LDPC can provide correction capability of up to 128 error bits. However, the user data of the read page may contain more error bits than the error correction code can correct back. Therefore, the flash memory controller can make a default number of pages form a Page Group (Page Group), and generate Parity pages (Parity pages) according to user data of the Page Group. Referring to the data organization of the example shown in FIG. 1, seven pages P#0 to P#6 form a page group, each page containing 4096 bits of user data, and corresponding ECCs are generated therefrom. For example, the error correction code for page 0 p#0 is ecc#0, the error correction code for page 1 p#1 is ecc#1, and so on. It should be noted here that the example shown in fig. 1 is a logical view, and does not represent user data of a page group and its error correction code, parity page and its error correction code actually stored in the same physical block. To optimize system performance, a page group of user data and its error correction code, a page of parity code and its error correction code may be stored in parallel in physical blocks of multiple logical unit numbers (Logical Number Unit, LUN) in different channels, and the application is not so limited. The data for the parity page may be generated using equation (1):

P _j ＝d _p0,j ⊕d _p1,j ⊕d _p2,j ⊕d _p3,j ⊕d _p4,j ⊕d _p5,j ⊕d _p6,j ，

where j is any integer from 0 to 4095, p0 represents page 0, p1 represents page 1, p2 represents page 2, and so on; p (P) _j A value representing the j-th bit in the parity page; d, d _p0,j A value representing the j-th bit in page 0, d _p1,j A value representing the j-th bit in page 1, d _p2,j Representing the value of the j-th bit in page 2, and so on. When the error bit of a page cannot be corrected by using the corresponding error correction code of the page, the flash memory controller can discard the page and generate the user data of the repaired page by exclusive OR operation according to the contents of other pages and parity check code pages in the page group. Assuming that the error bits in page 1 cannot be corrected using the corresponding error correction code, the recovery of the error page can be performed using equation (2):

d _p1,j ＝d _p0,j ⊕d _p2,j ⊕d _p3,j ⊕d _p4,j ⊕d _p5,j ⊕d _p6,j ⊕P _j 。

the parity of a page group may also be referred to as a redundant array of independent disks error correction code (Redundant Array of Independent Disks, RAID ECC) depending on its role.

To accomplish the two-dimensional protection described above, FIG. 2 shows a system architecture of some embodiments. The electronic Device 10 includes a Host Side 110, a flash controller 130 and a flash module 150, and the flash controller 130 and the flash module 150 may be collectively referred to as a Device Side (Device Side). The electronic device 10 may be implemented in an electronic product such as a personal computer, a notebook computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera, and the like. The host 110 and the host interface controller (Host Interface Controller) 131 of the flash memory controller 130 may communicate with each other via a universal serial bus (Universal Serial Bus, USB), an advanced technology attachment (Advanced Technology Attachment, ATA), a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), a peripheral component interconnect express (Peripheral Component Interconnect Express, PCI-E), a universal flash memory storage (Universal Flash Storage, UFS), a Non-volatile memory (Non-Volatile Memory Express, NVMe), an Embedded multimedia Card (eMMC), and other communication protocols. The flash interface controller (Flash Interface Controller) 139 of the flash controller 130 and the flash module 150 may communicate with each other in a Double Data Rate (DDR) communication protocol, such as an open NAND flash (Open NAND Flash Interface, ONFI), double Data Rate switch (DDR Toggle), or other communication protocol. The flash controller 130 includes a processing unit 134 that may be implemented in a variety of ways, such as using general purpose hardware (e.g., a single processor, a multiprocessor with parallel processing capabilities, a graphics processor, or other processor with computing capabilities), and provides the functionality described below when executing software and/or firmware instructions. The processing unit 134 receives host commands, such as Read commands (Read commands), write commands (Write commands), erase commands (Erase commands), etc., via the host interface controller 131, and schedules and executes these commands. The flash controller 130 further includes a random access memory (Random Access Memory, RAM) 136, which may be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), or a combination thereof, for configuring space as a data buffer, storing user data (also referred to as host data) read from the host 110 and to be written to the flash memory module 150, parity codes, etc., storing user data read from the flash memory module 150 and to be output to the host 110, and storing ECC, parity codes, etc. read from the flash memory module 150 for data repair. The ram136 may further store data needed during execution, such as variables, data tables, host-to-Flash (H2F Table), flash-Host (F2H Table), and the like. Flash interface controller 139 includes a NAND flash controller (NAND Flash Controller, NFC) that provides the functions required when accessing flash module 150, such as command serializer (Command Sequencer), ECC encoder, ECC decoder, and the like. The ECC encoder is used for generating corresponding ECC according to the content of one user data page or RAID ECC page.

A Bus Architecture (Bus Architecture) 132 may be configured in the flash memory controller 130 for coupling components to each other for transferring data, addresses, control signals, etc., including a host interface controller 131, a processing unit 134, a RAM136, a direct memory access (Direct Memory Access, DMA) controller 135, a flash memory interface controller 139, etc. In some embodiments, host interface controller 131, processing unit 134, RAM136, DMA controller 135, and flash interface controller 139 may be coupled to each other by a single bus. In other embodiments, a high-speed bus may be configured in flash controller 130 for coupling processing unit 134, DMA controller 135, and RAM136 to each other, and a low-speed bus may be configured for coupling processing unit 134, DMA controller 135, host interface controller 131, and flash interface controller 139 to each other. The bus includes parallel physical lines that connect two or more components in the flash controller 130. A bus is a shared transmission medium that can only be used by two devices to communicate with each other at any given time for transferring data. Data and control signals can travel bi-directionally between the components along the data and control lines, respectively, but on the other hand address signals can travel uni-directionally along the address lines. For example, when processing unit 134 wants to read data at a particular address of RAM136, processing unit 134 transfers the address to RAM136 at an address line. The data of the address is then returned to the processing unit 134 on the data line. To complete the data read operation, control signals are passed using control lines.

Flash controller 130 may include a RAID ECC engine 137 including exclusive OR gates and registers for performing the operations described above for equation (1), equation (2), or the like. DMA controller 135 may include an instruction queue (Instruction Queue). The processing unit 134 may issue data access instructions to the DMA controller 135 via the bus architecture 132, and the DMA controller 135 stores the instructions in an instruction queue according to the arrival time. Each data access instruction may include information of a source component, a source address, a destination component, a destination address, and the like. The DMA controller 135 transfers specified data between components through the bus architecture 132 according to the data access command, for example, reads data of a specific address and length in the RAM136 and inputs the data into the RAID ECC engine 137, and stores the parity generated by the RAID ECC engine 137 to the specific address in the RAM 136.

Flash memory module 150 provides a large amount of memory, typically hundreds of Gigabytes (GB), and even multiple megabytes (TB), for storing large amounts of user data, such as high resolution pictures, movies, and the like. The flash memory module 150 includes a control circuit and a memory array, and the memory Cells in the memory array may include single-layer Cells (Single Level Cells, SLCs), multi-layer Cells (Multiple Level Cells, MLCs), triple-layer Cells (Triple Level Cells, TLCs), quad-layer Cells (QLCs), or any combination thereof. The processing unit 134 writes user data to a specified address (destination address) in the flash memory module 150 and reads user data from the specified address (source address) in the flash memory module 150 through the flash memory interface controller 139. The flash interface controller 139 coordinates Data and command transfer between the flash controller 130 and the flash module 150 using a plurality of electronic signals, including a Data Line (Data Line), a clock signal (clock signal) and a control signal (control signal). The data line can be used for transmitting commands, addresses, read-out and written data; the control signal lines may be used to transmit control signals such as Chip Enable (CE), address fetch Enable (Address Latch Enable, ALE), command fetch Enable (Command Latch Enable, CLE), write Enable (WE), and the like.

However, the architecture of the embodiment described above would have the DMA controller 135 to wait for the host interface controller 131 to store a page of user data to the specified address of RAM136 before being able to read the page of user data from the specified address of RAM136 and input to the RAID ECC engine 137. In detail, reference is made to the steps shown in fig. 3.

Step (1): the host interface controller 131 retrieves user data of one page from the host side 110 and stores the user data of this page to a specified address in the RAM 136.

Step (2): DMA controller 135 reads one page of user data from a specified address in RAM136 and inputs to RAID ECC engine 137. Steps (1) and (2) are continuously looped through the flash controller 130 until the user data of a page group is input to the RAID ECC engine 137 for operation.

Step (3): DMA controller 135 retrieves the parity for this page group from RAID ECC engine 137 and stores it to the specified address of RAM 136.

Step (4): flash interface controller 139 reads the user data for these pages and the parity for the page group from the specified address in RAM136 and writes to flash module 150.

The execution of the step (1) and the step (2) needs to wait for each other, thereby prolonging the time for writing data. Referring to fig. 4, for example, the operation p#1 (W) of the host interface controller 131 writing the user data of the 1 st page to the RAM136 needs to wait for the read operation p#0 (R) of the DMA controller 135 reading the user data of the 0 th page from the RAM136, the read operation p#1 (R) of the DMA controller 135 reading the user data of the 1 st page from the RAM136 needs to wait for the operation p#1 (W) of the host interface controller 131 writing the user data of the 1 st page to the RAM136, and so on. In addition, since the host interface controller 131 and the DMA controller 135 need to compete for control of the bus architecture 132, the lead time (time interval ts shown in fig. 4) may be further extended between the step (1) and the step (2) because other components (e.g., the processing unit 134, the flash interface controller 139, etc.) occupy the resources of the bus architecture 132.

To solve the problems of the above-described embodiments, the embodiment of the present application proposes a new flash memory controller, which modifies interface settings among the host interface controller 131, the DMA controller 135 and the RAID ECC engine 137, to avoid that user data of a page group is read from the RAM136 and input to the RAID ECC engine 137 by the DMA controller 135 occupying resources of the bus architecture 132. Referring to the electronic device 50 shown in fig. 5, the host interface controller 531 and the RAID ECC engine 537 add interfaces connected to each other, so that after the host interface controller 531 obtains user data of a page from the host 110, the user data of the page is stored in the specified address in the RAM136 through the bus architecture 132, and at the same time, the user data of the page is transferred to the RAID ECC engine 537 through the newly-configured interface. After transferring the user data of a page group to the RAID ECC engine 537, the host interface controller 531 sends a control signal to the DMA controller 535, so that the DMA controller 535 obtains the parity of the page group from the RAID ECC engine 537 and stores the parity to the specified address of the RAM136 through the bus architecture 132.

Refer to the interfacing schematic of fig. 6. The RAID ECC engine 537 sets up an interface 673, connected to the interface 610 in the host interface controller 531, for directly retrieving user data for each page in the page group from the host interface controller 531 for encoding of the parity of the page group, without retrieval from the RAM136 by any DMA controller. Before starting data transfer, the host interface controller 531 may enter an initialization phase, informing the RAID ECC engine 537 via the interface 610 of how many pages each page group contains, operating mode, etc. In detail, referring to the timing diagram of fig. 7, for setting the total number of pages for one page group, the RAID ECC engine 537 may enable (assent) the set engine ready signal (Set RAID Ready Signal, set_raid_rdy) for a period of time t71, informing the host interface controller 531 that the total number of pages may be set during this period of time. In period t71, the host interface controller 531 may place the total number of pages on the group capacity data lines (Group Size Data Lines, grp_size [2:0 ]) and generate a square wave on the Set Pulse Signal, set_raid_pls, for the RAID ECC engine 537 to fetch the total number of pages of the page group on the group capacity data lines at the rising edge of the square wave, and store the total number of pages in the register. For operation mode setting, the RAID ECC engine 537 may assert a set mode ready signal (Set Mode Ready Signal, set_mode_rdy) for a period of time t73, informing the host interface controller 531 that the operation mode may be set during this period. During period t73, the host interface controller 531 may place an operation mode (e.g., encoding mode mode=0) on the operation mode data line (Operation Mode Data Lines, op_mode [1:0 ]) and generate a square wave on the set mode pulse signal (Set Mode Pulse Signal, set_mode_pls) for the RAID ECC engine 537 to fetch the indicated operation mode on the operation mode data line at the rising edge of the square wave and store the same in the register.

After the initialization phase is completed, RAID ECC engine 537 may assert the encoding ready signal (Encode Ready Signal, enc_rdy) until user data for a page group is received (e.g., period t 75) to inform host interface controller 531 that user data may be transferred during the active period. The host interface controller 531 may assert the encode enable signal (Encode Enabling Signal, enc_en) until the user data for the last page has been transferred (e.g., during t 77). In period t77, the host interface controller 531 may place the user data of each page on the encoded data lines (Encode Data Lines, enc_dat [63:0 ]) in conjunction with a Clock Signal (not shown in FIG. 7) for the RAID ECC engine 537 to extract. The RAID ECC engine 537 may calculate the extracted user data using equation (1) to generate the parity for the page group. The host interface controller 531 may contain a transfer counter, initially 0, and increment 1 after transferring user data for one page. When the value of the transfer counter is equal to the total number of pages of the page group, the host interface controller 531 may assert an end acknowledge signal (Termination Valid Signal, term_valid) for a period of time, informing the DMA controller 535 that the acquisition of the parity of the page group from the RAID ECC engine 537 may begin and be stored to the specified address of the RAM136 via the bus architecture 132.

During the initialization phase, a controller (not shown in fig. 5 and 6) in the RAID ECC engine 537 may drive the interface 673 to assert the set engine ready signal for a period of time and to assert the set mode ready signal for a period of time. A controller (not shown in fig. 5 and 6) in the host interface controller 531 may drive the interface 610 to detect the set engine ready signal, place the total number of pages on the group capacity data line, generate a square wave on the set engine pulse signal, detect the mode ready signal, place the mode of operation on the mode of operation data line, and generate a square wave on the set engine pulse signal.

During the data transfer phase, a controller (not shown in fig. 5 and 6) in the RAID ECC engine 537 may drive the interface 673 to assert the code ready signal for a period of time. A controller (not shown in fig. 5 and 6) in host interface controller 531 may drive interface 610 to assert the encode enable signal for a period of time, place the user data for each page on the encode data line, and assert the end acknowledge signal for a period of time.

It should be noted that the host interface controller 531 may further provide a first interface (not shown in fig. 5 and 6) connected to the host 110 and a second interface (not shown in fig. 5 and 6) connected to the bus architecture 132. A controller (not shown in fig. 5 and 6) in the host interface controller 531 may drive the first interface to acquire user data of each page from the host side 110 using a communication protocol, and drive the second interface to acquire control of the bus architecture 132 using a further extensible interface (Advanced eXtensible Interface, AXI) communication protocol, and store the user data of each page to a designated address in the RAM136 through the bus architecture 132. The circuit structures and functions of the controller, the first interface and the second interface in the host interface controller 531 are well known to those skilled in the art, and are not described in detail for brevity.

Refer to the interfacing schematic of fig. 6. The RAID ECC engine 537 sets up an interface 677, coupled to interface 650 in the DMA controller 535, for outputting the parity of the page group to the DMA controller 535. In detail, with reference to the timing diagram of fig. 8, when the DMA controller 535 receives the end confirmation signal, the DMA controller 535 may assert the end output valid signal (Termination Out Valid, term_out_valid) until the parity of the page group is received (e.g., period t 81), so as to inform the RAID ECC engine 537 that the parity of the page group may be transferred during the valid period. The RAID ECC engine 537 may assert the end output enable signal (Termination Out Enabling Signal, term_out_en) until the parity for the page group is transferred (e.g., period t 83). In period t83, RAID ECC engine 537 may match a Clock Signal (not shown in FIG. 7) to place the parity of the page group on the end output parity data lines (Termination Out Parity Data Lines, term_out_ pty [63:0 ]) for DMA controller 535 to fetch.

During the parity transfer phase, a controller (not shown in fig. 5 and 6) in DMA controller 535 may drive interface 650 to detect the end acknowledge signal and assert the end output valid signal for a period of time. A controller (not shown in fig. 5 and 6) in the RAID ECC engine 537 may drive the interface 677 to assert the end output enable signal for a period of time and place the parity of the page group on the end output parity data line.

It should be noted here that the DMA controller 535 may further be provided with an interface (not shown in fig. 5 and 6) connected to the bus architecture 132. A controller (not shown in fig. 5 and 6) in DMA controller 535 may drive this interface to acquire control of bus architecture 132 using an advanced extensible interface communication protocol and store the parity of the page group through bus architecture 132 to a specified address in RAM 136. The circuit structure and function of the controller and interface in the DMA controller 535 are well known to those skilled in the art and will not be described in detail for the sake of brevity.

In detail, reference is made to the steps shown in fig. 9 according to an architecture of an embodiment of the present application.

Step (5): the host interface controller 531 obtains user data of a page from the host 110, stores the user data of the page to a specified address in the RAM136 through the bus architecture 132, and outputs the user data of the page to the RAID ECC engine 537 through the interface 610 for encoding. Step (5) is continuously performed in the flash controller 530 in a loop until the user data of a page group is input to the RAID ECC engine 537 for operation.

Step (6): the host interface controller 531 sends an end acknowledge signal to the DMA controller 535 over the interface 610 informing the DMA controller 535 that the acquisition of the parity of the page group from the RAID ECC engine 537 can begin.

Step (7): DMA controller 535 retrieves the parity for this page group from RAID ECC engine 537 via interface 650 and stores the specified address to RAM136 via bus architecture 132.

Step (8): flash interface controller 139 reads the user data for these pages and the parity for the page group from the specified address in RAM136 and writes to flash module 150. The flash interface controller 139 may also generate an error correction code based on the user data for each page, generate an error correction code based on the parity for the group of pages, and write the error correction code for each page and the error correction code for the parity to the flash module 150.

Compared to the timing diagram corresponding to the previous embodiment shown in fig. 4, the new architecture of the embodiment of the present application can save the read operations p#0 (R) to p#6 (R) of the DMA controller 135 from the multiple pages of the RAM136, and can avoid the collision between other components and the DMA controller 135 caused by competing for the control right of the bus architecture 132, and avoid the pre-time required by other components to wait for the completion of the read operations p#0 (R) to p#6 (R).

Although the components described above are included in fig. 5-6 and 9, it is not excluded that many more additional components may be used to achieve a better technical result without violating the spirit of the application. Further, although the steps of fig. 9 are performed in the specified order, those skilled in the art may modify the order between the steps without departing from the spirit of the application and thus the application is not limited to using only the order as described above. Furthermore, one skilled in the art may integrate several steps into one step or perform more steps in addition to these steps, sequentially or in parallel, and the application should not be limited thereby.

The above description is only of the preferred embodiments of the present application, but not limited thereto, and any person skilled in the art can make further modifications and variations without departing from the spirit and scope of the present application, and the scope of the present application is defined by the appended claims.

Claims

1. A method of writing data of a page group to a flash memory module, performed by a flash memory controller, the method of writing data of a page group to a flash memory module comprising:

the method comprises the steps that a host interface controller obtains user data of a page group from a host end, wherein the page group comprises a plurality of pages;

the host interface controller stores the user data of the page to a random access memory through a bus architecture, and simultaneously outputs the user data of the page to an engine through an interface, so that the engine calculates a parity check code of the page group according to the user data of the page;

a direct memory access controller obtains the parity of the page group from the engine and stores the parity of the page group to the random access memory through the bus architecture; and

the flash interface controller obtains the user data of the page and the parity of the page group from the random access memory through the bus architecture and writes the user data of the page and the parity of the page group to a flash module.

2. The method of writing data of a group of pages to a flash memory module of claim 1, wherein the host interface controller does not output the user data of the pages to the engine via the bus architecture.

3. The method of writing data of a page group to a flash memory module of claim 1, further comprising:

and after the host interface controller outputs the user data of the page group to the engine through the interface, transmitting an end confirmation signal to the direct memory access controller through the interface, wherein the end confirmation signal is used for informing the direct memory access controller to start to acquire the parity check code of the page group from the engine.

4. The method of writing data of a page group to a flash memory module of claim 1, further comprising:

the flash memory interface controller generates a first error correction code according to the user data of each page, generates a second error correction code according to the parity codes of the page group, and writes the first error correction code and the second error correction code to the flash memory module.

5. An apparatus for writing data of a page group to a flash memory module, comprising:

a bus architecture;

an engine; and

a host interface controller, comprising:

a first interface coupled to the bus architecture;

the second interface is coupled with the host end;

a third interface coupled to the engine; and

the first controller is configured to control the first controller,

the first controller drives the second interface to acquire user data of a page group from the host, wherein the page group comprises a plurality of pages; the first interface is driven to store the user data of the page to a random access memory through the bus architecture, and the third interface is driven to output the user data of the page to the engine, so that the engine calculates a parity code of the page group according to the user data of the page.

6. The apparatus for writing data of a page group to a flash memory module as recited in claim 5, further comprising:

a direct memory access controller comprising:

a fourth interface coupled to the bus architecture;

a fifth interface coupled to the engine and the host interface controller; and

a second controller is provided for controlling the operation of the first controller,

wherein the second controller drives the fifth interface to obtain the parity of the page group from the engine and drives the fourth interface to store the parity of the page group to the random access memory through the bus architecture.

7. The apparatus of claim 6, wherein the first controller outputs the user data of the page group to the flash memory module through the third interface, and transmits an end acknowledge signal to the direct memory access controller through the third interface after the completion of the outputting of the user data of the page group to the engine, for notifying the direct memory access controller to start the acquisition of the parity of the page group from the engine.

8. The apparatus for writing data of a page group to a flash memory module as recited in claim 6, further comprising:

and a flash memory interface controller coupled to the bus architecture, for obtaining the user data of the page and the parity of the page group from the random access memory through the bus architecture, and writing the user data of the page and the parity of the page group to a flash memory module.

9. The apparatus of claim 8, wherein the flash interface controller generates a first error correction code based on the user data for each of the pages, generates a second error correction code based on the parity code for the page group, and writes the first error correction code and the second error correction code to the flash module.

10. The apparatus of any of claims 5 to 9, wherein the engine does not obtain the user data of the page through the bus architecture.