CN112988449A

CN112988449A - Device and method for writing data of page group into flash memory module

Info

Publication number: CN112988449A
Application number: CN202010267832.5A
Authority: CN
Inventors: 李安邦
Original assignee: Silicon Motion Inc
Current assignee: Silicon Motion Inc
Priority date: 2019-12-16
Filing date: 2020-04-08
Publication date: 2021-06-18
Anticipated expiration: 2040-04-08
Also published as: TW202125511A; CN112988449B; TWI719880B

Abstract

The invention relates to a method and a device for writing data of a page group into a flash memory module, wherein the method for writing the data of the page group into the flash memory module comprises the following steps: the host interface controller stores user data of a plurality of pages in a random access memory through a bus architecture, and simultaneously outputs the user data of the pages to an engine through an interface, so that the engine calculates parity codes of the page groups according to the user data of the pages, the direct memory access controller acquires the parity codes of the page groups from the engine and stores the parity codes of the page groups in the random access memory through the bus architecture, and the flash memory interface controller acquires the user data of the pages and the parity codes of the page groups from the random access memory through the bus architecture and writes the user data of the pages and the parity codes of the page groups in the flash memory module. Thus, the time and computational resources required to generate parity codes for a group of pages are reduced.

Description

Device and method for writing data of page group into flash memory module

Technical Field

The present invention relates to a memory device, and more particularly, to a device and method for writing data of a page group into a flash memory module.

Background

Flash memories are generally classified into NOR flash memories and NAND flash memories. NOR flash is a random access device and a central processing unit (Host) may provide any address on an address pin to access NOR flash and obtain data stored at the address from a data pin of NOR flash in a timely manner. In contrast, NAND flash memory is not random access, but serial access. NAND flash does not have access to any random address, as NOR flash does cpu need to write serial byte (Bytes) values to NAND flash for defining the type of Command (Command) (e.g., read, write, erase, etc.) and the address used on the Command. The address may point to one page (the smallest data block for a write operation in flash memory) or one block (the smallest data block for an erase operation in flash memory).

Flash controllers typically use Error Correcting Codes (ECC) to repair errors that occur when user data is passed through a channel or stored. During data writing, the flash memory controller encodes the user data to generate redundant information of the error correction code. This redundancy allows the flash controller to correct a limited number of erroneous bits occurring anywhere in the user data during a data read without the need for re-reading. In order to prevent the user data of the read Page from having more error bits than the error correction code can correct, the flash memory controller may make a default number of pages form a Page Group (Page Group), and generate the parity of the Page Group according to the user data of the Page Group. However, since the calculation of the parity of the page group is a data calculation operation across pages, it takes a lot of time and calculation resources. Therefore, the present invention provides an apparatus and method for writing data of a page group into a flash memory module, which is used to reduce the time and computational resources required for generating parity codes of the page group.

Disclosure of Invention

In view of the above, it is a problem to be solved how to alleviate or eliminate the above-mentioned drawbacks of the related art.

The invention relates to a method for writing data of a page group into a flash memory module, which is executed by a flash memory controller and comprises the following steps: the method comprises the steps that a host interface controller obtains user data of a page group from a host end, wherein the page group comprises a plurality of pages; the host interface controller stores the user data of the page to the random access memory through the bus architecture, and simultaneously outputs the user data of the page to the engine through the interface, so that the engine calculates the parity check code of the page group according to the user data of the page; the direct memory access controller acquires the parity check code of the page group from the engine and stores the parity check code of the page group to the random access memory through the bus architecture; and the flash memory interface controller acquires the user data of the page and the parity of the page group from the random access memory through the bus architecture, and writes the user data of the page and the parity of the page group into the flash memory module.

The invention also relates to a device for writing data of a page group into a flash memory module, comprising: a bus architecture; an engine; and a host interface controller. The host interface controller comprises a first interface coupled with the bus architecture; the second interface is coupled with the host end; a third interface coupled to the engine; and a controller. The controller drives the second interface to obtain user data of a page group from the host, wherein the page group comprises a plurality of pages; the first interface is driven to store the user data of the page to the random access memory through the bus architecture, and the third interface is driven to output the user data of the page to the engine at the same time, so that the engine calculates the parity check code of the page group according to the user data of the page.

One of the advantages of the above embodiments is that by directly outputting the user data of the page to the engine for the calculation of the parity as described above using the host interface controller, the time for the engine to read the user data of the page from the random access memory through the bus architecture can be saved.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application.

FIG. 1 shows a logical data organization of a page, a parity page, and its error correction code.

Fig. 2 is a system architecture diagram of an electronic device of some embodiments.

FIG. 3 is a diagram illustrating the generation and writing of user data and parity thereof based on a page group under the system architecture of FIG. 2.

Fig. 4 is an operation sequence diagram based on the execution steps shown in fig. 3.

Fig. 5 is a system architecture diagram of an electronic device according to an embodiment of the invention.

FIG. 6 is a diagram illustrating the interfacing of components in a flash memory controller according to an embodiment of the present invention.

FIG. 7 is a timing diagram illustrating the transfer of multiple pages of user data from a host interface controller to a RAID engine according to embodiments of the present invention.

FIG. 8 is a timing diagram illustrating the transmission of parity for a group of pages from a RAID error correction code engine to a DMA controller according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating the generation and writing of user data and parity thereof based on a page group under the system architecture of FIG. 5.

Wherein the symbols in the drawings are briefly described as follows:

10. 50: an electronic device; 110: a host end; 130: a flash memory controller; 131: a host interface controller; 132: a bus architecture; 134: a processing unit; 135: a direct memory access controller; 136: a random access memory; 137: an error correction code engine of a redundant array of independent disks; 139: a flash memory interface controller; 150: a flash memory module; 530: a flash memory controller; 531: a host interface controller; 535: a direct memory access controller; 537: an error correction code engine of a redundant array of independent disks; 610. 650, 673, 677: an interface.

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals indicate the same or similar components or process flows.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of further features, integers, steps, operations, elements, components, and/or groups thereof.

The use of words such as "first," "second," "third," etc. in this disclosure is intended to modify a component in a claim and is not intended to imply a priority order, precedence relationship, or order between components or steps in a method.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between components may also be interpreted in a similar manner, e.g., "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

In order to achieve data fault tolerance, the flash memory controller may generate an Error Correction Code (ECC) according to the user data of each page, and write the user data into the flash memory module together with the ECC, so that the user data read from the flash memory module and containing Error bits can be corrected in the future. The error correcting Code may be a Low-Density Parity Check Code (LDPC), BCH Code (Bose-Chaudhuri-Hocquenghem Code), or other kind of Code. Taking every 1 kbyte of user data as an example, BCH codes can provide a correction capability of up to 72 error bits, while LDPC codes can provide a correction capability of up to 128 error bits. However, the user data of the read page may contain more error bits than the error correction code can correct back. Therefore, the flash controller may form a Page Group with a default number of pages, and generate Parity pages (Parity pages) according to the user data of the Page Group. Referring to the data organization of the example shown in FIG. 1, seven pages P #0 through P #6 form a group of pages, each containing 4096 bits of user data and from which a corresponding ECC is generated. For example, the error correction code for page 0, P #0, is ECC #0, the error correction code for page 1, P #1, is ECC #1, and so on. It is noted here that the example shown in fig. 1 is a logical view and user data and its error correction code, parity pages and their error correction code, which do not represent a group of pages, are actually stored in the same physical block. In order to optimize system performance, the user data page and its error correction code, the parity page and its error correction code of a page group may be stored in parallel in physical blocks of multiple Logical Unit Numbers (LUNs) in different channels, and the invention is not limited thereto. The data for a parity code page may be generated using equation (1):

P_j＝d_p0,j⊕d_p1,j⊕d_p2,j⊕d_p3,j⊕d_p4,j⊕d_p5,j⊕d_p6,j，

wherein j is any integer from 0 to 4095, p0 represents page 0, p1 represents page 1, p2 represents page 2, and so on; p_jA value representing the jth bit in the parity code page; d_p0,jRepresenting the value of the jth bit in page 0, d_p1,jRepresenting the value of the jth bit in page 1, d_p2,jRepresenting the value of the jth bit in page 2, and so on. When the error bits in a page cannot be corrected by using the corresponding error correction code of the page, the flash memory controller may discard the page and generate the user data of the repaired page by using exclusive-or operation according to the contents of other pages in the page group and the parity page. Assuming that the error bits in page 1 cannot be corrected using the corresponding error correction code, the recovery of the error page can be performed using equation (2):

d_p1,j＝d_p0,j⊕d_p2,j⊕d_p3,j⊕d_p4,j⊕d_p5,j⊕d_p6,j⊕P_j。

the parity codes for a group of pages may also be referred to as Redundant Array of Independent Disks (RAID ECC) codes, depending on their role.

To accomplish the two-dimensional protection described above, fig. 2 shows the system architecture of some embodiments. The electronic Device 10 includes a Host Side (Host Side)110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 may be collectively referred to as a Device Side (Device Side). The electronic device 10 may be implemented in a personal computer, a notebook computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera, and other electronic products. Host Interface Controller (Host Interface Controller)131 of Host 110 and Flash Controller 130 may communicate with each other via a communication protocol such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Memory Storage (UFS), Non-Volatile Memory (NVMe), Embedded multimedia Card (mc), and so on. Flash Interface Controller (Flash Interface Controller)139 of Flash Controller 130 and Flash module 150 may communicate with each other in a Double Data Rate (DDR) communication protocol, such as Open NAND Flash Interface (ONFI), Double Data Rate switch (DDR Toggle), or other communication protocol. Flash controller 130 includes a processing unit 134 that may be implemented in a variety of ways, such as using general purpose hardware (e.g., a single processor, a plurality of processors with parallel processing capabilities, a graphics processor, or other processor with computing capabilities) and providing the functionality described hereinafter when executing software and/or firmware instructions. The processing unit 134 receives host commands, such as a Read Command (Read Command), a Write Command (Write Command), an Erase Command (Erase Command), and the like, through the host interface controller 131, and schedules and executes the commands. The flash Memory controller 130 further includes a Random Access Memory (RAM) 136, which may be implemented as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or a combination thereof, and is configured to configure a space as a data buffer, store user data (also referred to as host data) read from the host 110 and to be written into the flash Memory module 150, parity codes, etc., store user data read from the flash Memory module 150 and to be output to the host 110, and store ECC, parity codes, etc., read from the flash Memory module 150 and used for data repair. The ram136 may further store data required during execution, such as variables, data tables, Host-to-Flash (H2F Table), Flash-Host (F2H Table), and the like. The Flash interface Controller 139 includes a NAND Flash Controller (NFC) and provides functions required for accessing the Flash module 150, such as a Command serializer (Command sequence), an ECC encoder, and an ECC decoder. The ECC encoder is used for generating corresponding ECC according to the content of one user data page or RAID ECC page.

The flash controller 130 may be configured with a Bus Architecture (Bus Architecture)132 for coupling components to transfer data, addresses, control signals, etc. including a host interface controller 131, a processing unit 134, a RAM136, a Direct Memory Access (DMA) controller 135, and a flash interface controller 139. In some embodiments, host interface controller 131, processing unit 134, RAM136, DMA controller 135, and flash interface controller 139 may be coupled to each other via a single bus. In other embodiments, flash controller 130 may be configured with a high speed bus for coupling processing unit 134, DMA controller 135, and RAM136 to each other, and a low speed bus for coupling processing unit 134, DMA controller 135, host interface controller 131, and flash interface controller 139 to each other. The bus comprises parallel physical lines connecting more than two components of the flash controller 130. A bus is a shared transmission medium, and only two devices can use these lines to communicate with each other for transferring data at any one time. Data and control signals can propagate bi-directionally between components along data and control lines, respectively, but address signals can only propagate uni-directionally along address lines, on the other hand. For example, when processing unit 134 wants to read data at a particular address of RAM136, processing unit 134 transfers that address on an address line to RAM 136. The data at this address is then returned to processing unit 134 over the data lines. To complete the data read operation, the control signals are passed using the control lines.

Flash controller 130 may include a RAID ECC engine 137 including exclusive OR gates and registers for performing the operations described above in equation (1), equation (2), or the like. DMA controller 135 may include an Instruction Queue (Instruction Queue). Processing unit 134 may issue data access instructions to DMA controller 135 via bus architecture 132, and DMA controller 135 may store the instructions in an instruction queue according to the arrival time. Each data access instruction may include information such as a source component, a source address, a destination component, a destination address, etc. The DMA controller 135 migrates the designated data among the components via the bus structure 132 according to the data access command, for example, reads the data with a specific address and length in the RAM136 and inputs the data to the RAID ECC engine 137, stores the parity generated by the RAID ECC engine 137 to the specific address in the RAM136, and so on.

The flash memory module 150 provides a large amount of storage space, typically hundreds of Gigabytes (GB), or even Terabytes (TB), for storing large amounts of user data, such as high resolution pictures, movies, and the like. The flash memory module 150 includes a control circuit and a memory array, and the memory Cells in the memory array may include Single Level Cells (SLCs), Multiple Level Cells (MLCs), Triple Level Cells (TLCs), Quad-Level Cells (QLCs), or any combination thereof. The processing unit 134 writes user data to a specified address (destination address) in the flash memory module 150 through the flash interface controller 139, and reads user data from a specified address (source address) in the flash memory module 150. Flash interface controller 139 uses a plurality of electrical signals to coordinate the Data and command transfers between flash controller 130 and flash module 150, including Data Line (Data Line), clock signal (clock signal) and control signal (control signal). The data lines can be used for transmitting commands, addresses, read-out and written-in data; the control signal line may be used to transmit control signals such as Chip Enable (CE), Address fetch Enable (ALE), Command fetch Enable (CLE), Write Enable (WE), and the like.

However, the architecture of the above-described embodiment may cause the DMA controller 135 to wait for the host interface controller 131 to store a page of user data to the specified address of the RAM136 before reading the page of user data from the specified address of the RAM136 and inputting the page of user data to the RAID ECC engine 137. In detail, refer to the steps shown in fig. 3.

Step (1): the host interface controller 131 obtains the user data of a page from the host 110 and stores the user data of the page to a designated address in the RAM 136.

Step (2): the DMA controller 135 reads one page of user data from a specified address in the RAM136 and inputs to the RAID ECC engine 137. Steps (1) and (2) are continuously executed in the flash controller 130 in a loop until all the user data of a page group is input to the RAID ECC engine 137 for operation.

And (3): the DMA controller 135 takes the parity for this group of pages from the RAID ECC engine 137 and stores it to the specified address of the RAM 136.

And (4): the flash interface controller 139 reads the user data for these pages and the parity for the group of pages from the specified address in RAM136 and writes to the flash module 150.

The execution of step (1) and step (2) needs to wait each other, lengthening the data writing time. Referring to FIG. 4, for example, an operation P #1(W) in which the host interface controller 131 writes page 1 user data to the RAM136 requires a read operation P #0(R) waiting for the DMA controller 135 to read page 0 user data from the RAM136, a read operation P #1(R) in which the DMA controller 135 reads page 1 user data from the RAM136 requires an operation P #1(W) waiting for the host interface controller 131 to write page 1 user data to the RAM136, and so on. In addition, since the host interface controller 131 and the DMA controller 135 need to compete for the control right of the bus architecture 132, the lead time (e.g., time interval ts shown in FIG. 4) between step (1) and step (2) may be further lengthened because other components (e.g., the processing unit 134, the flash memory interface controller 139, etc.) occupy the resources of the bus architecture 132.

In order to solve the problems of the above embodiments, the embodiment of the present invention provides a new flash controller, which modifies the interface settings among the host interface controller 131, the DMA controller 135 and the RAID ECC engine 137, so as to avoid the DMA controller 135 occupying the resources of the bus architecture 132 to read the user data of the page group from the RAM136 and input the user data to the RAID ECC engine 137. Referring to the electronic device 50 shown in fig. 5, the host interface controller 531 and the RAID ECC engine 537 add an interface for interconnecting, so that after the host interface controller 531 obtains a page of user data from the host 110, the host interface controller 531 stores the page of user data to a specified address in the RAM136 through the bus structure 132, and simultaneously transmits the page of user data to the RAID ECC engine 537 through a newly configured interface. After the host interface controller 531 transfers the user data of a page group to the RAID ECC engine 537, it sends a control signal to the DMA controller 535, so that the DMA controller 535 obtains the parity of the page group from the RAID ECC engine 537 and stores the parity to the specified address of the RAM136 through the bus structure 132.

Refer to the interfacing schematic of fig. 6. The RAID ECC engine 537 is provided with an interface 673, connected to the interface 610 in the host interface controller 531, for obtaining the user data of each page in the page group directly from the host interface controller 531 for encoding the parity of the page group, without obtaining from the RAM136 through any DMA controller. Before starting the data transfer, the host interface controller 531 may enter an initialization phase, informing the RAID ECC engine 537 via the interface 610 how many pages each group of pages contains, the operation mode, etc. In conjunction with the timing diagram of fig. 7, in detail, for the total number of pages of a page group, the RAID ECC engine 537 may assert a Set RAID Ready Signal (Set _ RAID _ rdy) for a period of time t71, informing the host interface controller 531 that the total number of pages may be Set during the period of time. During the period t71, the host interface controller 531 may put the total number of pages on the Group capacity Data Lines (grp _ Size [2:0]) and generate a square wave on the Set engine Pulse Signal (Set _ RAID _ pls) for the RAID ECC engine 537 to extract the total number of pages of the page Group on the Group capacity Data Lines on the rising edge of the square wave and store the total number of pages in the register. For the operational Mode setting, the RAID ECC engine 537 may assert a Set Mode Ready Signal (Set _ Mode _ rdy) for a period of time t73, informing the host interface controller 531 that the operational Mode may be Set during this period. During the period t73, the host interface controller 531 may place the Operation Mode (e.g., encoding Mode 0) on the Operation Mode Data Lines (op _ Mode [1:0]) and generate a square wave on the Set Mode Pulse Signal (Set _ Mode _ pls) for the RAID ECC engine 537 to extract the indicated Operation Mode on the Operation Mode Data Lines at the rising edge of the square wave and store the Operation Mode in the register.

After the initialization phase is completed, the RAID ECC engine 537 may assert an Encode Ready Signal (enc _ rdy) until user data of one page group is received (e.g., period t75) for notifying the host interface controller 531 that the user data may be transferred during the assertion period. The host interface controller 531 may assert an Encode enable Signal (enc _ en) until the user data of the last page is transferred (e.g., period t 77). During period t77, the host interface controller 531 may place each page of user Data on the encoded Data Lines (Encode Data Lines, enc _ dat [63:0]) along with a Clock Signal (Clock Signal, not shown in FIG. 7) for the RAID ECC engine 537 to fetch. The RAID ECC engine 537 may calculate the extracted user data using equation (1) to generate a parity code for the group of pages. The host interface controller 531 may contain a transfer counter, which is initially 0 and is incremented by 1 after the user data of one page has been transferred. When the value of the transfer counter equals to the total number of pages in the page group, the host interface controller 531 asserts a Termination Valid Signal (term _ Valid) for a period of time to notify the DMA controller 535 that the parity of the page group can be obtained from the RAID ECC engine 537 and stored in the specified address of the RAM136 via the bus structure 132.

During the initialization phase, a controller (not shown in fig. 5 and 6) in the RAID ECC engine 537 may drive the interface 673 to assert the set engine ready signal for a period of time and the set mode ready signal for a period of time. A controller (not shown in fig. 5 and 6) in the host interface controller 531 may drive the interface 610 to detect a set engine ready signal, place the total number of pages on the group capacity data line, generate a square wave on the set engine pulse signal, detect a set mode ready signal, place the operation mode on the operation mode data line, and generate a square wave on the set engine pulse signal.

During the data transfer phase, a controller (not shown in fig. 5 and 6) in the RAID ECC engine 537 may drive the interface 673 to assert the encode ready signal for a period of time. A controller (not shown in fig. 5 and 6) in the host interface controller 531 may drive the interface 610 to assert the encode enable signal for a period of time, place user data for each page on the encoded data lines, and assert the end acknowledge signal for a period of time.

It should be noted that the host interface controller 531 may further provide a first interface (not shown in fig. 5 and 6) connected to the host end 110 and a second interface (not shown in fig. 5 and 6) connected to the bus architecture 132. A controller (not shown in fig. 5 and 6) in the host Interface controller 531 may drive the first Interface to acquire user data of each page from the host end 110 using a communication protocol, and drive the second Interface to acquire control authority of the bus fabric 132 using an Advanced eXtensible Interface (AXI) communication protocol, and store the user data of each page to a designated address in the RAM136 through the bus fabric 132. The circuit structures and functions of the controller, the first interface and the second interface in the host interface controller 531 are well known in the art, and are not described in detail for brevity.

Refer to the interfacing schematic of fig. 6. RAID ECC engine 537 provides an interface 677 coupled to interface 650 in DMA controller 535 for outputting the parity of the group of pages to DMA controller 535. In conjunction with the timing diagram of fig. 8, in detail, when the DMA controller 535 receives the end confirmation signal, the DMA controller 535 may validate the end Out Valid signal (Termination Out Valid) until the parity of the page group is received (e.g., the period t81), so as to inform the RAID ECC engine 537 that the parity of the page group may be transmitted during validation. The RAID ECC engine 537 may assert a Termination Out initialization Signal (term _ Out _ en) until the parity of the page group is transferred (e.g., period t 83). During period t83, RAID ECC engine 537 may place the Parity of the page group on the end output Parity Data line (Termination Out Parity Data Lines, term _ Out _ pty [63:0]) along with a Clock Signal (not shown in FIG. 7) for DMA controller 535 to fetch.

During the parity code transfer phase, a controller (not shown in FIGS. 5 and 6) in DMA controller 535 may drive interface 650 to detect the end _ ack signal and assert the end _ valid signal for a period of time. A controller (not shown in fig. 5 and 6) in RAID ECC engine 537 may drive interface 677 to assert the end output enable signal for a period of time and place the parity of the group of pages on the end output parity data lines.

It is noted that the DMA controller 535 may alternatively be provided with an interface (not shown in FIGS. 5 and 6) to the bus architecture 132. A controller (not shown in fig. 5 and 6) in DMA controller 535 may drive the interface to use the advanced extensible interface communication protocol to gain control of bus architecture 132 and store the parity of the group of pages via bus architecture 132 to the specified address in RAM 136. The circuit structure and function of the controller and the interface in the DMA controller 535 are well known in the art, and are not described in detail for brevity.

In detail, reference is made to the steps shown in fig. 9 according to the architecture of the embodiment of the present invention.

And (5): the host interface controller 531 obtains a page of user data from the host 110, stores the page of user data in the RAM136 at a designated address through the bus structure 132, and outputs the page of user data to the RAID ECC engine 537 for encoding through the interface 610. Step (5) is continuously executed in the flash controller 530 in a loop until all the user data of a page group is inputted to the RAID ECC engine 537 for operation.

And (6): the host interface controller 531 sends an end acknowledge signal to the DMA controller 535 via the interface 610 informing the DMA controller 535 that the DMA controller 535 may start to fetch the parity codes for the page group from the RAID ECC engine 537.

And (7): the DMA controller 535 retrieves the parity code for this group of pages from the RAID ECC engine 537 via the interface 650 and stores it to the specified address of the RAM136 via the bus fabric 132.

And (8): the flash interface controller 139 reads the user data for these pages and the parity for the group of pages from the specified address in RAM136 and writes to the flash module 150. The flash interface controller 139 may also generate an error correction code according to the user data of each page, generate an error correction code according to the parity of the group of pages, and write the error correction code of each page and the error correction code of the parity into the flash memory module 150.

Compared to the timing diagram of FIG. 4 corresponding to the previous embodiment, the new architecture of the present invention can save the read operations P #0(R) to P #6(R) from multiple pages of the RAM136 of the DMA controller 135 designed previously, and can also avoid collisions between other components and the DMA controller 135 caused by contention for control of the bus structure 132, and avoid the lead time required by other components to wait for the completion of the read operations P #0(R) to P #6 (R).

Although fig. 5-6 and 9 include the above-described components, it is not excluded that more additional components may be used to achieve better technical results without departing from the spirit of the present invention. Further, although the steps of fig. 9 are performed in a specified order, a person skilled in the art may modify the order between the steps to achieve the same result without departing from the spirit of the invention, and therefore, the invention is not limited to use of only the order as described above. In addition, a person skilled in the art may also integrate several steps into one step, or perform more steps in sequence or in parallel besides these steps, and the present invention should not be limited thereby.

The above description is only for the preferred embodiment of the present invention, and it is not intended to limit the scope of the present invention, and any person skilled in the art can make further modifications and variations without departing from the spirit and scope of the present invention, therefore, the scope of the present invention should be determined by the claims of the present application.

Claims

1. A method for writing data of a group of pages to a flash memory module, performed by a flash memory controller, the method comprising:

the method comprises the steps that a host interface controller obtains user data of a page group from a host end, wherein the page group comprises a plurality of pages;

the host interface controller stores the user data of the page to a random access memory through a bus architecture, and simultaneously outputs the user data of the page to an engine through an interface, so that the engine calculates the parity check code of the page group according to the user data of the page;

a direct memory access controller obtaining the parity codes for the group of pages from the engine and storing the parity codes for the group of pages to the random access memory over the bus architecture; and

the flash memory interface controller obtains the user data of the page and the parity of the page group from the random access memory through the bus architecture, and writes the user data of the page and the parity of the page group to a flash memory module.

2. The method of writing data of a group of pages to a flash memory module of claim 1 wherein said host interface controller does not output said user data of said pages to said engine over said bus architecture.

3. The method of claim 1, further comprising:

and after the host interface controller outputs the user data of the page group to the engine through the interface, transmitting an end confirmation signal to the direct storage access controller through the interface, wherein the end confirmation signal is used for informing the direct storage access controller to start acquiring the parity check code of the page group from the engine.

4. The method of claim 1, further comprising:

the flash memory interface controller generates a first error correction code according to the user data of each of the pages, generates a second error correction code according to the parity of the group of pages, and writes the first error correction code and the second error correction code to the flash memory module.

5. An apparatus for writing data of a group of pages to a flash memory module, comprising:

a bus architecture;

an engine; and

a host interface controller, comprising:

a first interface coupled to the bus architecture;

the second interface is coupled with the host end;

a third interface coupled to the engine; and

a first controller for controlling the operation of the first switch,

the first controller drives the second interface to obtain user data of a page group from the host, wherein the page group comprises a plurality of pages; driving the first interface to store the user data of the page to a random access memory through the bus architecture, while driving the third interface to output the user data of the page to the engine, such that the engine calculates a parity of the group of pages from the user data of the page.

6. The apparatus for writing data of a group of pages to a flash memory module of claim 5 further comprising:

a direct memory access controller, comprising:

a fourth interface coupled to the bus architecture;

a fifth interface coupling the engine and the host interface controller; and

a second controller for controlling the operation of the display device,

wherein the second controller drives the fifth interface to retrieve the parity for the group of pages from the engine and drives the fourth interface to store the parity for the group of pages to the random access memory over the bus architecture.

7. The apparatus of claim 6, wherein the first controller transmits an end acknowledge signal to the DMA controller via the third interface after outputting the user data of the page group to the engine via the third interface, for informing the DMA controller to start retrieving the parity of the page group from the engine.

8. The apparatus for writing data of a group of pages to a flash memory module of claim 6, further comprising:

a flash interface controller, coupled to the bus fabric, obtaining the user data of the page and the parity of the page group from the random access memory through the bus fabric, and writing the user data of the page and the parity of the page group to a flash memory module.

9. The apparatus of claim 8, wherein the flash interface controller generates a first error correction code based on the user data for each of the pages, generates a second error correction code based on the parity codes for the group of pages, and writes the first error correction code and the second error correction code to the flash module.

10. The apparatus for writing data of a group of pages to a flash memory module according to any of claims 5 to 9, wherein said engine does not obtain said user data of said pages through said bus architecture.